2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_defines.h"
27 #include "brw_context.h"
28 #include "main/compiler.h"
30 #include "program/prog_parameter.h"
33 #include "brw_ir_allocator.h"
38 #define MAX_SAMPLER_MESSAGE_SIZE 11
39 #define MAX_VGRF_SIZE 16
41 enum PACKED register_file
{
46 HW_REG
, /* a struct brw_reg */
48 UNIFORM
, /* prog_data->params[reg] */
56 bool is_negative_one() const;
58 bool is_accumulator() const;
59 bool in_range(const backend_reg
&r
, unsigned n
) const;
62 enum register_file file
; /**< Register file: GRF, MRF, IMM. */
63 enum brw_reg_type type
; /**< Register type: BRW_REGISTER_TYPE_* */
68 * For GRF, it's a virtual register number until register allocation.
70 * For MRF, it's the hardware register.
75 * Offset within the virtual register.
77 * In the scalar backend, this is in units of a float per pixel for pre-
78 * register allocation registers (i.e., one register in SIMD8 mode and two
79 * registers in SIMD16 mode).
81 * For uniforms, this is in units of 1 float.
85 struct brw_reg fixed_hw_reg
;
95 struct backend_instruction
: public exec_node
{
99 bool is_control_flow() const;
100 bool is_commutative() const;
101 bool can_do_source_mods() const;
102 bool can_do_saturate() const;
103 bool can_do_cmod() const;
104 bool reads_accumulator_implicitly() const;
105 bool writes_accumulator_implicitly(const struct brw_device_info
*devinfo
) const;
107 void remove(bblock_t
*block
);
108 void insert_after(bblock_t
*block
, backend_instruction
*inst
);
109 void insert_before(bblock_t
*block
, backend_instruction
*inst
);
110 void insert_before(bblock_t
*block
, exec_list
*list
);
113 * True if the instruction has side effects other than writing to
114 * its destination registers. You are expected not to reorder or
115 * optimize these out unless you know what you are doing.
117 bool has_side_effects() const;
120 * True if the instruction might be affected by side effects of other
123 bool is_volatile() const;
125 struct backend_instruction
{
126 struct exec_node link
;
129 * Annotation for the generated IR. One of the two can be set.
132 const char *annotation
;
135 uint32_t offset
; /**< spill/unspill offset or texture offset bitfield */
136 uint8_t mlen
; /**< SEND message length */
137 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
138 uint8_t target
; /**< MRT target. */
139 uint8_t regs_written
; /**< Number of registers written by the instruction. */
141 enum opcode opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
142 enum brw_conditional_mod conditional_mod
; /**< BRW_CONDITIONAL_* */
143 enum brw_predicate predicate
;
144 bool predicate_inverse
:1;
145 bool writes_accumulator
:1; /**< instruction implicitly writes accumulator */
146 bool force_writemask_all
:1;
150 bool shadow_compare
:1;
152 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
153 * mod and predication.
155 unsigned flag_subreg
:1;
157 /** The number of hardware registers used for a message header. */
163 enum instruction_scheduler_mode
{
165 SCHEDULE_PRE_NON_LIFO
,
170 struct backend_shader
{
173 backend_shader(const struct brw_compiler
*compiler
,
176 const nir_shader
*shader
,
177 struct brw_stage_prog_data
*stage_prog_data
);
181 const struct brw_compiler
*compiler
;
182 void *log_data
; /* Passed to compiler->*_log functions */
184 const struct brw_device_info
* const devinfo
;
185 const nir_shader
*nir
;
186 struct brw_stage_prog_data
* const stage_prog_data
;
188 /** ralloc context for temporary data used during compile */
192 * List of either fs_inst or vec4_instruction (inheriting from
193 * backend_instruction)
195 exec_list instructions
;
199 gl_shader_stage stage
;
201 const char *stage_name
;
202 const char *stage_abbrev
;
204 brw::simple_allocator alloc
;
206 virtual void dump_instruction(backend_instruction
*inst
) = 0;
207 virtual void dump_instruction(backend_instruction
*inst
, FILE *file
) = 0;
208 virtual void dump_instructions();
209 virtual void dump_instructions(const char *name
);
211 void calculate_cfg();
212 void invalidate_cfg();
214 virtual void invalidate_live_intervals() = 0;
217 uint32_t brw_texture_offset(int *offsets
, unsigned num_components
);
219 void brw_setup_image_uniform_values(gl_shader_stage stage
,
220 struct brw_stage_prog_data
*stage_prog_data
,
221 unsigned param_start_index
,
222 const gl_uniform_storage
*storage
);
225 struct backend_shader
;
226 #endif /* __cplusplus */
228 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type
*type
);
229 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op
);
230 uint32_t brw_math_function(enum opcode op
);
231 const char *brw_instruction_name(enum opcode op
);
232 bool brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
233 bool brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
234 bool brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
);
236 bool opt_predicated_break(struct backend_shader
*s
);
243 * Scratch data used when compiling a GLSL geometry shader.
245 struct brw_gs_compile
247 struct brw_gs_prog_key key
;
248 struct brw_vue_map input_vue_map
;
250 unsigned control_data_bits_per_vertex
;
251 unsigned control_data_header_size_bits
;
254 struct brw_compiler
*
255 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
258 brw_assign_common_binding_table_offsets(gl_shader_stage stage
,
259 const struct brw_device_info
*devinfo
,
260 const struct gl_shader_program
*shader_prog
,
261 const struct gl_program
*prog
,
262 struct brw_stage_prog_data
*stage_prog_data
,
263 uint32_t next_binding_table_offset
);
265 bool brw_vs_precompile(struct gl_context
*ctx
,
266 struct gl_shader_program
*shader_prog
,
267 struct gl_program
*prog
);
268 bool brw_gs_precompile(struct gl_context
*ctx
,
269 struct gl_shader_program
*shader_prog
,
270 struct gl_program
*prog
);
271 bool brw_fs_precompile(struct gl_context
*ctx
,
272 struct gl_shader_program
*shader_prog
,
273 struct gl_program
*prog
);
274 bool brw_cs_precompile(struct gl_context
*ctx
,
275 struct gl_shader_program
*shader_prog
,
276 struct gl_program
*prog
);
278 int type_size_scalar(const struct glsl_type
*type
);
279 int type_size_vec4(const struct glsl_type
*type
);
281 bool is_scalar_shader_stage(const struct brw_compiler
*compiler
, int stage
);