src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "brw_context.h"
  28 #include "main/compiler.h"
  29 #include "glsl/ir.h"
  30 #include "program/prog_parameter.h"
  31
  32 #ifdef __cplusplus
  33 #include "brw_ir_allocator.h"
  34 #endif
  35
  36 #pragma once
  37
  38 #define MAX_SAMPLER_MESSAGE_SIZE 11
  39 #define MAX_VGRF_SIZE 16
  40
  41 enum PACKED register_file {
  42    ARF,
  43    FIXED_GRF,
  44    MRF,
  45    IMM,
  46    VGRF,
  47    ATTR,
  48    UNIFORM, /* prog_data->params[reg] */
  49    BAD_FILE,
  50 };
  51
  52 #ifdef __cplusplus
  53 struct backend_reg : public brw_reg
  54 {
  55    backend_reg() {}
  56    backend_reg(struct brw_reg reg) : brw_reg(reg) {}
  57
  58    bool is_zero() const;
  59    bool is_one() const;
  60    bool is_negative_one() const;
  61    bool is_null() const;
  62    bool is_accumulator() const;
  63    bool in_range(const backend_reg &r, unsigned n) const;
  64
  65    enum register_file file; /**< Register file: VGRF, MRF, IMM. */
  66
  67    /**
  68     * Offset within the virtual register.
  69     *
  70     * In the scalar backend, this is in units of a float per pixel for pre-
  71     * register allocation registers (i.e., one register in SIMD8 mode and two
  72     * registers in SIMD16 mode).
  73     *
  74     * For uniforms, this is in units of 1 float.
  75     */
  76    uint16_t reg_offset;
  77 };
  78 #endif
  79
  80 struct cfg_t;
  81 struct bblock_t;
  82
  83 #ifdef __cplusplus
  84 struct backend_instruction : public exec_node {
  85    bool is_3src() const;
  86    bool is_tex() const;
  87    bool is_math() const;
  88    bool is_control_flow() const;
  89    bool is_commutative() const;
  90    bool can_do_source_mods() const;
  91    bool can_do_saturate() const;
  92    bool can_do_cmod() const;
  93    bool reads_accumulator_implicitly() const;
  94    bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
  95
  96    void remove(bblock_t *block);
  97    void insert_after(bblock_t *block, backend_instruction *inst);
  98    void insert_before(bblock_t *block, backend_instruction *inst);
  99    void insert_before(bblock_t *block, exec_list *list);
 100
 101    /**
 102     * True if the instruction has side effects other than writing to
 103     * its destination registers.  You are expected not to reorder or
 104     * optimize these out unless you know what you are doing.
 105     */
 106    bool has_side_effects() const;
 107
 108    /**
 109     * True if the instruction might be affected by side effects of other
 110     * instructions.
 111     */
 112    bool is_volatile() const;
 113 #else
 114 struct backend_instruction {
 115    struct exec_node link;
 116 #endif
 117    /** @{
 118     * Annotation for the generated IR.  One of the two can be set.
 119     */
 120    const void *ir;
 121    const char *annotation;
 122    /** @} */
 123
 124    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 125    uint8_t mlen; /**< SEND message length */
 126    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 127    uint8_t target; /**< MRT target. */
 128    uint8_t regs_written; /**< Number of registers written by the instruction. */
 129
 130    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 131    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 132    enum brw_predicate predicate;
 133    bool predicate_inverse:1;
 134    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 135    bool force_writemask_all:1;
 136    bool no_dd_clear:1;
 137    bool no_dd_check:1;
 138    bool saturate:1;
 139    bool shadow_compare:1;
 140
 141    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 142     * mod and predication.
 143     */
 144    unsigned flag_subreg:1;
 145
 146    /** The number of hardware registers used for a message header. */
 147    uint8_t header_size;
 148 };
 149
 150 #ifdef __cplusplus
 151
 152 enum instruction_scheduler_mode {
 153    SCHEDULE_PRE,
 154    SCHEDULE_PRE_NON_LIFO,
 155    SCHEDULE_PRE_LIFO,
 156    SCHEDULE_POST,
 157 };
 158
 159 struct backend_shader {
 160 protected:
 161
 162    backend_shader(const struct brw_compiler *compiler,
 163                   void *log_data,
 164                   void *mem_ctx,
 165                   const nir_shader *shader,
 166                   struct brw_stage_prog_data *stage_prog_data);
 167
 168 public:
 169
 170    const struct brw_compiler *compiler;
 171    void *log_data; /* Passed to compiler->*_log functions */
 172
 173    const struct brw_device_info * const devinfo;
 174    const nir_shader *nir;
 175    struct brw_stage_prog_data * const stage_prog_data;
 176
 177    /** ralloc context for temporary data used during compile */
 178    void *mem_ctx;
 179
 180    /**
 181     * List of either fs_inst or vec4_instruction (inheriting from
 182     * backend_instruction)
 183     */
 184    exec_list instructions;
 185
 186    cfg_t *cfg;
 187
 188    gl_shader_stage stage;
 189    bool debug_enabled;
 190    const char *stage_name;
 191    const char *stage_abbrev;
 192
 193    brw::simple_allocator alloc;
 194
 195    virtual void dump_instruction(backend_instruction *inst) = 0;
 196    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 197    virtual void dump_instructions();
 198    virtual void dump_instructions(const char *name);
 199
 200    void calculate_cfg();
 201    void invalidate_cfg();
 202
 203    virtual void invalidate_live_intervals() = 0;
 204 };
 205
 206 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
 207
 208 void brw_setup_image_uniform_values(gl_shader_stage stage,
 209                                     struct brw_stage_prog_data *stage_prog_data,
 210                                     unsigned param_start_index,
 211                                     const gl_uniform_storage *storage);
 212
 213 #else
 214 struct backend_shader;
 215 #endif /* __cplusplus */
 216
 217 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 218 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 219 uint32_t brw_math_function(enum opcode op);
 220 const char *brw_instruction_name(enum opcode op);
 221 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 222 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 223 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 224
 225 bool opt_predicated_break(struct backend_shader *s);
 226
 227 #ifdef __cplusplus
 228 extern "C" {
 229 #endif
 230
 231 /**
 232  * Scratch data used when compiling a GLSL geometry shader.
 233  */
 234 struct brw_gs_compile
 235 {
 236    struct brw_gs_prog_key key;
 237    struct brw_vue_map input_vue_map;
 238
 239    unsigned control_data_bits_per_vertex;
 240    unsigned control_data_header_size_bits;
 241 };
 242
 243 struct brw_compiler *
 244 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
 245
 246 void
 247 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
 248                                         const struct brw_device_info *devinfo,
 249                                         const struct gl_shader_program *shader_prog,
 250                                         const struct gl_program *prog,
 251                                         struct brw_stage_prog_data *stage_prog_data,
 252                                         uint32_t next_binding_table_offset);
 253
 254 bool brw_vs_precompile(struct gl_context *ctx,
 255                        struct gl_shader_program *shader_prog,
 256                        struct gl_program *prog);
 257 bool brw_gs_precompile(struct gl_context *ctx,
 258                        struct gl_shader_program *shader_prog,
 259                        struct gl_program *prog);
 260 bool brw_fs_precompile(struct gl_context *ctx,
 261                        struct gl_shader_program *shader_prog,
 262                        struct gl_program *prog);
 263 bool brw_cs_precompile(struct gl_context *ctx,
 264                        struct gl_shader_program *shader_prog,
 265                        struct gl_program *prog);
 266
 267 int type_size_scalar(const struct glsl_type *type);
 268 int type_size_vec4(const struct glsl_type *type);
 269 int type_size_vec4_times_4(const struct glsl_type *type);
 270
 271 bool is_scalar_shader_stage(const struct brw_compiler *compiler, int stage);
 272
 273 #ifdef __cplusplus
 274 }
 275 #endif