src/mesa/drivers/dri/i965/brw_state.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_STATE_H
  34 #define BRW_STATE_H
  35
  36 #include "brw_context.h"
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 enum intel_msaa_layout;
  43
  44 extern const struct brw_tracked_state brw_blend_constant_color;
  45 extern const struct brw_tracked_state brw_cc_unit;
  46 extern const struct brw_tracked_state brw_clip_unit;
  47 extern const struct brw_tracked_state brw_vs_pull_constants;
  48 extern const struct brw_tracked_state brw_tcs_pull_constants;
  49 extern const struct brw_tracked_state brw_tes_pull_constants;
  50 extern const struct brw_tracked_state brw_gs_pull_constants;
  51 extern const struct brw_tracked_state brw_wm_pull_constants;
  52 extern const struct brw_tracked_state brw_cs_pull_constants;
  53 extern const struct brw_tracked_state brw_constant_buffer;
  54 extern const struct brw_tracked_state brw_curbe_offsets;
  55 extern const struct brw_tracked_state brw_invariant_state;
  56 extern const struct brw_tracked_state brw_gs_unit;
  57 extern const struct brw_tracked_state brw_binding_table_pointers;
  58 extern const struct brw_tracked_state brw_depthbuffer;
  59 extern const struct brw_tracked_state brw_recalculate_urb_fence;
  60 extern const struct brw_tracked_state brw_sf_vp;
  61 extern const struct brw_tracked_state brw_cs_texture_surfaces;
  62 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
  63 extern const struct brw_tracked_state brw_vs_abo_surfaces;
  64 extern const struct brw_tracked_state brw_vs_image_surfaces;
  65 extern const struct brw_tracked_state brw_tcs_ubo_surfaces;
  66 extern const struct brw_tracked_state brw_tcs_abo_surfaces;
  67 extern const struct brw_tracked_state brw_tcs_image_surfaces;
  68 extern const struct brw_tracked_state brw_tes_ubo_surfaces;
  69 extern const struct brw_tracked_state brw_tes_abo_surfaces;
  70 extern const struct brw_tracked_state brw_tes_image_surfaces;
  71 extern const struct brw_tracked_state brw_gs_ubo_surfaces;
  72 extern const struct brw_tracked_state brw_gs_abo_surfaces;
  73 extern const struct brw_tracked_state brw_gs_image_surfaces;
  74 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
  75 extern const struct brw_tracked_state brw_renderbuffer_read_surfaces;
  76 extern const struct brw_tracked_state brw_texture_surfaces;
  77 extern const struct brw_tracked_state brw_wm_binding_table;
  78 extern const struct brw_tracked_state brw_gs_binding_table;
  79 extern const struct brw_tracked_state brw_tes_binding_table;
  80 extern const struct brw_tracked_state brw_tcs_binding_table;
  81 extern const struct brw_tracked_state brw_vs_binding_table;
  82 extern const struct brw_tracked_state brw_wm_ubo_surfaces;
  83 extern const struct brw_tracked_state brw_wm_abo_surfaces;
  84 extern const struct brw_tracked_state brw_wm_image_surfaces;
  85 extern const struct brw_tracked_state brw_cs_ubo_surfaces;
  86 extern const struct brw_tracked_state brw_cs_abo_surfaces;
  87 extern const struct brw_tracked_state brw_cs_image_surfaces;
  88 extern const struct brw_tracked_state brw_wm_unit;
  89
  90 extern const struct brw_tracked_state brw_psp_urb_cbs;
  91
  92 extern const struct brw_tracked_state brw_indices;
  93 extern const struct brw_tracked_state brw_index_buffer;
  94 extern const struct brw_tracked_state gen7_cs_push_constants;
  95 extern const struct brw_tracked_state gen6_binding_table_pointers;
  96 extern const struct brw_tracked_state gen6_gs_binding_table;
  97 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
  98 extern const struct brw_tracked_state gen6_sampler_state;
  99 extern const struct brw_tracked_state gen6_sol_surface;
 100 extern const struct brw_tracked_state gen6_sf_vp;
 101 extern const struct brw_tracked_state gen6_urb;
 102 extern const struct brw_tracked_state gen7_depthbuffer;
 103 extern const struct brw_tracked_state gen7_l3_state;
 104 extern const struct brw_tracked_state gen7_push_constant_space;
 105 extern const struct brw_tracked_state gen7_urb;
 106 extern const struct brw_tracked_state gen8_pma_fix;
 107 extern const struct brw_tracked_state brw_cs_work_groups_surface;
 108
 109 static inline bool
 110 brw_state_dirty(const struct brw_context *brw,
 111                 GLuint mesa_flags, uint64_t brw_flags)
 112 {
 113    return ((brw->NewGLState & mesa_flags) |
 114            (brw->ctx.NewDriverState & brw_flags)) != 0;
 115 }
 116
 117 /* brw_binding_tables.c */
 118 void brw_upload_binding_table(struct brw_context *brw,
 119                               uint32_t packet_name,
 120                               const struct brw_stage_prog_data *prog_data,
 121                               struct brw_stage_state *stage_state);
 122
 123 /* brw_misc_state.c */
 124 void brw_upload_invariant_state(struct brw_context *brw);
 125 uint32_t
 126 brw_depthbuffer_format(struct brw_context *brw);
 127
 128 uint32_t
 129 brw_convert_depth_value(mesa_format format, float value);
 130
 131 void brw_upload_state_base_address(struct brw_context *brw);
 132
 133 /* gen8_depth_state.c */
 134 void gen8_write_pma_stall_bits(struct brw_context *brw,
 135                                uint32_t pma_stall_bits);
 136
 137 /***********************************************************************
 138  * brw_state.c
 139  */
 140 void brw_upload_render_state(struct brw_context *brw);
 141 void brw_render_state_finished(struct brw_context *brw);
 142 void brw_upload_compute_state(struct brw_context *brw);
 143 void brw_compute_state_finished(struct brw_context *brw);
 144 void brw_init_state(struct brw_context *brw);
 145 void brw_destroy_state(struct brw_context *brw);
 146 void brw_emit_select_pipeline(struct brw_context *brw,
 147                               enum brw_pipeline pipeline);
 148
 149 static inline void
 150 brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
 151 {
 152    if (unlikely(brw->last_pipeline != pipeline)) {
 153       assert(pipeline < BRW_NUM_PIPELINES);
 154       brw_emit_select_pipeline(brw, pipeline);
 155       brw->last_pipeline = pipeline;
 156    }
 157 }
 158
 159 /***********************************************************************
 160  * brw_program_cache.c
 161  */
 162
 163 void brw_upload_cache(struct brw_cache *cache,
 164                       enum brw_cache_id cache_id,
 165                       const void *key,
 166                       GLuint key_sz,
 167                       const void *data,
 168                       GLuint data_sz,
 169                       const void *aux,
 170                       GLuint aux_sz,
 171                       uint32_t *out_offset, void *out_aux);
 172
 173 bool brw_search_cache(struct brw_cache *cache,
 174                       enum brw_cache_id cache_id,
 175                       const void *key,
 176                       GLuint key_size,
 177                       uint32_t *inout_offset, void *inout_aux);
 178
 179 const void *brw_find_previous_compile(struct brw_cache *cache,
 180                                       enum brw_cache_id cache_id,
 181                                       unsigned program_string_id);
 182
 183 void brw_program_cache_check_size(struct brw_context *brw);
 184
 185 void brw_init_caches( struct brw_context *brw );
 186 void brw_destroy_caches( struct brw_context *brw );
 187
 188 void brw_print_program_cache(struct brw_context *brw);
 189
 190 /***********************************************************************
 191  * brw_state_batch.c
 192  */
 193 #define BRW_BATCH_STRUCT(brw, s) \
 194    intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
 195
 196 void *brw_state_batch(struct brw_context *brw,
 197                       int size, int alignment, uint32_t *out_offset);
 198 uint32_t brw_state_batch_size(struct brw_context *brw, uint32_t offset);
 199
 200 /* brw_wm_surface_state.c */
 201 void gen4_init_vtable_surface_functions(struct brw_context *brw);
 202 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
 203 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
 204 enum isl_format brw_isl_format_for_mesa_format(mesa_format mesa_format);
 205
 206 GLuint translate_tex_target(GLenum target);
 207
 208 enum isl_format translate_tex_format(struct brw_context *brw,
 209                                      mesa_format mesa_format,
 210                                      GLenum srgb_decode);
 211
 212 int brw_get_texture_swizzle(const struct gl_context *ctx,
 213                             const struct gl_texture_object *t);
 214
 215 void brw_emit_buffer_surface_state(struct brw_context *brw,
 216                                    uint32_t *out_offset,
 217                                    struct brw_bo *bo,
 218                                    unsigned buffer_offset,
 219                                    unsigned surface_format,
 220                                    unsigned buffer_size,
 221                                    unsigned pitch,
 222                                    bool rw);
 223
 224 void brw_update_texture_surface(struct gl_context *ctx,
 225                                 unsigned unit, uint32_t *surf_offset,
 226                                 bool for_gather, uint32_t plane);
 227
 228 uint32_t brw_update_renderbuffer_surface(struct brw_context *brw,
 229                                          struct gl_renderbuffer *rb,
 230                                          uint32_t flags, unsigned unit,
 231                                          uint32_t surf_index);
 232
 233 void brw_update_renderbuffer_surfaces(struct brw_context *brw,
 234                                       const struct gl_framebuffer *fb,
 235                                       uint32_t render_target_start,
 236                                       uint32_t *surf_offset);
 237
 238 /* gen7_wm_surface_state.c */
 239 void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
 240 void gen7_init_vtable_surface_functions(struct brw_context *brw);
 241
 242 /* gen8_surface_state.c */
 243
 244 void gen8_init_vtable_surface_functions(struct brw_context *brw);
 245
 246 /* brw_sampler_state.c */
 247 void brw_emit_sampler_state(struct brw_context *brw,
 248                             uint32_t *sampler_state,
 249                             uint32_t batch_offset_for_sampler_state,
 250                             unsigned min_filter,
 251                             unsigned mag_filter,
 252                             unsigned mip_filter,
 253                             unsigned max_anisotropy,
 254                             unsigned address_rounding,
 255                             unsigned wrap_s,
 256                             unsigned wrap_t,
 257                             unsigned wrap_r,
 258                             unsigned base_level,
 259                             unsigned min_lod,
 260                             unsigned max_lod,
 261                             int lod_bias,
 262                             unsigned shadow_function,
 263                             bool non_normalized_coordinates,
 264                             uint32_t border_color_offset);
 265
 266 /* gen6_surface_state.c */
 267 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 268
 269 /* brw_vs_surface_state.c */
 270 void
 271 brw_upload_pull_constants(struct brw_context *brw,
 272                           GLbitfield64 brw_new_constbuf,
 273                           const struct gl_program *prog,
 274                           struct brw_stage_state *stage_state,
 275                           const struct brw_stage_prog_data *prog_data);
 276
 277 /* gen7_vs_state.c */
 278 void
 279 gen7_upload_constant_state(struct brw_context *brw,
 280                            const struct brw_stage_state *stage_state,
 281                            bool active, unsigned opcode);
 282
 283 /* brw_clip.c */
 284 void brw_upload_clip_prog(struct brw_context *brw);
 285
 286 /* brw_sf.c */
 287 void brw_upload_sf_prog(struct brw_context *brw);
 288
 289 bool brw_is_drawing_points(const struct brw_context *brw);
 290 bool brw_is_drawing_lines(const struct brw_context *brw);
 291
 292 /* gen7_l3_state.c */
 293 void
 294 gen7_restore_default_l3_config(struct brw_context *brw);
 295
 296 static inline bool
 297 use_state_point_size(const struct brw_context *brw)
 298 {
 299    const struct gl_context *ctx = &brw->ctx;
 300
 301    /* Section 14.4 (Points) of the OpenGL 4.5 specification says:
 302     *
 303     *    "If program point size mode is enabled, the derived point size is
 304     *     taken from the (potentially clipped) shader built-in gl_PointSize
 305     *     written by:
 306     *
 307     *        * the geometry shader, if active;
 308     *        * the tessellation evaluation shader, if active and no
 309     *          geometry shader is active;
 310     *        * the vertex shader, otherwise
 311     *
 312     *    and clamped to the implementation-dependent point size range.  If
 313     *    the value written to gl_PointSize is less than or equal to zero,
 314     *    or if no value was written to gl_PointSize, results are undefined.
 315     *    If program point size mode is disabled, the derived point size is
 316     *    specified with the command
 317     *
 318     *       void PointSize(float size);
 319     *
 320     *    size specifies the requested size of a point.  The default value
 321     *    is 1.0."
 322     *
 323     * The rules for GLES come from the ES 3.2, OES_geometry_point_size, and
 324     * OES_tessellation_point_size specifications.  To summarize: if the last
 325     * stage before rasterization is a GS or TES, then use gl_PointSize from
 326     * the shader if written.  Otherwise, use 1.0.  If the last stage is a
 327     * vertex shader, use gl_PointSize, or it is undefined.
 328     *
 329     * We can combine these rules into a single condition for both APIs.
 330     * Using the state point size when the last shader stage doesn't write
 331     * gl_PointSize satisfies GL's requirements, as it's undefined.  Because
 332     * ES doesn't have a PointSize() command, the state point size will
 333     * remain 1.0, satisfying the ES default value in the GS/TES case, and
 334     * the VS case (1.0 works for "undefined").  Mesa sets the program point
 335     * mode flag to always-enabled in ES, so we can safely check that, and
 336     * it'll be ignored for ES.
 337     *
 338     * _NEW_PROGRAM | _NEW_POINT
 339     * BRW_NEW_VUE_MAP_GEOM_OUT
 340     */
 341    return (!ctx->VertexProgram.PointSizeEnabled && !ctx->Point._Attenuated) ||
 342           (brw->vue_map_geom_out.slots_valid & VARYING_BIT_PSIZ) == 0;
 343 }
 344
 345 void brw_copy_pipeline_atoms(struct brw_context *brw,
 346                              enum brw_pipeline pipeline,
 347                              const struct brw_tracked_state **atoms,
 348                              int num_atoms);
 349 void gen4_init_atoms(struct brw_context *brw);
 350 void gen45_init_atoms(struct brw_context *brw);
 351 void gen5_init_atoms(struct brw_context *brw);
 352 void gen6_init_atoms(struct brw_context *brw);
 353 void gen7_init_atoms(struct brw_context *brw);
 354 void gen75_init_atoms(struct brw_context *brw);
 355 void gen8_init_atoms(struct brw_context *brw);
 356 void gen9_init_atoms(struct brw_context *brw);
 357 void gen10_init_atoms(struct brw_context *brw);
 358
 359 void upload_gs_state_for_tf(struct brw_context *brw);
 360
 361 /* Memory Object Control State:
 362  * Specifying zero for L3 means "uncached in L3", at least on Haswell
 363  * and Baytrail, since there are no PTE flags for setting L3 cacheability.
 364  * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
 365  * may still respect that.
 366  */
 367 #define GEN7_MOCS_L3                    1
 368
 369 /* Ivybridge only: cache in LLC.
 370  * Specifying zero here means to use the PTE values set by the kernel;
 371  * non-zero overrides the PTE values.
 372  */
 373 #define IVB_MOCS_LLC                    (1 << 1)
 374
 375 /* Baytrail only: snoop in CPU cache */
 376 #define BYT_MOCS_SNOOP                  (1 << 1)
 377
 378 /* Haswell only: LLC/eLLC controls (write-back or uncached).
 379  * Specifying zero here means to use the PTE values set by the kernel,
 380  * which is useful since it offers additional control (write-through
 381  * cacheing and age).  Non-zero overrides the PTE values.
 382  */
 383 #define HSW_MOCS_UC_LLC_UC_ELLC         (1 << 1)
 384 #define HSW_MOCS_WB_LLC_WB_ELLC         (2 << 1)
 385 #define HSW_MOCS_UC_LLC_WB_ELLC         (3 << 1)
 386
 387 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
 388  * and let you force write-back (WB) or write-through (WT) caching, or leave
 389  * it up to the page table entry (PTE) specified by the kernel.
 390  */
 391 #define BDW_MOCS_WB  0x78
 392 #define BDW_MOCS_WT  0x58
 393 #define BDW_MOCS_PTE 0x18
 394
 395 /* Skylake: MOCS is now an index into an array of 62 different caching
 396  * configurations programmed by the kernel.
 397  */
 398 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
 399 #define SKL_MOCS_WB  (2 << 1)
 400 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
 401 #define SKL_MOCS_PTE (1 << 1)
 402
 403 /* Cannonlake: MOCS is now an index into an array of 62 different caching
 404  * configurations programmed by the kernel.
 405  */
 406 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
 407 #define CNL_MOCS_WB  (2 << 1)
 408 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
 409 #define CNL_MOCS_PTE (1 << 1)
 410
 411 #ifdef __cplusplus
 412 }
 413 #endif
 414
 415 #endif