2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
36 #include "brw_context.h"
42 enum intel_msaa_layout
;
44 extern const struct brw_tracked_state brw_blend_constant_color
;
45 extern const struct brw_tracked_state brw_clip_unit
;
46 extern const struct brw_tracked_state brw_vs_pull_constants
;
47 extern const struct brw_tracked_state brw_tcs_pull_constants
;
48 extern const struct brw_tracked_state brw_tes_pull_constants
;
49 extern const struct brw_tracked_state brw_gs_pull_constants
;
50 extern const struct brw_tracked_state brw_wm_pull_constants
;
51 extern const struct brw_tracked_state brw_cs_pull_constants
;
52 extern const struct brw_tracked_state brw_constant_buffer
;
53 extern const struct brw_tracked_state brw_curbe_offsets
;
54 extern const struct brw_tracked_state brw_invariant_state
;
55 extern const struct brw_tracked_state brw_binding_table_pointers
;
56 extern const struct brw_tracked_state brw_depthbuffer
;
57 extern const struct brw_tracked_state brw_recalculate_urb_fence
;
58 extern const struct brw_tracked_state brw_sf_vp
;
59 extern const struct brw_tracked_state brw_cs_texture_surfaces
;
60 extern const struct brw_tracked_state brw_vs_ubo_surfaces
;
61 extern const struct brw_tracked_state brw_vs_abo_surfaces
;
62 extern const struct brw_tracked_state brw_vs_image_surfaces
;
63 extern const struct brw_tracked_state brw_tcs_ubo_surfaces
;
64 extern const struct brw_tracked_state brw_tcs_abo_surfaces
;
65 extern const struct brw_tracked_state brw_tcs_image_surfaces
;
66 extern const struct brw_tracked_state brw_tes_ubo_surfaces
;
67 extern const struct brw_tracked_state brw_tes_abo_surfaces
;
68 extern const struct brw_tracked_state brw_tes_image_surfaces
;
69 extern const struct brw_tracked_state brw_gs_ubo_surfaces
;
70 extern const struct brw_tracked_state brw_gs_abo_surfaces
;
71 extern const struct brw_tracked_state brw_gs_image_surfaces
;
72 extern const struct brw_tracked_state brw_renderbuffer_surfaces
;
73 extern const struct brw_tracked_state brw_renderbuffer_read_surfaces
;
74 extern const struct brw_tracked_state brw_texture_surfaces
;
75 extern const struct brw_tracked_state brw_wm_binding_table
;
76 extern const struct brw_tracked_state brw_gs_binding_table
;
77 extern const struct brw_tracked_state brw_tes_binding_table
;
78 extern const struct brw_tracked_state brw_tcs_binding_table
;
79 extern const struct brw_tracked_state brw_vs_binding_table
;
80 extern const struct brw_tracked_state brw_wm_ubo_surfaces
;
81 extern const struct brw_tracked_state brw_wm_abo_surfaces
;
82 extern const struct brw_tracked_state brw_wm_image_surfaces
;
83 extern const struct brw_tracked_state brw_cs_ubo_surfaces
;
84 extern const struct brw_tracked_state brw_cs_abo_surfaces
;
85 extern const struct brw_tracked_state brw_cs_image_surfaces
;
87 extern const struct brw_tracked_state brw_psp_urb_cbs
;
89 extern const struct brw_tracked_state brw_indices
;
90 extern const struct brw_tracked_state brw_index_buffer
;
91 extern const struct brw_tracked_state gen7_cs_push_constants
;
92 extern const struct brw_tracked_state gen6_binding_table_pointers
;
93 extern const struct brw_tracked_state gen6_gs_binding_table
;
94 extern const struct brw_tracked_state gen6_renderbuffer_surfaces
;
95 extern const struct brw_tracked_state gen6_sampler_state
;
96 extern const struct brw_tracked_state gen6_sol_surface
;
97 extern const struct brw_tracked_state gen6_sf_vp
;
98 extern const struct brw_tracked_state gen6_urb
;
99 extern const struct brw_tracked_state gen7_depthbuffer
;
100 extern const struct brw_tracked_state gen7_l3_state
;
101 extern const struct brw_tracked_state gen7_push_constant_space
;
102 extern const struct brw_tracked_state gen7_urb
;
103 extern const struct brw_tracked_state gen8_pma_fix
;
104 extern const struct brw_tracked_state brw_cs_work_groups_surface
;
107 brw_state_dirty(const struct brw_context
*brw
,
108 GLuint mesa_flags
, uint64_t brw_flags
)
110 return ((brw
->NewGLState
& mesa_flags
) |
111 (brw
->ctx
.NewDriverState
& brw_flags
)) != 0;
114 /* brw_binding_tables.c */
115 void brw_upload_binding_table(struct brw_context
*brw
,
116 uint32_t packet_name
,
117 const struct brw_stage_prog_data
*prog_data
,
118 struct brw_stage_state
*stage_state
);
120 /* brw_misc_state.c */
121 void brw_upload_invariant_state(struct brw_context
*brw
);
123 brw_depthbuffer_format(struct brw_context
*brw
);
126 brw_convert_depth_value(mesa_format format
, float value
);
128 void brw_upload_state_base_address(struct brw_context
*brw
);
130 /* gen8_depth_state.c */
131 void gen8_write_pma_stall_bits(struct brw_context
*brw
,
132 uint32_t pma_stall_bits
);
134 /* brw_disk_cache.c */
135 bool brw_disk_cache_upload_program(struct brw_context
*brw
,
136 gl_shader_stage stage
);
137 void brw_disk_cache_write_program(struct brw_context
*brw
);
139 /***********************************************************************
142 void brw_upload_render_state(struct brw_context
*brw
);
143 void brw_render_state_finished(struct brw_context
*brw
);
144 void brw_upload_compute_state(struct brw_context
*brw
);
145 void brw_compute_state_finished(struct brw_context
*brw
);
146 void brw_init_state(struct brw_context
*brw
);
147 void brw_destroy_state(struct brw_context
*brw
);
148 void brw_emit_select_pipeline(struct brw_context
*brw
,
149 enum brw_pipeline pipeline
);
152 brw_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
154 if (unlikely(brw
->last_pipeline
!= pipeline
)) {
155 assert(pipeline
< BRW_NUM_PIPELINES
);
156 brw_emit_select_pipeline(brw
, pipeline
);
157 brw
->last_pipeline
= pipeline
;
161 /***********************************************************************
162 * brw_program_cache.c
165 void brw_upload_cache(struct brw_cache
*cache
,
166 enum brw_cache_id cache_id
,
173 uint32_t *out_offset
, void *out_aux
);
175 bool brw_search_cache(struct brw_cache
*cache
,
176 enum brw_cache_id cache_id
,
179 uint32_t *inout_offset
, void *inout_aux
);
181 const void *brw_find_previous_compile(struct brw_cache
*cache
,
182 enum brw_cache_id cache_id
,
183 unsigned program_string_id
);
185 void brw_program_cache_check_size(struct brw_context
*brw
);
187 void brw_init_caches( struct brw_context
*brw
);
188 void brw_destroy_caches( struct brw_context
*brw
);
190 void brw_print_program_cache(struct brw_context
*brw
);
192 /* intel_batchbuffer.c */
193 void brw_require_statebuffer_space(struct brw_context
*brw
, int size
);
194 void *brw_state_batch(struct brw_context
*brw
,
195 int size
, int alignment
, uint32_t *out_offset
);
196 uint32_t brw_state_batch_size(struct brw_context
*brw
, uint32_t offset
);
198 /* brw_wm_surface_state.c */
199 uint32_t brw_get_surface_tiling_bits(uint32_t tiling
);
200 uint32_t brw_get_surface_num_multisamples(unsigned num_samples
);
201 enum isl_format
brw_isl_format_for_mesa_format(mesa_format mesa_format
);
203 GLuint
translate_tex_target(GLenum target
);
205 enum isl_format
translate_tex_format(struct brw_context
*brw
,
206 mesa_format mesa_format
,
209 int brw_get_texture_swizzle(const struct gl_context
*ctx
,
210 const struct gl_texture_object
*t
);
212 void brw_emit_buffer_surface_state(struct brw_context
*brw
,
213 uint32_t *out_offset
,
215 unsigned buffer_offset
,
216 unsigned surface_format
,
217 unsigned buffer_size
,
219 unsigned reloc_flags
);
221 /* brw_sampler_state.c */
222 void brw_emit_sampler_state(struct brw_context
*brw
,
223 uint32_t *sampler_state
,
224 uint32_t batch_offset_for_sampler_state
,
228 unsigned max_anisotropy
,
229 unsigned address_rounding
,
237 unsigned shadow_function
,
238 bool non_normalized_coordinates
,
239 uint32_t border_color_offset
);
241 /* gen6_constant_state.c */
243 brw_populate_constant_data(struct brw_context
*brw
,
244 const struct gl_program
*prog
,
245 const struct brw_stage_state
*stage_state
,
247 const uint32_t *param
,
250 brw_upload_pull_constants(struct brw_context
*brw
,
251 GLbitfield64 brw_new_constbuf
,
252 const struct gl_program
*prog
,
253 struct brw_stage_state
*stage_state
,
254 const struct brw_stage_prog_data
*prog_data
);
256 brw_upload_cs_push_constants(struct brw_context
*brw
,
257 const struct gl_program
*prog
,
258 const struct brw_cs_prog_data
*cs_prog_data
,
259 struct brw_stage_state
*stage_state
);
261 /* gen7_vs_state.c */
263 gen7_upload_constant_state(struct brw_context
*brw
,
264 const struct brw_stage_state
*stage_state
,
265 bool active
, unsigned opcode
);
268 void brw_upload_clip_prog(struct brw_context
*brw
);
271 void brw_upload_sf_prog(struct brw_context
*brw
);
273 bool brw_is_drawing_points(const struct brw_context
*brw
);
274 bool brw_is_drawing_lines(const struct brw_context
*brw
);
276 /* gen7_l3_state.c */
278 gen7_restore_default_l3_config(struct brw_context
*brw
);
281 use_state_point_size(const struct brw_context
*brw
)
283 const struct gl_context
*ctx
= &brw
->ctx
;
285 /* Section 14.4 (Points) of the OpenGL 4.5 specification says:
287 * "If program point size mode is enabled, the derived point size is
288 * taken from the (potentially clipped) shader built-in gl_PointSize
291 * * the geometry shader, if active;
292 * * the tessellation evaluation shader, if active and no
293 * geometry shader is active;
294 * * the vertex shader, otherwise
296 * and clamped to the implementation-dependent point size range. If
297 * the value written to gl_PointSize is less than or equal to zero,
298 * or if no value was written to gl_PointSize, results are undefined.
299 * If program point size mode is disabled, the derived point size is
300 * specified with the command
302 * void PointSize(float size);
304 * size specifies the requested size of a point. The default value
307 * The rules for GLES come from the ES 3.2, OES_geometry_point_size, and
308 * OES_tessellation_point_size specifications. To summarize: if the last
309 * stage before rasterization is a GS or TES, then use gl_PointSize from
310 * the shader if written. Otherwise, use 1.0. If the last stage is a
311 * vertex shader, use gl_PointSize, or it is undefined.
313 * We can combine these rules into a single condition for both APIs.
314 * Using the state point size when the last shader stage doesn't write
315 * gl_PointSize satisfies GL's requirements, as it's undefined. Because
316 * ES doesn't have a PointSize() command, the state point size will
317 * remain 1.0, satisfying the ES default value in the GS/TES case, and
318 * the VS case (1.0 works for "undefined"). Mesa sets the program point
319 * mode flag to always-enabled in ES, so we can safely check that, and
320 * it'll be ignored for ES.
322 * _NEW_PROGRAM | _NEW_POINT
323 * BRW_NEW_VUE_MAP_GEOM_OUT
325 return (!ctx
->VertexProgram
.PointSizeEnabled
&& !ctx
->Point
._Attenuated
) ||
326 (brw
->vue_map_geom_out
.slots_valid
& VARYING_BIT_PSIZ
) == 0;
329 void brw_copy_pipeline_atoms(struct brw_context
*brw
,
330 enum brw_pipeline pipeline
,
331 const struct brw_tracked_state
**atoms
,
333 void gen4_init_atoms(struct brw_context
*brw
);
334 void gen45_init_atoms(struct brw_context
*brw
);
335 void gen5_init_atoms(struct brw_context
*brw
);
336 void gen6_init_atoms(struct brw_context
*brw
);
337 void gen7_init_atoms(struct brw_context
*brw
);
338 void gen75_init_atoms(struct brw_context
*brw
);
339 void gen8_init_atoms(struct brw_context
*brw
);
340 void gen9_init_atoms(struct brw_context
*brw
);
341 void gen10_init_atoms(struct brw_context
*brw
);
343 /* Memory Object Control State:
344 * Specifying zero for L3 means "uncached in L3", at least on Haswell
345 * and Baytrail, since there are no PTE flags for setting L3 cacheability.
346 * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
347 * may still respect that.
349 #define GEN7_MOCS_L3 1
351 /* Ivybridge only: cache in LLC.
352 * Specifying zero here means to use the PTE values set by the kernel;
353 * non-zero overrides the PTE values.
355 #define IVB_MOCS_LLC (1 << 1)
357 /* Baytrail only: snoop in CPU cache */
358 #define BYT_MOCS_SNOOP (1 << 1)
360 /* Haswell only: LLC/eLLC controls (write-back or uncached).
361 * Specifying zero here means to use the PTE values set by the kernel,
362 * which is useful since it offers additional control (write-through
363 * cacheing and age). Non-zero overrides the PTE values.
365 #define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
366 #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
367 #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
369 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
370 * and let you force write-back (WB) or write-through (WT) caching, or leave
371 * it up to the page table entry (PTE) specified by the kernel.
373 #define BDW_MOCS_WB 0x78
374 #define BDW_MOCS_WT 0x58
375 #define BDW_MOCS_PTE 0x18
377 /* Skylake: MOCS is now an index into an array of 62 different caching
378 * configurations programmed by the kernel.
380 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
381 #define SKL_MOCS_WB (2 << 1)
382 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
383 #define SKL_MOCS_PTE (1 << 1)
385 /* Cannonlake: MOCS is now an index into an array of 62 different caching
386 * configurations programmed by the kernel.
388 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
389 #define CNL_MOCS_WB (2 << 1)
390 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
391 #define CNL_MOCS_PTE (1 << 1)