2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
36 #include "brw_context.h"
42 enum intel_msaa_layout
;
44 extern const struct brw_tracked_state brw_blend_constant_color
;
45 extern const struct brw_tracked_state brw_clip_unit
;
46 extern const struct brw_tracked_state brw_vs_pull_constants
;
47 extern const struct brw_tracked_state brw_tcs_pull_constants
;
48 extern const struct brw_tracked_state brw_tes_pull_constants
;
49 extern const struct brw_tracked_state brw_gs_pull_constants
;
50 extern const struct brw_tracked_state brw_wm_pull_constants
;
51 extern const struct brw_tracked_state brw_cs_pull_constants
;
52 extern const struct brw_tracked_state brw_constant_buffer
;
53 extern const struct brw_tracked_state brw_curbe_offsets
;
54 extern const struct brw_tracked_state brw_binding_table_pointers
;
55 extern const struct brw_tracked_state brw_depthbuffer
;
56 extern const struct brw_tracked_state brw_recalculate_urb_fence
;
57 extern const struct brw_tracked_state brw_sf_vp
;
58 extern const struct brw_tracked_state brw_cs_texture_surfaces
;
59 extern const struct brw_tracked_state brw_vs_ubo_surfaces
;
60 extern const struct brw_tracked_state brw_vs_image_surfaces
;
61 extern const struct brw_tracked_state brw_tcs_ubo_surfaces
;
62 extern const struct brw_tracked_state brw_tcs_image_surfaces
;
63 extern const struct brw_tracked_state brw_tes_ubo_surfaces
;
64 extern const struct brw_tracked_state brw_tes_image_surfaces
;
65 extern const struct brw_tracked_state brw_gs_ubo_surfaces
;
66 extern const struct brw_tracked_state brw_gs_image_surfaces
;
67 extern const struct brw_tracked_state brw_renderbuffer_surfaces
;
68 extern const struct brw_tracked_state brw_renderbuffer_read_surfaces
;
69 extern const struct brw_tracked_state brw_texture_surfaces
;
70 extern const struct brw_tracked_state brw_wm_binding_table
;
71 extern const struct brw_tracked_state brw_gs_binding_table
;
72 extern const struct brw_tracked_state brw_tes_binding_table
;
73 extern const struct brw_tracked_state brw_tcs_binding_table
;
74 extern const struct brw_tracked_state brw_vs_binding_table
;
75 extern const struct brw_tracked_state brw_wm_ubo_surfaces
;
76 extern const struct brw_tracked_state brw_wm_image_surfaces
;
77 extern const struct brw_tracked_state brw_cs_ubo_surfaces
;
78 extern const struct brw_tracked_state brw_cs_image_surfaces
;
80 extern const struct brw_tracked_state brw_psp_urb_cbs
;
82 extern const struct brw_tracked_state brw_indices
;
83 extern const struct brw_tracked_state brw_index_buffer
;
84 extern const struct brw_tracked_state gen7_cs_push_constants
;
85 extern const struct brw_tracked_state gen6_binding_table_pointers
;
86 extern const struct brw_tracked_state gen6_gs_binding_table
;
87 extern const struct brw_tracked_state gen6_renderbuffer_surfaces
;
88 extern const struct brw_tracked_state gen6_sampler_state
;
89 extern const struct brw_tracked_state gen6_sol_surface
;
90 extern const struct brw_tracked_state gen6_sf_vp
;
91 extern const struct brw_tracked_state gen6_urb
;
92 extern const struct brw_tracked_state gen7_l3_state
;
93 extern const struct brw_tracked_state gen7_push_constant_space
;
94 extern const struct brw_tracked_state gen7_urb
;
95 extern const struct brw_tracked_state gen8_pma_fix
;
96 extern const struct brw_tracked_state brw_cs_work_groups_surface
;
99 brw_state_dirty(const struct brw_context
*brw
,
100 GLuint mesa_flags
, uint64_t brw_flags
)
102 return ((brw
->NewGLState
& mesa_flags
) |
103 (brw
->ctx
.NewDriverState
& brw_flags
)) != 0;
106 /* brw_binding_tables.c */
107 void brw_upload_binding_table(struct brw_context
*brw
,
108 uint32_t packet_name
,
109 const struct brw_stage_prog_data
*prog_data
,
110 struct brw_stage_state
*stage_state
);
112 /* brw_misc_state.c */
113 void brw_upload_invariant_state(struct brw_context
*brw
);
115 brw_depthbuffer_format(struct brw_context
*brw
);
117 void brw_upload_state_base_address(struct brw_context
*brw
);
119 /* gen8_depth_state.c */
120 void gen8_write_pma_stall_bits(struct brw_context
*brw
,
121 uint32_t pma_stall_bits
);
123 /* brw_disk_cache.c */
124 void brw_disk_cache_init(struct intel_screen
*screen
);
125 bool brw_disk_cache_upload_program(struct brw_context
*brw
,
126 gl_shader_stage stage
);
127 void brw_disk_cache_write_compute_program(struct brw_context
*brw
);
128 void brw_disk_cache_write_render_programs(struct brw_context
*brw
);
130 /***********************************************************************
133 void brw_upload_render_state(struct brw_context
*brw
);
134 void brw_render_state_finished(struct brw_context
*brw
);
135 void brw_upload_compute_state(struct brw_context
*brw
);
136 void brw_compute_state_finished(struct brw_context
*brw
);
137 void brw_init_state(struct brw_context
*brw
);
138 void brw_destroy_state(struct brw_context
*brw
);
139 void brw_emit_select_pipeline(struct brw_context
*brw
,
140 enum brw_pipeline pipeline
);
141 void brw_enable_obj_preemption(struct brw_context
*brw
, bool enable
);
144 brw_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
146 if (unlikely(brw
->last_pipeline
!= pipeline
)) {
147 assert(pipeline
< BRW_NUM_PIPELINES
);
148 brw_emit_select_pipeline(brw
, pipeline
);
149 brw
->last_pipeline
= pipeline
;
153 /***********************************************************************
154 * brw_program_cache.c
157 void brw_upload_cache(struct brw_cache
*cache
,
158 enum brw_cache_id cache_id
,
165 uint32_t *out_offset
, void *out_aux
);
167 bool brw_search_cache(struct brw_cache
*cache
, enum brw_cache_id cache_id
,
168 const void *key
, GLuint key_size
, uint32_t *inout_offset
,
169 void *inout_aux
, bool flag_state
);
171 const void *brw_find_previous_compile(struct brw_cache
*cache
,
172 enum brw_cache_id cache_id
,
173 unsigned program_string_id
);
175 void brw_program_cache_check_size(struct brw_context
*brw
);
177 void brw_init_caches( struct brw_context
*brw
);
178 void brw_destroy_caches( struct brw_context
*brw
);
180 void brw_print_program_cache(struct brw_context
*brw
);
182 enum brw_cache_id
brw_stage_cache_id(gl_shader_stage stage
);
184 /* intel_batchbuffer.c */
185 void brw_require_statebuffer_space(struct brw_context
*brw
, int size
);
186 void *brw_state_batch(struct brw_context
*brw
,
187 int size
, int alignment
, uint32_t *out_offset
);
189 /* brw_wm_surface_state.c */
190 uint32_t brw_get_surface_tiling_bits(uint32_t tiling
);
191 uint32_t brw_get_surface_num_multisamples(unsigned num_samples
);
192 enum isl_format
brw_isl_format_for_mesa_format(mesa_format mesa_format
);
194 GLuint
translate_tex_target(GLenum target
);
196 enum isl_format
translate_tex_format(struct brw_context
*brw
,
197 mesa_format mesa_format
,
200 int brw_get_texture_swizzle(const struct gl_context
*ctx
,
201 const struct gl_texture_object
*t
);
203 void brw_emit_buffer_surface_state(struct brw_context
*brw
,
204 uint32_t *out_offset
,
206 unsigned buffer_offset
,
207 unsigned surface_format
,
208 unsigned buffer_size
,
210 unsigned reloc_flags
);
212 /* brw_sampler_state.c */
213 void brw_emit_sampler_state(struct brw_context
*brw
,
214 uint32_t *sampler_state
,
215 uint32_t batch_offset_for_sampler_state
,
219 unsigned max_anisotropy
,
220 unsigned address_rounding
,
228 unsigned shadow_function
,
229 bool non_normalized_coordinates
,
230 uint32_t border_color_offset
);
232 /* gen6_constant_state.c */
234 brw_populate_constant_data(struct brw_context
*brw
,
235 const struct gl_program
*prog
,
236 const struct brw_stage_state
*stage_state
,
238 const uint32_t *param
,
241 brw_upload_pull_constants(struct brw_context
*brw
,
242 GLbitfield64 brw_new_constbuf
,
243 const struct gl_program
*prog
,
244 struct brw_stage_state
*stage_state
,
245 const struct brw_stage_prog_data
*prog_data
);
247 brw_upload_cs_push_constants(struct brw_context
*brw
,
248 const struct gl_program
*prog
,
249 const struct brw_cs_prog_data
*cs_prog_data
,
250 struct brw_stage_state
*stage_state
);
252 /* gen7_vs_state.c */
254 gen7_upload_constant_state(struct brw_context
*brw
,
255 const struct brw_stage_state
*stage_state
,
256 bool active
, unsigned opcode
);
259 void brw_upload_clip_prog(struct brw_context
*brw
);
262 void brw_upload_sf_prog(struct brw_context
*brw
);
264 bool brw_is_drawing_points(const struct brw_context
*brw
);
265 bool brw_is_drawing_lines(const struct brw_context
*brw
);
267 /* gen7_l3_state.c */
269 gen7_restore_default_l3_config(struct brw_context
*brw
);
272 use_state_point_size(const struct brw_context
*brw
)
274 const struct gl_context
*ctx
= &brw
->ctx
;
276 /* Section 14.4 (Points) of the OpenGL 4.5 specification says:
278 * "If program point size mode is enabled, the derived point size is
279 * taken from the (potentially clipped) shader built-in gl_PointSize
282 * * the geometry shader, if active;
283 * * the tessellation evaluation shader, if active and no
284 * geometry shader is active;
285 * * the vertex shader, otherwise
287 * and clamped to the implementation-dependent point size range. If
288 * the value written to gl_PointSize is less than or equal to zero,
289 * or if no value was written to gl_PointSize, results are undefined.
290 * If program point size mode is disabled, the derived point size is
291 * specified with the command
293 * void PointSize(float size);
295 * size specifies the requested size of a point. The default value
298 * The rules for GLES come from the ES 3.2, OES_geometry_point_size, and
299 * OES_tessellation_point_size specifications. To summarize: if the last
300 * stage before rasterization is a GS or TES, then use gl_PointSize from
301 * the shader if written. Otherwise, use 1.0. If the last stage is a
302 * vertex shader, use gl_PointSize, or it is undefined.
304 * We can combine these rules into a single condition for both APIs.
305 * Using the state point size when the last shader stage doesn't write
306 * gl_PointSize satisfies GL's requirements, as it's undefined. Because
307 * ES doesn't have a PointSize() command, the state point size will
308 * remain 1.0, satisfying the ES default value in the GS/TES case, and
309 * the VS case (1.0 works for "undefined"). Mesa sets the program point
310 * mode flag to always-enabled in ES, so we can safely check that, and
311 * it'll be ignored for ES.
313 * _NEW_PROGRAM | _NEW_POINT
314 * BRW_NEW_VUE_MAP_GEOM_OUT
316 return (!ctx
->VertexProgram
.PointSizeEnabled
&& !ctx
->Point
._Attenuated
) ||
317 (brw
->vue_map_geom_out
.slots_valid
& VARYING_BIT_PSIZ
) == 0;
320 void brw_copy_pipeline_atoms(struct brw_context
*brw
,
321 enum brw_pipeline pipeline
,
322 const struct brw_tracked_state
**atoms
,
324 void gen4_init_atoms(struct brw_context
*brw
);
325 void gen45_init_atoms(struct brw_context
*brw
);
326 void gen5_init_atoms(struct brw_context
*brw
);
327 void gen6_init_atoms(struct brw_context
*brw
);
328 void gen7_init_atoms(struct brw_context
*brw
);
329 void gen75_init_atoms(struct brw_context
*brw
);
330 void gen8_init_atoms(struct brw_context
*brw
);
331 void gen9_init_atoms(struct brw_context
*brw
);
332 void gen10_init_atoms(struct brw_context
*brw
);
333 void gen11_init_atoms(struct brw_context
*brw
);
335 /* Memory Object Control State:
336 * Specifying zero for L3 means "uncached in L3", at least on Haswell
337 * and Baytrail, since there are no PTE flags for setting L3 cacheability.
338 * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
339 * may still respect that.
341 #define GEN7_MOCS_L3 1
343 /* Ivybridge only: cache in LLC.
344 * Specifying zero here means to use the PTE values set by the kernel;
345 * non-zero overrides the PTE values.
347 #define IVB_MOCS_LLC (1 << 1)
349 /* Baytrail only: snoop in CPU cache */
350 #define BYT_MOCS_SNOOP (1 << 1)
352 /* Haswell only: LLC/eLLC controls (write-back or uncached).
353 * Specifying zero here means to use the PTE values set by the kernel,
354 * which is useful since it offers additional control (write-through
355 * cacheing and age). Non-zero overrides the PTE values.
357 #define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
358 #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
359 #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
361 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
362 * and let you force write-back (WB) or write-through (WT) caching, or leave
363 * it up to the page table entry (PTE) specified by the kernel.
365 #define BDW_MOCS_WB 0x78
366 #define BDW_MOCS_WT 0x58
367 #define BDW_MOCS_PTE 0x18
369 /* Skylake: MOCS is now an index into an array of 62 different caching
370 * configurations programmed by the kernel.
372 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
373 #define SKL_MOCS_WB (2 << 1)
374 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
375 #define SKL_MOCS_PTE (1 << 1)
377 /* Cannonlake: MOCS is now an index into an array of 62 different caching
378 * configurations programmed by the kernel.
380 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
381 #define CNL_MOCS_WB (2 << 1)
382 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
383 #define CNL_MOCS_PTE (1 << 1)
385 /* Ice Lake uses same MOCS settings as Cannonlake */
386 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
387 #define ICL_MOCS_WB (2 << 1)
388 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
389 #define ICL_MOCS_PTE (1 << 1)
391 uint32_t brw_get_bo_mocs(const struct gen_device_info
*devinfo
,