i965: Port Gen4-5 VS_STATE to genxml.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_state.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_STATE_H
34 #define BRW_STATE_H
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 enum intel_msaa_layout;
43
44 extern const struct brw_tracked_state brw_blend_constant_color;
45 extern const struct brw_tracked_state brw_cc_vp;
46 extern const struct brw_tracked_state brw_cc_unit;
47 extern const struct brw_tracked_state brw_clip_unit;
48 extern const struct brw_tracked_state brw_vs_pull_constants;
49 extern const struct brw_tracked_state brw_tcs_pull_constants;
50 extern const struct brw_tracked_state brw_tes_pull_constants;
51 extern const struct brw_tracked_state brw_gs_pull_constants;
52 extern const struct brw_tracked_state brw_wm_pull_constants;
53 extern const struct brw_tracked_state brw_cs_pull_constants;
54 extern const struct brw_tracked_state brw_constant_buffer;
55 extern const struct brw_tracked_state brw_curbe_offsets;
56 extern const struct brw_tracked_state brw_invariant_state;
57 extern const struct brw_tracked_state brw_fs_samplers;
58 extern const struct brw_tracked_state brw_gs_unit;
59 extern const struct brw_tracked_state brw_binding_table_pointers;
60 extern const struct brw_tracked_state brw_depthbuffer;
61 extern const struct brw_tracked_state brw_recalculate_urb_fence;
62 extern const struct brw_tracked_state brw_sf_unit;
63 extern const struct brw_tracked_state brw_sf_vp;
64 extern const struct brw_tracked_state brw_vs_samplers;
65 extern const struct brw_tracked_state brw_tcs_samplers;
66 extern const struct brw_tracked_state brw_tes_samplers;
67 extern const struct brw_tracked_state brw_gs_samplers;
68 extern const struct brw_tracked_state brw_cs_samplers;
69 extern const struct brw_tracked_state brw_cs_texture_surfaces;
70 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
71 extern const struct brw_tracked_state brw_vs_abo_surfaces;
72 extern const struct brw_tracked_state brw_vs_image_surfaces;
73 extern const struct brw_tracked_state brw_tcs_ubo_surfaces;
74 extern const struct brw_tracked_state brw_tcs_abo_surfaces;
75 extern const struct brw_tracked_state brw_tcs_image_surfaces;
76 extern const struct brw_tracked_state brw_tes_ubo_surfaces;
77 extern const struct brw_tracked_state brw_tes_abo_surfaces;
78 extern const struct brw_tracked_state brw_tes_image_surfaces;
79 extern const struct brw_tracked_state brw_gs_ubo_surfaces;
80 extern const struct brw_tracked_state brw_gs_abo_surfaces;
81 extern const struct brw_tracked_state brw_gs_image_surfaces;
82 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
83 extern const struct brw_tracked_state brw_renderbuffer_read_surfaces;
84 extern const struct brw_tracked_state brw_texture_surfaces;
85 extern const struct brw_tracked_state brw_wm_binding_table;
86 extern const struct brw_tracked_state brw_gs_binding_table;
87 extern const struct brw_tracked_state brw_tes_binding_table;
88 extern const struct brw_tracked_state brw_tcs_binding_table;
89 extern const struct brw_tracked_state brw_vs_binding_table;
90 extern const struct brw_tracked_state brw_wm_ubo_surfaces;
91 extern const struct brw_tracked_state brw_wm_abo_surfaces;
92 extern const struct brw_tracked_state brw_wm_image_surfaces;
93 extern const struct brw_tracked_state brw_cs_ubo_surfaces;
94 extern const struct brw_tracked_state brw_cs_abo_surfaces;
95 extern const struct brw_tracked_state brw_cs_image_surfaces;
96 extern const struct brw_tracked_state brw_wm_unit;
97
98 extern const struct brw_tracked_state brw_psp_urb_cbs;
99
100 extern const struct brw_tracked_state brw_indices;
101 extern const struct brw_tracked_state brw_index_buffer;
102 extern const struct brw_tracked_state brw_cs_state;
103 extern const struct brw_tracked_state gen7_cs_push_constants;
104 extern const struct brw_tracked_state gen6_binding_table_pointers;
105 extern const struct brw_tracked_state gen6_gs_binding_table;
106 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
107 extern const struct brw_tracked_state gen6_sampler_state;
108 extern const struct brw_tracked_state gen6_sol_surface;
109 extern const struct brw_tracked_state gen6_sf_vp;
110 extern const struct brw_tracked_state gen6_urb;
111 extern const struct brw_tracked_state gen7_depthbuffer;
112 extern const struct brw_tracked_state gen7_l3_state;
113 extern const struct brw_tracked_state gen7_push_constant_space;
114 extern const struct brw_tracked_state gen7_urb;
115 extern const struct brw_tracked_state gen8_index_buffer;
116 extern const struct brw_tracked_state gen8_pma_fix;
117 extern const struct brw_tracked_state gen8_vf_topology;
118 extern const struct brw_tracked_state brw_cs_work_groups_surface;
119
120 static inline bool
121 brw_state_dirty(const struct brw_context *brw,
122 GLuint mesa_flags, uint64_t brw_flags)
123 {
124 return ((brw->NewGLState & mesa_flags) |
125 (brw->ctx.NewDriverState & brw_flags)) != 0;
126 }
127
128 /* brw_binding_tables.c */
129 void brw_upload_binding_table(struct brw_context *brw,
130 uint32_t packet_name,
131 const struct brw_stage_prog_data *prog_data,
132 struct brw_stage_state *stage_state);
133
134 /* brw_misc_state.c */
135 void brw_upload_invariant_state(struct brw_context *brw);
136 uint32_t
137 brw_depthbuffer_format(struct brw_context *brw);
138
139 void brw_upload_state_base_address(struct brw_context *brw);
140
141 /* gen8_depth_state.c */
142 void gen8_write_pma_stall_bits(struct brw_context *brw,
143 uint32_t pma_stall_bits);
144
145 /***********************************************************************
146 * brw_state.c
147 */
148 void brw_upload_render_state(struct brw_context *brw);
149 void brw_render_state_finished(struct brw_context *brw);
150 void brw_upload_compute_state(struct brw_context *brw);
151 void brw_compute_state_finished(struct brw_context *brw);
152 void brw_init_state(struct brw_context *brw);
153 void brw_destroy_state(struct brw_context *brw);
154 void brw_emit_select_pipeline(struct brw_context *brw,
155 enum brw_pipeline pipeline);
156
157 static inline void
158 brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
159 {
160 if (unlikely(brw->last_pipeline != pipeline)) {
161 assert(pipeline < BRW_NUM_PIPELINES);
162 brw_emit_select_pipeline(brw, pipeline);
163 brw->last_pipeline = pipeline;
164 }
165 }
166
167 /***********************************************************************
168 * brw_program_cache.c
169 */
170
171 void brw_upload_cache(struct brw_cache *cache,
172 enum brw_cache_id cache_id,
173 const void *key,
174 GLuint key_sz,
175 const void *data,
176 GLuint data_sz,
177 const void *aux,
178 GLuint aux_sz,
179 uint32_t *out_offset, void *out_aux);
180
181 bool brw_search_cache(struct brw_cache *cache,
182 enum brw_cache_id cache_id,
183 const void *key,
184 GLuint key_size,
185 uint32_t *inout_offset, void *inout_aux);
186
187 const void *brw_find_previous_compile(struct brw_cache *cache,
188 enum brw_cache_id cache_id,
189 unsigned program_string_id);
190
191 void brw_program_cache_check_size(struct brw_context *brw);
192
193 void brw_init_caches( struct brw_context *brw );
194 void brw_destroy_caches( struct brw_context *brw );
195
196 void brw_print_program_cache(struct brw_context *brw);
197
198 /***********************************************************************
199 * brw_state_batch.c
200 */
201 #define BRW_BATCH_STRUCT(brw, s) \
202 intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
203
204 void *brw_state_batch(struct brw_context *brw,
205 int size, int alignment, uint32_t *out_offset);
206 uint32_t brw_state_batch_size(struct brw_context *brw, uint32_t offset);
207
208 /* brw_wm_surface_state.c */
209 void gen4_init_vtable_surface_functions(struct brw_context *brw);
210 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
211 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
212
213 uint32_t brw_isl_format_for_mesa_format(mesa_format mesa_format);
214
215 GLuint translate_tex_target(GLenum target);
216
217 GLuint translate_tex_format(struct brw_context *brw,
218 mesa_format mesa_format,
219 GLenum srgb_decode);
220
221 int brw_get_texture_swizzle(const struct gl_context *ctx,
222 const struct gl_texture_object *t);
223
224 void brw_emit_buffer_surface_state(struct brw_context *brw,
225 uint32_t *out_offset,
226 struct brw_bo *bo,
227 unsigned buffer_offset,
228 unsigned surface_format,
229 unsigned buffer_size,
230 unsigned pitch,
231 bool rw);
232
233 void brw_update_texture_surface(struct gl_context *ctx,
234 unsigned unit, uint32_t *surf_offset,
235 bool for_gather, uint32_t plane);
236
237 uint32_t brw_update_renderbuffer_surface(struct brw_context *brw,
238 struct gl_renderbuffer *rb,
239 uint32_t flags, unsigned unit,
240 uint32_t surf_index);
241
242 void brw_update_renderbuffer_surfaces(struct brw_context *brw,
243 const struct gl_framebuffer *fb,
244 uint32_t render_target_start,
245 uint32_t *surf_offset);
246
247 /* gen7_wm_surface_state.c */
248 void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
249 void gen7_init_vtable_surface_functions(struct brw_context *brw);
250
251 /* gen8_surface_state.c */
252
253 void gen8_init_vtable_surface_functions(struct brw_context *brw);
254
255 /* brw_sampler_state.c */
256 void brw_emit_sampler_state(struct brw_context *brw,
257 uint32_t *sampler_state,
258 uint32_t batch_offset_for_sampler_state,
259 unsigned min_filter,
260 unsigned mag_filter,
261 unsigned mip_filter,
262 unsigned max_anisotropy,
263 unsigned address_rounding,
264 unsigned wrap_s,
265 unsigned wrap_t,
266 unsigned wrap_r,
267 unsigned base_level,
268 unsigned min_lod,
269 unsigned max_lod,
270 int lod_bias,
271 unsigned shadow_function,
272 bool non_normalized_coordinates,
273 uint32_t border_color_offset);
274
275 /* gen6_surface_state.c */
276 void gen6_init_vtable_surface_functions(struct brw_context *brw);
277
278 /* brw_vs_surface_state.c */
279 void
280 brw_upload_pull_constants(struct brw_context *brw,
281 GLbitfield64 brw_new_constbuf,
282 const struct gl_program *prog,
283 struct brw_stage_state *stage_state,
284 const struct brw_stage_prog_data *prog_data);
285
286 /* gen7_vs_state.c */
287 void
288 gen7_upload_constant_state(struct brw_context *brw,
289 const struct brw_stage_state *stage_state,
290 bool active, unsigned opcode);
291
292 /* brw_clip.c */
293 void brw_upload_clip_prog(struct brw_context *brw);
294
295 /* brw_sf.c */
296 void brw_upload_sf_prog(struct brw_context *brw);
297
298 bool brw_is_drawing_points(const struct brw_context *brw);
299 bool brw_is_drawing_lines(const struct brw_context *brw);
300
301 /* gen7_l3_state.c */
302 void
303 gen7_restore_default_l3_config(struct brw_context *brw);
304
305 static inline bool
306 use_state_point_size(const struct brw_context *brw)
307 {
308 const struct gl_context *ctx = &brw->ctx;
309
310 /* Section 14.4 (Points) of the OpenGL 4.5 specification says:
311 *
312 * "If program point size mode is enabled, the derived point size is
313 * taken from the (potentially clipped) shader built-in gl_PointSize
314 * written by:
315 *
316 * * the geometry shader, if active;
317 * * the tessellation evaluation shader, if active and no
318 * geometry shader is active;
319 * * the vertex shader, otherwise
320 *
321 * and clamped to the implementation-dependent point size range. If
322 * the value written to gl_PointSize is less than or equal to zero,
323 * or if no value was written to gl_PointSize, results are undefined.
324 * If program point size mode is disabled, the derived point size is
325 * specified with the command
326 *
327 * void PointSize(float size);
328 *
329 * size specifies the requested size of a point. The default value
330 * is 1.0."
331 *
332 * The rules for GLES come from the ES 3.2, OES_geometry_point_size, and
333 * OES_tessellation_point_size specifications. To summarize: if the last
334 * stage before rasterization is a GS or TES, then use gl_PointSize from
335 * the shader if written. Otherwise, use 1.0. If the last stage is a
336 * vertex shader, use gl_PointSize, or it is undefined.
337 *
338 * We can combine these rules into a single condition for both APIs.
339 * Using the state point size when the last shader stage doesn't write
340 * gl_PointSize satisfies GL's requirements, as it's undefined. Because
341 * ES doesn't have a PointSize() command, the state point size will
342 * remain 1.0, satisfying the ES default value in the GS/TES case, and
343 * the VS case (1.0 works for "undefined"). Mesa sets the program point
344 * mode flag to always-enabled in ES, so we can safely check that, and
345 * it'll be ignored for ES.
346 *
347 * _NEW_PROGRAM | _NEW_POINT
348 * BRW_NEW_VUE_MAP_GEOM_OUT
349 */
350 return (!ctx->VertexProgram.PointSizeEnabled && !ctx->Point._Attenuated) ||
351 (brw->vue_map_geom_out.slots_valid & VARYING_BIT_PSIZ) == 0;
352 }
353
354 void brw_copy_pipeline_atoms(struct brw_context *brw,
355 enum brw_pipeline pipeline,
356 const struct brw_tracked_state **atoms,
357 int num_atoms);
358 void gen4_init_atoms(struct brw_context *brw);
359 void gen45_init_atoms(struct brw_context *brw);
360 void gen5_init_atoms(struct brw_context *brw);
361 void gen6_init_atoms(struct brw_context *brw);
362 void gen7_init_atoms(struct brw_context *brw);
363 void gen75_init_atoms(struct brw_context *brw);
364 void gen8_init_atoms(struct brw_context *brw);
365 void gen9_init_atoms(struct brw_context *brw);
366
367 void upload_gs_state_for_tf(struct brw_context *brw);
368
369 /* Memory Object Control State:
370 * Specifying zero for L3 means "uncached in L3", at least on Haswell
371 * and Baytrail, since there are no PTE flags for setting L3 cacheability.
372 * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
373 * may still respect that.
374 */
375 #define GEN7_MOCS_L3 1
376
377 /* Ivybridge only: cache in LLC.
378 * Specifying zero here means to use the PTE values set by the kernel;
379 * non-zero overrides the PTE values.
380 */
381 #define IVB_MOCS_LLC (1 << 1)
382
383 /* Baytrail only: snoop in CPU cache */
384 #define BYT_MOCS_SNOOP (1 << 1)
385
386 /* Haswell only: LLC/eLLC controls (write-back or uncached).
387 * Specifying zero here means to use the PTE values set by the kernel,
388 * which is useful since it offers additional control (write-through
389 * cacheing and age). Non-zero overrides the PTE values.
390 */
391 #define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
392 #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
393 #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
394
395 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
396 * and let you force write-back (WB) or write-through (WT) caching, or leave
397 * it up to the page table entry (PTE) specified by the kernel.
398 */
399 #define BDW_MOCS_WB 0x78
400 #define BDW_MOCS_WT 0x58
401 #define BDW_MOCS_PTE 0x18
402
403 /* Skylake: MOCS is now an index into an array of 62 different caching
404 * configurations programmed by the kernel.
405 */
406 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
407 #define SKL_MOCS_WB (2 << 1)
408 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
409 #define SKL_MOCS_PTE (1 << 1)
410
411 #ifdef __cplusplus
412 }
413 #endif
414
415 #endif