i965: Enable OpenGL 4.5 on Haswell.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_batch.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #include "brw_state.h"
33 #include "intel_batchbuffer.h"
34 #include "main/imports.h"
35 #include "util/ralloc.h"
36
37 static void
38 brw_track_state_batch(struct brw_context *brw,
39 enum aub_state_struct_type type,
40 uint32_t offset,
41 int size,
42 int index)
43 {
44 struct intel_batchbuffer *batch = &brw->batch;
45
46 if (!brw->state_batch_list) {
47 /* Our structs are always aligned to at least 32 bytes, so
48 * our array doesn't need to be any larger
49 * TODO: don't use rzalloc
50 */
51 brw->state_batch_list = rzalloc_size(brw, sizeof(*brw->state_batch_list) *
52 batch->bo->size / 32);
53 }
54
55 brw->state_batch_list[brw->state_batch_count].offset = offset;
56 brw->state_batch_list[brw->state_batch_count].size = size;
57 brw->state_batch_list[brw->state_batch_count].type = type;
58 brw->state_batch_list[brw->state_batch_count].index = index;
59 brw->state_batch_count++;
60 }
61
62 /**
63 * Convenience function to populate a single drm_intel_aub_annotation data
64 * structure.
65 */
66 static inline void
67 make_annotation(drm_intel_aub_annotation *annotation, uint32_t type,
68 uint32_t subtype, uint32_t ending_offset)
69 {
70 annotation->type = type;
71 annotation->subtype = subtype;
72 annotation->ending_offset = ending_offset;
73 }
74
75 /**
76 * Generate a set of aub file annotations for the current batch buffer, and
77 * deliver them to DRM.
78 *
79 * The "used" section of the batch buffer (the portion containing batch
80 * commands) is annotated with AUB_TRACE_TYPE_BATCH. The remainder of the
81 * batch buffer (which contains data structures pointed to by batch commands)
82 * is annotated according to the type of each data structure.
83 */
84 void
85 brw_annotate_aub(struct brw_context *brw)
86 {
87 unsigned annotation_count = 2 * brw->state_batch_count + 1;
88 drm_intel_aub_annotation annotations[annotation_count];
89 int a = 0;
90 make_annotation(&annotations[a++], AUB_TRACE_TYPE_BATCH, 0,
91 4 * USED_BATCH(brw->batch));
92 for (int i = brw->state_batch_count; i-- > 0; ) {
93 uint32_t type = brw->state_batch_list[i].type;
94 uint32_t start_offset = brw->state_batch_list[i].offset;
95 uint32_t end_offset = start_offset + brw->state_batch_list[i].size;
96 make_annotation(&annotations[a++], AUB_TRACE_TYPE_NOTYPE, 0,
97 start_offset);
98 make_annotation(&annotations[a++], AUB_TRACE_TYPE(type),
99 AUB_TRACE_SUBTYPE(type), end_offset);
100 }
101 assert(a == annotation_count);
102 drm_intel_bufmgr_gem_set_aub_annotations(brw->batch.bo, annotations,
103 annotation_count);
104 }
105
106 /**
107 * Allocates a block of space in the batchbuffer for indirect state.
108 *
109 * We don't want to allocate separate BOs for every bit of indirect
110 * state in the driver. It means overallocating by a significant
111 * margin (4096 bytes, even if the object is just a 20-byte surface
112 * state), and more buffers to walk and count for aperture size checking.
113 *
114 * However, due to the restrictions imposed by the aperture size
115 * checking performance hacks, we can't have the batch point at a
116 * separate indirect state buffer, because once the batch points at
117 * it, no more relocations can be added to it. So, we sneak these
118 * buffers in at the top of the batchbuffer.
119 */
120 void *
121 __brw_state_batch(struct brw_context *brw,
122 enum aub_state_struct_type type,
123 int size,
124 int alignment,
125 int index,
126 uint32_t *out_offset)
127
128 {
129 struct intel_batchbuffer *batch = &brw->batch;
130 uint32_t offset;
131
132 assert(size < batch->bo->size);
133 offset = ROUND_DOWN_TO(batch->state_batch_offset - size, alignment);
134
135 /* If allocating from the top would wrap below the batchbuffer, or
136 * if the batch's used space (plus the reserved pad) collides with our
137 * space, then flush and try again.
138 */
139 if (batch->state_batch_offset < size ||
140 offset < 4 * USED_BATCH(*batch) + batch->reserved_space) {
141 intel_batchbuffer_flush(brw);
142 offset = ROUND_DOWN_TO(batch->state_batch_offset - size, alignment);
143 }
144
145 batch->state_batch_offset = offset;
146
147 if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_AUB)))
148 brw_track_state_batch(brw, type, offset, size, index);
149
150 *out_offset = offset;
151 return batch->map + (offset>>2);
152 }