src/mesa/drivers/dri/i965/brw_state_batch.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_state.h"
  35 #include "intel_batchbuffer.h"
  36 #include "imports.h"
  37
  38
  39
  40 /* A facility similar to the data caching code above, which aims to
  41  * prevent identical commands being issued repeatedly.
  42  */
  43 GLboolean brw_cached_batch_struct( struct brw_context *brw,
  44                                    const void *data,
  45                                    GLuint sz )
  46 {
  47    struct brw_cached_batch_item *item = brw->cached_batch_items;
  48    struct header *newheader = (struct header *)data;
  49
  50    if (brw->emit_state_always) {
  51       intel_batchbuffer_data(brw->intel.batch, data, sz, 0);
  52       return GL_TRUE;
  53    }
  54
  55    while (item) {
  56       if (item->header->opcode == newheader->opcode) {
  57          if (item->sz == sz && memcmp(item->header, newheader, sz) == 0)
  58             return GL_FALSE;
  59          if (item->sz != sz) {
  60             _mesa_free(item->header);
  61             item->header = _mesa_malloc(sz);
  62             item->sz = sz;
  63          }
  64          goto emit;
  65       }
  66       item = item->next;
  67    }
  68
  69    assert(!item);
  70    item = CALLOC_STRUCT(brw_cached_batch_item);
  71    item->header = _mesa_malloc(sz);
  72    item->sz = sz;
  73    item->next = brw->cached_batch_items;
  74    brw->cached_batch_items = item;
  75
  76  emit:
  77    memcpy(item->header, newheader, sz);
  78    intel_batchbuffer_data(brw->intel.batch, data, sz, 0);
  79    return GL_TRUE;
  80 }
  81
  82 static void clear_batch_cache( struct brw_context *brw )
  83 {
  84    struct brw_cached_batch_item *item = brw->cached_batch_items;
  85
  86    while (item) {
  87       struct brw_cached_batch_item *next = item->next;
  88       free((void *)item->header);
  89       free(item);
  90       item = next;
  91    }
  92
  93    brw->cached_batch_items = NULL;
  94
  95
  96    brw_clear_all_caches(brw);
  97
  98    brw_invalidate_pools(brw);
  99 }
 100
 101 void brw_clear_batch_cache_flush( struct brw_context *brw )
 102 {
 103    clear_batch_cache(brw);
 104
 105    brw->wrap = 0;
 106
 107 /*    brw_do_flush(brw, BRW_FLUSH_STATE_CACHE|BRW_FLUSH_READ_CACHE); */
 108
 109    brw->state.dirty.mesa |= ~0;
 110    brw->state.dirty.brw |= ~0;
 111    brw->state.dirty.cache |= ~0;
 112 }
 113
 114
 115
 116 void brw_destroy_batch_cache( struct brw_context *brw )
 117 {
 118    clear_batch_cache(brw);
 119 }