2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
32 /** @file brw_state_cache.c
34 * This file implements a simple static state cache for 965. The
35 * consumers can query the hash table of state using a cache_id,
36 * opaque key data, and receive the corresponding state buffer object
37 * of state (plus associated auxiliary data) in return. Objects in
38 * the cache may not have relocations (pointers to other BOs) in them.
40 * The inner workings are a simple hash table based on a CRC of the
43 * Replacement is not implemented. Instead, when the cache gets too
44 * big we throw out all of the cache data and let it get regenerated.
47 #include "main/imports.h"
48 #include "intel_batchbuffer.h"
49 #include "brw_state.h"
54 #define FILE_DEBUG_FLAG DEBUG_STATE
57 hash_key(struct brw_cache_item
*item
)
59 GLuint
*ikey
= (GLuint
*)item
->key
;
60 GLuint hash
= item
->cache_id
, i
;
62 assert(item
->key_size
% 4 == 0);
64 /* I'm sure this can be improved on:
66 for (i
= 0; i
< item
->key_size
/4; i
++) {
68 hash
= (hash
<< 5) | (hash
>> 27);
75 brw_cache_item_equals(const struct brw_cache_item
*a
,
76 const struct brw_cache_item
*b
)
78 return a
->cache_id
== b
->cache_id
&&
80 a
->key_size
== b
->key_size
&&
81 (memcmp(a
->key
, b
->key
, a
->key_size
) == 0);
84 static struct brw_cache_item
*
85 search_cache(struct brw_cache
*cache
, GLuint hash
,
86 struct brw_cache_item
*lookup
)
88 struct brw_cache_item
*c
;
93 for (c
= cache
->items
[hash
% cache
->size
]; c
; c
= c
->next
)
96 fprintf(stderr
, "bucket %d/%d = %d/%d items\n", hash
% cache
->size
,
97 cache
->size
, bucketcount
, cache
->n_items
);
100 for (c
= cache
->items
[hash
% cache
->size
]; c
; c
= c
->next
) {
101 if (brw_cache_item_equals(lookup
, c
))
110 rehash(struct brw_cache
*cache
)
112 struct brw_cache_item
**items
;
113 struct brw_cache_item
*c
, *next
;
116 size
= cache
->size
* 3;
117 items
= calloc(size
, sizeof(*items
));
119 for (i
= 0; i
< cache
->size
; i
++)
120 for (c
= cache
->items
[i
]; c
; c
= next
) {
122 c
->next
= items
[c
->hash
% size
];
123 items
[c
->hash
% size
] = c
;
127 cache
->items
= items
;
133 * Returns the buffer object matching cache_id and key, or NULL.
136 brw_search_cache(struct brw_cache
*cache
,
137 enum brw_cache_id cache_id
,
138 const void *key
, GLuint key_size
,
139 uint32_t *inout_offset
, void *out_aux
)
141 struct brw_context
*brw
= cache
->brw
;
142 struct brw_cache_item
*item
;
143 struct brw_cache_item lookup
;
146 lookup
.cache_id
= cache_id
;
148 lookup
.key_size
= key_size
;
149 hash
= hash_key(&lookup
);
152 item
= search_cache(cache
, hash
, &lookup
);
157 *(void **)out_aux
= ((char *)item
->key
+ item
->key_size
);
159 if (item
->offset
!= *inout_offset
) {
160 brw
->state
.dirty
.brw
|= (1 << cache_id
);
161 *inout_offset
= item
->offset
;
168 brw_cache_new_bo(struct brw_cache
*cache
, uint32_t new_size
)
170 struct brw_context
*brw
= cache
->brw
;
171 drm_intel_bo
*new_bo
;
173 new_bo
= drm_intel_bo_alloc(brw
->bufmgr
, "program cache", new_size
, 64);
175 drm_intel_gem_bo_map_unsynchronized(new_bo
);
177 /* Copy any existing data that needs to be saved. */
178 if (cache
->next_offset
!= 0) {
180 memcpy(new_bo
->virtual, cache
->bo
->virtual, cache
->next_offset
);
182 drm_intel_bo_map(cache
->bo
, false);
183 drm_intel_bo_subdata(new_bo
, 0, cache
->next_offset
,
185 drm_intel_bo_unmap(cache
->bo
);
190 drm_intel_bo_unmap(cache
->bo
);
191 drm_intel_bo_unreference(cache
->bo
);
193 cache
->bo_used_by_gpu
= false;
195 /* Since we have a new BO in place, we need to signal the units
196 * that depend on it (state base address on gen5+, or unit state before).
198 brw
->state
.dirty
.brw
|= BRW_NEW_PROGRAM_CACHE
;
202 * Attempts to find an item in the cache with identical data and aux
206 brw_try_upload_using_copy(struct brw_cache
*cache
,
207 struct brw_cache_item
*result_item
,
211 struct brw_context
*brw
= cache
->brw
;
213 struct brw_cache_item
*item
;
215 for (i
= 0; i
< cache
->size
; i
++) {
216 for (item
= cache
->items
[i
]; item
; item
= item
->next
) {
217 const void *item_aux
= item
->key
+ item
->key_size
;
220 if (item
->cache_id
!= result_item
->cache_id
||
221 item
->size
!= result_item
->size
||
222 item
->aux_size
!= result_item
->aux_size
) {
226 if (cache
->aux_compare
[result_item
->cache_id
]) {
227 if (!cache
->aux_compare
[result_item
->cache_id
](item_aux
, aux
))
229 } else if (memcmp(item_aux
, aux
, item
->aux_size
) != 0) {
234 drm_intel_bo_map(cache
->bo
, false);
235 ret
= memcmp(cache
->bo
->virtual + item
->offset
, data
, item
->size
);
237 drm_intel_bo_unmap(cache
->bo
);
241 result_item
->offset
= item
->offset
;
251 brw_upload_item_data(struct brw_cache
*cache
,
252 struct brw_cache_item
*item
,
255 struct brw_context
*brw
= cache
->brw
;
257 /* Allocate space in the cache BO for our new program. */
258 if (cache
->next_offset
+ item
->size
> cache
->bo
->size
) {
259 uint32_t new_size
= cache
->bo
->size
* 2;
261 while (cache
->next_offset
+ item
->size
> new_size
)
264 brw_cache_new_bo(cache
, new_size
);
267 /* If we would block on writing to an in-use program BO, just
270 if (!brw
->has_llc
&& cache
->bo_used_by_gpu
) {
271 perf_debug("Copying busy program cache buffer.\n");
272 brw_cache_new_bo(cache
, cache
->bo
->size
);
275 item
->offset
= cache
->next_offset
;
277 /* Programs are always 64-byte aligned, so set up the next one now */
278 cache
->next_offset
= ALIGN(item
->offset
+ item
->size
, 64);
282 brw_upload_cache(struct brw_cache
*cache
,
283 enum brw_cache_id cache_id
,
290 uint32_t *out_offset
,
293 struct brw_context
*brw
= cache
->brw
;
294 struct brw_cache_item
*item
= CALLOC_STRUCT(brw_cache_item
);
298 item
->cache_id
= cache_id
;
299 item
->size
= data_size
;
301 item
->key_size
= key_size
;
302 item
->aux_size
= aux_size
;
303 hash
= hash_key(item
);
306 /* If we can find a matching prog/prog_data combo in the cache
307 * already, then reuse the existing stuff. This will mean not
308 * flagging CACHE_NEW_* when transitioning between the two
309 * equivalent hash keys. This is notably useful for programs
310 * generating shaders at runtime, where multiple shaders may
311 * compile to the thing in our backend.
313 if (!brw_try_upload_using_copy(cache
, item
, data
, aux
)) {
314 brw_upload_item_data(cache
, item
, data
);
317 /* Set up the memory containing the key and aux_data */
318 tmp
= malloc(key_size
+ aux_size
);
320 memcpy(tmp
, key
, key_size
);
321 memcpy(tmp
+ key_size
, aux
, aux_size
);
325 if (cache
->n_items
> cache
->size
* 1.5)
329 item
->next
= cache
->items
[hash
];
330 cache
->items
[hash
] = item
;
333 /* Copy data to the buffer */
335 memcpy((char *) cache
->bo
->virtual + item
->offset
, data
, data_size
);
337 drm_intel_bo_subdata(cache
->bo
, item
->offset
, data_size
, data
);
340 *out_offset
= item
->offset
;
341 *(void **)out_aux
= (void *)((char *)item
->key
+ item
->key_size
);
342 cache
->brw
->state
.dirty
.brw
|= 1 << cache_id
;
346 brw_init_caches(struct brw_context
*brw
)
348 struct brw_cache
*cache
= &brw
->cache
;
355 calloc(cache
->size
, sizeof(struct brw_cache_item
*));
357 cache
->bo
= drm_intel_bo_alloc(brw
->bufmgr
,
361 drm_intel_gem_bo_map_unsynchronized(cache
->bo
);
363 cache
->aux_compare
[BRW_CACHE_VS_PROG
] = brw_vs_prog_data_compare
;
364 cache
->aux_compare
[BRW_CACHE_GS_PROG
] = brw_gs_prog_data_compare
;
365 cache
->aux_compare
[BRW_CACHE_FS_PROG
] = brw_wm_prog_data_compare
;
366 cache
->aux_free
[BRW_CACHE_VS_PROG
] = brw_stage_prog_data_free
;
367 cache
->aux_free
[BRW_CACHE_GS_PROG
] = brw_stage_prog_data_free
;
368 cache
->aux_free
[BRW_CACHE_FS_PROG
] = brw_stage_prog_data_free
;
372 brw_clear_cache(struct brw_context
*brw
, struct brw_cache
*cache
)
374 struct brw_cache_item
*c
, *next
;
377 DBG("%s\n", __FUNCTION__
);
379 for (i
= 0; i
< cache
->size
; i
++) {
380 for (c
= cache
->items
[i
]; c
; c
= next
) {
382 if (cache
->aux_free
[c
->cache_id
]) {
383 const void *item_aux
= c
->key
+ c
->key_size
;
384 cache
->aux_free
[c
->cache_id
](item_aux
);
386 free((void *)c
->key
);
389 cache
->items
[i
] = NULL
;
394 /* Start putting programs into the start of the BO again, since
395 * we'll never find the old results.
397 cache
->next_offset
= 0;
399 /* We need to make sure that the programs get regenerated, since
400 * any offsets leftover in brw_context will no longer be valid.
402 brw
->state
.dirty
.mesa
|= ~0;
403 brw
->state
.dirty
.brw
|= ~0ull;
404 intel_batchbuffer_flush(brw
);
408 brw_state_cache_check_size(struct brw_context
*brw
)
410 /* un-tuned guess. Each object is generally a page, so 2000 of them is 8 MB of
413 if (brw
->cache
.n_items
> 2000) {
414 perf_debug("Exceeded state cache size limit. Clearing the set "
415 "of compiled programs, which will trigger recompiles\n");
416 brw_clear_cache(brw
, &brw
->cache
);
422 brw_destroy_cache(struct brw_context
*brw
, struct brw_cache
*cache
)
425 DBG("%s\n", __FUNCTION__
);
428 drm_intel_bo_unmap(cache
->bo
);
429 drm_intel_bo_unreference(cache
->bo
);
431 brw_clear_cache(brw
, cache
);
439 brw_destroy_caches(struct brw_context
*brw
)
441 brw_destroy_cache(brw
, &brw
->cache
);