src/mesa/drivers/dri/i965/brw_state_dump.c

   1 /*
   2  * Copyright © 2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "main/mtypes.h"
  29 #include "intel_batchbuffer.h"
  30
  31 #include "brw_context.h"
  32 #include "brw_defines.h"
  33
  34 /**
  35  * Prints out a header, the contents, and the message associated with
  36  * the hardware state data given.
  37  *
  38  * \param name Name of the state object
  39  * \param data Pointer to the base of the state object
  40  * \param hw_offset Hardware offset of the base of the state data.
  41  * \param index Index of the DWORD being output.
  42  */
  43 static void
  44 state_out(const char *name, void *data, uint32_t hw_offset, int index,
  45           char *fmt, ...)
  46 {
  47     va_list va;
  48
  49     fprintf(stderr, "%8s: 0x%08x: 0x%08x: ",
  50             name, hw_offset + index * 4, ((uint32_t *)data)[index]);
  51     va_start(va, fmt);
  52     vfprintf(stderr, fmt, va);
  53     va_end(va);
  54 }
  55
  56 /** Generic, undecoded state buffer debug printout */
  57 static void
  58 state_struct_out(const char *name, drm_intel_bo *buffer,
  59                  unsigned int offset, unsigned int size)
  60 {
  61    int i;
  62
  63    if (buffer == NULL)
  64       return;
  65
  66    drm_intel_bo_map(buffer, GL_FALSE);
  67    for (i = 0; i < size / 4; i++) {
  68       state_out(name, buffer->virtual + offset, buffer->offset + offset, i,
  69                 "dword %d\n", i);
  70    }
  71    drm_intel_bo_unmap(buffer);
  72 }
  73
  74 static const char *
  75 get_965_surfacetype(unsigned int surfacetype)
  76 {
  77     switch (surfacetype) {
  78     case 0: return "1D";
  79     case 1: return "2D";
  80     case 2: return "3D";
  81     case 3: return "CUBE";
  82     case 4: return "BUFFER";
  83     case 7: return "NULL";
  84     default: return "unknown";
  85     }
  86 }
  87
  88 static const char *
  89 get_965_surface_format(unsigned int surface_format)
  90 {
  91     switch (surface_format) {
  92     case 0x000: return "r32g32b32a32_float";
  93     case 0x0c1: return "b8g8r8a8_unorm";
  94     case 0x100: return "b5g6r5_unorm";
  95     case 0x102: return "b5g5r5a1_unorm";
  96     case 0x104: return "b4g4r4a4_unorm";
  97     default: return "unknown";
  98     }
  99 }
 100
 101 static void dump_wm_surface_state(struct brw_context *brw)
 102 {
 103    dri_bo *bo;
 104    GLubyte *base;
 105    int i;
 106
 107    bo = brw->intel.batch.bo;
 108    drm_intel_bo_map(bo, GL_FALSE);
 109    base = bo->virtual;
 110
 111    for (i = 0; i < brw->wm.nr_surfaces; i++) {
 112       unsigned int surfoff;
 113       uint32_t *surf;
 114       char name[20];
 115
 116       if (brw->wm.surf_offset[i] == 0) {
 117          fprintf(stderr, "WM SURF%d: NULL\n", i);
 118          continue;
 119       }
 120       surfoff = bo->offset + brw->wm.surf_offset[i];
 121       surf = (uint32_t *)(base + brw->wm.surf_offset[i]);
 122
 123       sprintf(name, "WM SURF%d", i);
 124       state_out(name, surf, surfoff, 0, "%s %s\n",
 125                 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
 126                 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)));
 127       state_out(name, surf, surfoff, 1, "offset\n");
 128       state_out(name, surf, surfoff, 2, "%dx%d size, %d mips\n",
 129                 GET_FIELD(surf[2], BRW_SURFACE_WIDTH) + 1,
 130                 GET_FIELD(surf[2], BRW_SURFACE_HEIGHT) + 1);
 131       state_out(name, surf, surfoff, 3, "pitch %d, %s tiled\n",
 132                 GET_FIELD(surf[3], BRW_SURFACE_PITCH) + 1,
 133                 (surf[3] & BRW_SURFACE_TILED) ?
 134                 ((surf[3] & BRW_SURFACE_TILED_Y) ? "Y" : "X") : "not");
 135       state_out(name, surf, surfoff, 4, "mip base %d\n",
 136                 GET_FIELD(surf[4], BRW_SURFACE_MIN_LOD));
 137       state_out(name, surf, surfoff, 5, "x,y offset: %d,%d\n",
 138                 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
 139                 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
 140    }
 141    drm_intel_bo_unmap(bo);
 142 }
 143
 144 static void dump_gen7_surface_state(struct brw_context *brw)
 145 {
 146    dri_bo *bo;
 147    GLubyte *base;
 148    int i;
 149
 150    bo = brw->intel.batch.bo;
 151    drm_intel_bo_map(bo, GL_FALSE);
 152    base = bo->virtual;
 153
 154    for (i = 0; i < brw->wm.nr_surfaces; i++) {
 155       unsigned int surfoff;
 156       struct gen7_surface_state *surf;
 157       char name[20];
 158
 159       if (brw->wm.surf_offset[i] == 0) {
 160          fprintf(stderr, "WM SURF%d: NULL\n", i);
 161          continue;
 162       }
 163       surfoff = bo->offset + brw->wm.surf_offset[i];
 164       surf = (struct gen7_surface_state *) (base + brw->wm.surf_offset[i]);
 165
 166       sprintf(name, "WM SURF%d", i);
 167       state_out(name, surf, surfoff, 0, "%s %s\n",
 168                 get_965_surfacetype(surf->ss0.surface_type),
 169                 get_965_surface_format(surf->ss0.surface_format));
 170       state_out(name, surf, surfoff, 1, "offset\n");
 171       state_out(name, surf, surfoff, 2, "%dx%d size, %d mips\n",
 172                 surf->ss2.width + 1, surf->ss2.height + 1, surf->ss5.mip_count);
 173       state_out(name, surf, surfoff, 3, "pitch %d, %stiled\n",
 174                 surf->ss3.pitch + 1, surf->ss0.tiled_surface ? "" : "not ");
 175       state_out(name, surf, surfoff, 4, "mip base %d\n",
 176                 surf->ss5.min_lod);
 177       state_out(name, surf, surfoff, 5, "x,y offset: %d,%d\n",
 178                 surf->ss5.x_offset, surf->ss5.y_offset);
 179    }
 180    drm_intel_bo_unmap(bo);
 181 }
 182
 183 static void dump_wm_sampler_state(struct brw_context *brw)
 184 {
 185    struct intel_context *intel = &brw->intel;
 186    struct gl_context *ctx = &brw->intel.ctx;
 187    int i;
 188
 189    assert(intel->gen < 7);
 190
 191    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 192    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 193       unsigned int offset;
 194       uint32_t sdc_offset;
 195       struct brw_sampler_state *samp;
 196       char name[20];
 197
 198       if (!ctx->Texture.Unit[i]._ReallyEnabled) {
 199          fprintf(stderr, "WM SAMP%d: disabled\n", i);
 200          continue;
 201       }
 202
 203       offset = (intel->batch.bo->offset +
 204                 brw->wm.sampler_offset +
 205                 i * sizeof(struct brw_sampler_state));
 206       samp = (struct brw_sampler_state *)(intel->batch.bo->virtual +
 207                                           brw->wm.sampler_offset +
 208                                           i * sizeof(struct brw_sampler_state));
 209
 210       sprintf(name, "WM SAMP%d", i);
 211       state_out(name, samp, offset, 0, "filtering\n");
 212       state_out(name, samp, offset, 1, "wrapping, lod\n");
 213       state_out(name, samp, offset, 2, "default color pointer\n");
 214       state_out(name, samp, offset, 3, "chroma key, aniso\n");
 215
 216       sprintf(name, " WM SDC%d", i);
 217
 218       sdc_offset = intel->batch.bo->offset + brw->wm.sdc_offset[i];
 219       if (intel->gen >= 5) {
 220          struct gen5_sampler_default_color *sdc = (intel->batch.bo->virtual +
 221                                                    brw->wm.sdc_offset[i]);
 222          state_out(name, sdc, sdc_offset, 0, "unorm rgba\n");
 223          state_out(name, sdc, sdc_offset, 1, "r %f\n", sdc->f[0]);
 224          state_out(name, sdc, sdc_offset, 2, "b %f\n", sdc->f[1]);
 225          state_out(name, sdc, sdc_offset, 3, "g %f\n", sdc->f[2]);
 226          state_out(name, sdc, sdc_offset, 4, "a %f\n", sdc->f[3]);
 227          state_out(name, sdc, sdc_offset, 5, "half float rg\n");
 228          state_out(name, sdc, sdc_offset, 6, "half float ba\n");
 229          state_out(name, sdc, sdc_offset, 7, "u16 rg\n");
 230          state_out(name, sdc, sdc_offset, 8, "u16 ba\n");
 231          state_out(name, sdc, sdc_offset, 9, "s16 rg\n");
 232          state_out(name, sdc, sdc_offset, 10, "s16 ba\n");
 233          state_out(name, sdc, sdc_offset, 11, "s8 rgba\n");
 234       } else {
 235          struct brw_sampler_default_color *sdc = (intel->batch.bo->virtual +
 236                                                   brw->wm.sdc_offset[i]);
 237          state_out(name, sdc, sdc_offset, 0, "r %f\n", sdc->color[0]);
 238          state_out(name, sdc, sdc_offset, 1, "g %f\n", sdc->color[1]);
 239          state_out(name, sdc, sdc_offset, 2, "b %f\n", sdc->color[2]);
 240          state_out(name, sdc, sdc_offset, 3, "a %f\n", sdc->color[3]);
 241       }
 242    }
 243    drm_intel_bo_unmap(intel->batch.bo);
 244 }
 245
 246 static void dump_gen7_sampler_state(struct brw_context *brw)
 247 {
 248    struct intel_context *intel = &brw->intel;
 249    struct gl_context *ctx = &brw->intel.ctx;
 250    int i;
 251
 252    assert(intel->gen >= 7);
 253
 254    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 255    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 256       unsigned int offset;
 257       uint32_t sdc_offset;
 258       struct gen7_sampler_state *samp;
 259       char name[20];
 260
 261       if (!ctx->Texture.Unit[i]._ReallyEnabled) {
 262          fprintf(stderr, "WM SAMP%d: disabled\n", i);
 263          continue;
 264       }
 265
 266       offset = (intel->batch.bo->offset +
 267                 brw->wm.sampler_offset +
 268                 i * sizeof(struct gen7_sampler_state));
 269       samp = (struct gen7_sampler_state *)
 270              (intel->batch.bo->virtual + brw->wm.sampler_offset +
 271               i * sizeof(struct gen7_sampler_state));
 272
 273       sprintf(name, "WM SAMP%d", i);
 274       state_out(name, samp, offset, 0, "filtering\n");
 275       state_out(name, samp, offset, 1, "wrapping, lod\n");
 276       state_out(name, samp, offset, 2, "default color pointer\n");
 277       state_out(name, samp, offset, 3, "chroma key, aniso\n");
 278
 279       sprintf(name, " WM SDC%d", i);
 280
 281       sdc_offset = intel->batch.bo->offset + brw->wm.sdc_offset[i];
 282       struct brw_sampler_default_color *sdc =
 283          intel->batch.bo->virtual + brw->wm.sdc_offset[i];
 284       state_out(name, sdc, sdc_offset, 0, "r %f\n", sdc->color[0]);
 285       state_out(name, sdc, sdc_offset, 1, "g %f\n", sdc->color[1]);
 286       state_out(name, sdc, sdc_offset, 2, "b %f\n", sdc->color[2]);
 287       state_out(name, sdc, sdc_offset, 3, "a %f\n", sdc->color[3]);
 288    }
 289    drm_intel_bo_unmap(intel->batch.bo);
 290 }
 291
 292
 293 static void dump_sf_viewport_state(struct brw_context *brw)
 294 {
 295    struct intel_context *intel = &brw->intel;
 296    const char *name = "SF VP";
 297    struct brw_sf_viewport *vp;
 298    uint32_t vp_off;
 299
 300    assert(intel->gen < 7);
 301
 302    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 303
 304    vp = intel->batch.bo->virtual + brw->sf.vp_offset;
 305    vp_off = intel->batch.bo->offset + brw->sf.vp_offset;
 306
 307    state_out(name, vp, vp_off, 0, "m00 = %f\n", vp->viewport.m00);
 308    state_out(name, vp, vp_off, 1, "m11 = %f\n", vp->viewport.m11);
 309    state_out(name, vp, vp_off, 2, "m22 = %f\n", vp->viewport.m22);
 310    state_out(name, vp, vp_off, 3, "m30 = %f\n", vp->viewport.m30);
 311    state_out(name, vp, vp_off, 4, "m31 = %f\n", vp->viewport.m31);
 312    state_out(name, vp, vp_off, 5, "m32 = %f\n", vp->viewport.m32);
 313
 314    state_out(name, vp, vp_off, 6, "top left = %d,%d\n",
 315              vp->scissor.xmin, vp->scissor.ymin);
 316    state_out(name, vp, vp_off, 7, "bottom right = %d,%d\n",
 317              vp->scissor.xmax, vp->scissor.ymax);
 318
 319    drm_intel_bo_unmap(intel->batch.bo);
 320 }
 321
 322 static void dump_clip_viewport_state(struct brw_context *brw,
 323                                      uint32_t offset)
 324 {
 325    struct intel_context *intel = &brw->intel;
 326    const char *name = "CLIP VP";
 327    struct brw_clipper_viewport *vp;
 328    uint32_t vp_off;
 329
 330    assert(intel->gen < 7);
 331
 332    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 333
 334    vp = intel->batch.bo->virtual + offset;
 335    vp_off = intel->batch.bo->offset + offset;
 336
 337    state_out(name, vp, vp_off, 0, "xmin = %f\n", vp->xmin);
 338    state_out(name, vp, vp_off, 1, "xmax = %f\n", vp->xmax);
 339    state_out(name, vp, vp_off, 2, "ymin = %f\n", vp->ymin);
 340    state_out(name, vp, vp_off, 3, "ymax = %f\n", vp->ymax);
 341    drm_intel_bo_unmap(intel->batch.bo);
 342 }
 343
 344 static void dump_sf_clip_viewport_state(struct brw_context *brw)
 345 {
 346    struct intel_context *intel = &brw->intel;
 347    const char *name = "SF_CLIP VP";
 348    struct gen7_sf_clip_viewport *vp;
 349    uint32_t vp_off;
 350
 351    assert(intel->gen >= 7);
 352
 353    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 354
 355    vp = intel->batch.bo->virtual + brw->sf.vp_offset;
 356    vp_off = intel->batch.bo->offset + brw->sf.vp_offset;
 357
 358    state_out(name, vp, vp_off, 0, "m00 = %f\n", vp->viewport.m00);
 359    state_out(name, vp, vp_off, 1, "m11 = %f\n", vp->viewport.m11);
 360    state_out(name, vp, vp_off, 2, "m22 = %f\n", vp->viewport.m22);
 361    state_out(name, vp, vp_off, 3, "m30 = %f\n", vp->viewport.m30);
 362    state_out(name, vp, vp_off, 4, "m31 = %f\n", vp->viewport.m31);
 363    state_out(name, vp, vp_off, 5, "m32 = %f\n", vp->viewport.m32);
 364    state_out(name, vp, vp_off, 6, "guardband xmin = %f\n", vp->guardband.xmin);
 365    state_out(name, vp, vp_off, 7, "guardband xmax = %f\n", vp->guardband.xmax);
 366    state_out(name, vp, vp_off, 8, "guardband ymin = %f\n", vp->guardband.ymin);
 367    state_out(name, vp, vp_off, 9, "guardband ymax = %f\n", vp->guardband.ymax);
 368    drm_intel_bo_unmap(intel->batch.bo);
 369 }
 370
 371
 372 static void dump_cc_viewport_state(struct brw_context *brw)
 373 {
 374    struct intel_context *intel = &brw->intel;
 375    const char *name = "CC VP";
 376    struct brw_cc_viewport *vp;
 377    uint32_t vp_off;
 378
 379    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 380
 381    vp = intel->batch.bo->virtual + brw->cc.vp_offset;
 382    vp_off = intel->batch.bo->offset + brw->cc.vp_offset;
 383
 384    state_out(name, vp, vp_off, 0, "min_depth = %f\n", vp->min_depth);
 385    state_out(name, vp, vp_off, 1, "max_depth = %f\n", vp->max_depth);
 386    drm_intel_bo_unmap(intel->batch.bo);
 387 }
 388
 389 static void dump_depth_stencil_state(struct brw_context *brw)
 390 {
 391    struct intel_context *intel = &brw->intel;
 392    const char *name = "DEPTH STENCIL";
 393    struct gen6_depth_stencil_state *ds;
 394    uint32_t ds_off;
 395
 396    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 397
 398    ds = intel->batch.bo->virtual + brw->cc.depth_stencil_state_offset;
 399    ds_off = intel->batch.bo->offset + brw->cc.depth_stencil_state_offset;
 400
 401    state_out(name, ds, ds_off, 0, "stencil %sable, func %d, write %sable\n",
 402                 ds->ds0.stencil_enable ? "en" : "dis",
 403                 ds->ds0.stencil_func,
 404                 ds->ds0.stencil_write_enable ? "en" : "dis");
 405    state_out(name, ds, ds_off, 1, "stencil test mask 0x%x, write mask 0x%x\n",
 406                 ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
 407    state_out(name, ds, ds_off, 2, "depth test %sable, func %d, write %sable\n",
 408                 ds->ds2.depth_test_enable ? "en" : "dis",
 409                 ds->ds2.depth_test_func,
 410                 ds->ds2.depth_write_enable ? "en" : "dis");
 411    drm_intel_bo_unmap(intel->batch.bo);
 412 }
 413
 414 static void dump_cc_state(struct brw_context *brw)
 415 {
 416    const char *name = "CC";
 417    struct gen6_color_calc_state *cc;
 418    uint32_t cc_off;
 419    dri_bo *bo = brw->intel.batch.bo;
 420
 421    if (brw->cc.state_offset == 0)
 422         return;
 423
 424    drm_intel_bo_map(bo, GL_FALSE);
 425    cc = bo->virtual + brw->cc.state_offset;
 426    cc_off = bo->offset + brw->cc.state_offset;
 427
 428    state_out(name, cc, cc_off, 0, "alpha test format %s, round disable %d, stencil ref %d,"
 429                 "bf stencil ref %d\n",
 430                 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
 431                 cc->cc0.round_disable,
 432                 cc->cc0.stencil_ref,
 433                 cc->cc0.bf_stencil_ref);
 434    state_out(name, cc, cc_off, 1, "\n");
 435    state_out(name, cc, cc_off, 2, "constant red %f\n", cc->constant_r);
 436    state_out(name, cc, cc_off, 3, "constant green %f\n", cc->constant_g);
 437    state_out(name, cc, cc_off, 4, "constant blue %f\n", cc->constant_b);
 438    state_out(name, cc, cc_off, 5, "constant alpha %f\n", cc->constant_a);
 439
 440    drm_intel_bo_unmap(bo);
 441
 442 }
 443
 444 static void dump_blend_state(struct brw_context *brw)
 445 {
 446    struct intel_context *intel = &brw->intel;
 447    const char *name = "BLEND";
 448    struct gen6_blend_state *blend;
 449    uint32_t blend_off;
 450
 451    drm_intel_bo_map(intel->batch.bo, GL_FALSE);
 452
 453    blend = intel->batch.bo->virtual + brw->cc.blend_state_offset;
 454    blend_off = intel->batch.bo->offset + brw->cc.blend_state_offset;
 455
 456    state_out(name, blend, blend_off, 0, "\n");
 457    state_out(name, blend, blend_off, 1, "\n");
 458
 459    drm_intel_bo_unmap(intel->batch.bo);
 460
 461 }
 462
 463 static void brw_debug_prog(struct brw_context *brw,
 464                            const char *name, uint32_t prog_offset)
 465 {
 466    unsigned int i;
 467    uint32_t *data;
 468
 469    drm_intel_bo_map(brw->cache.bo, false);
 470
 471    data = brw->cache.bo->virtual + prog_offset;
 472
 473    for (i = 0; i < brw->cache.bo->size / 4 / 4; i++) {
 474       fprintf(stderr, "%8s: 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 475               name, (unsigned int)brw->cache.bo->offset + i * 4 * 4,
 476               data[i * 4], data[i * 4 + 1], data[i * 4 + 2], data[i * 4 + 3]);
 477       /* Stop at the end of the program.  It'd be nice to keep track of the actual
 478        * intended program size instead of guessing like this.
 479        */
 480       if (data[i * 4 + 0] == 0 &&
 481           data[i * 4 + 1] == 0 &&
 482           data[i * 4 + 2] == 0 &&
 483           data[i * 4 + 3] == 0)
 484          break;
 485    }
 486
 487    drm_intel_bo_unmap(brw->cache.bo);
 488 }
 489
 490 static void
 491 dump_state_batch(struct brw_context *brw)
 492 {
 493    int i;
 494
 495    for (i = 0; i < brw->state_batch_count; i++) {
 496       switch (brw->state_batch_list[i].type) {
 497       case AUB_TRACE_CLIP_VP_STATE:
 498          dump_clip_viewport_state(brw, brw->state_batch_list[i].offset);
 499          break;
 500       default:
 501          break;
 502       }
 503    }
 504 }
 505
 506 /**
 507  * Print additional debug information associated with the batchbuffer
 508  * when DEBUG_BATCH is set.
 509  *
 510  * For 965, this means mapping the state buffers that would have been referenced
 511  * by the batchbuffer and dumping them.
 512  *
 513  * The buffer offsets printed rely on the buffer containing the last offset
 514  * it was validated at.
 515  */
 516 void brw_debug_batch(struct intel_context *intel)
 517 {
 518    struct brw_context *brw = brw_context(&intel->ctx);
 519
 520    state_struct_out("WM bind",
 521                     brw->intel.batch.bo,
 522                     brw->wm.bind_bo_offset,
 523                     4 * brw->wm.nr_surfaces);
 524    if (intel->gen < 7) {
 525       dump_wm_surface_state(brw);
 526       dump_wm_sampler_state(brw);
 527    } else {
 528       dump_gen7_surface_state(brw);
 529       dump_gen7_sampler_state(brw);
 530    }
 531
 532    if (intel->gen < 6)
 533        state_struct_out("VS", intel->batch.bo, brw->vs.state_offset,
 534                         sizeof(struct brw_vs_unit_state));
 535    brw_debug_prog(brw, "VS prog", brw->vs.prog_offset);
 536
 537    if (intel->gen < 6)
 538        state_struct_out("GS", intel->batch.bo, brw->gs.state_offset,
 539                         sizeof(struct brw_gs_unit_state));
 540    if (brw->gs.prog_active) {
 541       brw_debug_prog(brw, "GS prog", brw->gs.prog_offset);
 542    }
 543
 544    if (intel->gen < 6) {
 545       state_struct_out("SF", intel->batch.bo, brw->sf.state_offset,
 546                        sizeof(struct brw_sf_unit_state));
 547       brw_debug_prog(brw, "SF prog", brw->sf.prog_offset);
 548    }
 549    if (intel->gen >= 7)
 550       dump_sf_clip_viewport_state(brw);
 551    else
 552       dump_sf_viewport_state(brw);
 553
 554    if (intel->gen < 6)
 555        state_struct_out("WM", intel->batch.bo, brw->wm.state_offset,
 556                         sizeof(struct brw_wm_unit_state));
 557    brw_debug_prog(brw, "WM prog", brw->wm.prog_offset);
 558
 559    if (intel->gen >= 6) {
 560         dump_cc_viewport_state(brw);
 561         dump_depth_stencil_state(brw);
 562         dump_cc_state(brw);
 563         dump_blend_state(brw);
 564    }
 565
 566    dump_state_batch(brw);
 567 }