2 * Copyright © 2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "main/mtypes.h"
29 #include "intel_batchbuffer.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
35 * Prints out a header, the contents, and the message associated with
36 * the hardware state data given.
38 * \param name Name of the state object
39 * \param data Pointer to the base of the state object
40 * \param hw_offset Hardware offset of the base of the state data.
41 * \param index Index of the DWORD being output.
44 state_out(const char *name
, void *data
, uint32_t hw_offset
, int index
,
49 fprintf(stderr
, "%8s: 0x%08x: 0x%08x: ",
50 name
, hw_offset
+ index
* 4, ((uint32_t *)data
)[index
]);
52 vfprintf(stderr
, fmt
, va
);
56 /** Generic, undecoded state buffer debug printout */
58 state_struct_out(const char *name
, drm_intel_bo
*buffer
,
59 unsigned int offset
, unsigned int size
)
66 drm_intel_bo_map(buffer
, GL_FALSE
);
67 for (i
= 0; i
< size
/ 4; i
++) {
68 state_out(name
, buffer
->virtual + offset
, buffer
->offset
+ offset
, i
,
71 drm_intel_bo_unmap(buffer
);
75 get_965_surfacetype(unsigned int surfacetype
)
77 switch (surfacetype
) {
81 case 3: return "CUBE";
82 case 4: return "BUFFER";
83 case 7: return "NULL";
84 default: return "unknown";
89 get_965_surface_format(unsigned int surface_format
)
91 switch (surface_format
) {
92 case 0x000: return "r32g32b32a32_float";
93 case 0x0c1: return "b8g8r8a8_unorm";
94 case 0x100: return "b5g6r5_unorm";
95 case 0x102: return "b5g5r5a1_unorm";
96 case 0x104: return "b4g4r4a4_unorm";
97 default: return "unknown";
101 static void dump_wm_surface_state(struct brw_context
*brw
)
107 bo
= brw
->intel
.batch
.bo
;
108 drm_intel_bo_map(bo
, GL_FALSE
);
111 for (i
= 0; i
< brw
->wm
.nr_surfaces
; i
++) {
112 unsigned int surfoff
;
116 if (brw
->wm
.surf_offset
[i
] == 0) {
117 fprintf(stderr
, "WM SURF%d: NULL\n", i
);
120 surfoff
= bo
->offset
+ brw
->wm
.surf_offset
[i
];
121 surf
= (uint32_t *)(base
+ brw
->wm
.surf_offset
[i
]);
123 sprintf(name
, "WM SURF%d", i
);
124 state_out(name
, surf
, surfoff
, 0, "%s %s\n",
125 get_965_surfacetype(GET_FIELD(surf
[0], BRW_SURFACE_TYPE
)),
126 get_965_surface_format(GET_FIELD(surf
[0], BRW_SURFACE_FORMAT
)));
127 state_out(name
, surf
, surfoff
, 1, "offset\n");
128 state_out(name
, surf
, surfoff
, 2, "%dx%d size, %d mips\n",
129 GET_FIELD(surf
[2], BRW_SURFACE_WIDTH
) + 1,
130 GET_FIELD(surf
[2], BRW_SURFACE_HEIGHT
) + 1);
131 state_out(name
, surf
, surfoff
, 3, "pitch %d, %s tiled\n",
132 GET_FIELD(surf
[3], BRW_SURFACE_PITCH
) + 1,
133 (surf
[3] & BRW_SURFACE_TILED
) ?
134 ((surf
[3] & BRW_SURFACE_TILED_Y
) ? "Y" : "X") : "not");
135 state_out(name
, surf
, surfoff
, 4, "mip base %d\n",
136 GET_FIELD(surf
[4], BRW_SURFACE_MIN_LOD
));
137 state_out(name
, surf
, surfoff
, 5, "x,y offset: %d,%d\n",
138 GET_FIELD(surf
[5], BRW_SURFACE_X_OFFSET
),
139 GET_FIELD(surf
[5], BRW_SURFACE_Y_OFFSET
));
141 drm_intel_bo_unmap(bo
);
144 static void dump_gen7_surface_state(struct brw_context
*brw
)
150 bo
= brw
->intel
.batch
.bo
;
151 drm_intel_bo_map(bo
, GL_FALSE
);
154 for (i
= 0; i
< brw
->wm
.nr_surfaces
; i
++) {
155 unsigned int surfoff
;
156 struct gen7_surface_state
*surf
;
159 if (brw
->wm
.surf_offset
[i
] == 0) {
160 fprintf(stderr
, "WM SURF%d: NULL\n", i
);
163 surfoff
= bo
->offset
+ brw
->wm
.surf_offset
[i
];
164 surf
= (struct gen7_surface_state
*) (base
+ brw
->wm
.surf_offset
[i
]);
166 sprintf(name
, "WM SURF%d", i
);
167 state_out(name
, surf
, surfoff
, 0, "%s %s\n",
168 get_965_surfacetype(surf
->ss0
.surface_type
),
169 get_965_surface_format(surf
->ss0
.surface_format
));
170 state_out(name
, surf
, surfoff
, 1, "offset\n");
171 state_out(name
, surf
, surfoff
, 2, "%dx%d size, %d mips\n",
172 surf
->ss2
.width
+ 1, surf
->ss2
.height
+ 1, surf
->ss5
.mip_count
);
173 state_out(name
, surf
, surfoff
, 3, "pitch %d, %stiled\n",
174 surf
->ss3
.pitch
+ 1, surf
->ss0
.tiled_surface
? "" : "not ");
175 state_out(name
, surf
, surfoff
, 4, "mip base %d\n",
177 state_out(name
, surf
, surfoff
, 5, "x,y offset: %d,%d\n",
178 surf
->ss5
.x_offset
, surf
->ss5
.y_offset
);
180 drm_intel_bo_unmap(bo
);
183 static void dump_wm_sampler_state(struct brw_context
*brw
)
185 struct intel_context
*intel
= &brw
->intel
;
186 struct gl_context
*ctx
= &brw
->intel
.ctx
;
189 assert(intel
->gen
< 7);
191 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
192 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
195 struct brw_sampler_state
*samp
;
198 if (!ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
199 fprintf(stderr
, "WM SAMP%d: disabled\n", i
);
203 offset
= (intel
->batch
.bo
->offset
+
204 brw
->wm
.sampler_offset
+
205 i
* sizeof(struct brw_sampler_state
));
206 samp
= (struct brw_sampler_state
*)(intel
->batch
.bo
->virtual +
207 brw
->wm
.sampler_offset
+
208 i
* sizeof(struct brw_sampler_state
));
210 sprintf(name
, "WM SAMP%d", i
);
211 state_out(name
, samp
, offset
, 0, "filtering\n");
212 state_out(name
, samp
, offset
, 1, "wrapping, lod\n");
213 state_out(name
, samp
, offset
, 2, "default color pointer\n");
214 state_out(name
, samp
, offset
, 3, "chroma key, aniso\n");
216 sprintf(name
, " WM SDC%d", i
);
218 sdc_offset
= intel
->batch
.bo
->offset
+ brw
->wm
.sdc_offset
[i
];
219 if (intel
->gen
>= 5) {
220 struct gen5_sampler_default_color
*sdc
= (intel
->batch
.bo
->virtual +
221 brw
->wm
.sdc_offset
[i
]);
222 state_out(name
, sdc
, sdc_offset
, 0, "unorm rgba\n");
223 state_out(name
, sdc
, sdc_offset
, 1, "r %f\n", sdc
->f
[0]);
224 state_out(name
, sdc
, sdc_offset
, 2, "b %f\n", sdc
->f
[1]);
225 state_out(name
, sdc
, sdc_offset
, 3, "g %f\n", sdc
->f
[2]);
226 state_out(name
, sdc
, sdc_offset
, 4, "a %f\n", sdc
->f
[3]);
227 state_out(name
, sdc
, sdc_offset
, 5, "half float rg\n");
228 state_out(name
, sdc
, sdc_offset
, 6, "half float ba\n");
229 state_out(name
, sdc
, sdc_offset
, 7, "u16 rg\n");
230 state_out(name
, sdc
, sdc_offset
, 8, "u16 ba\n");
231 state_out(name
, sdc
, sdc_offset
, 9, "s16 rg\n");
232 state_out(name
, sdc
, sdc_offset
, 10, "s16 ba\n");
233 state_out(name
, sdc
, sdc_offset
, 11, "s8 rgba\n");
235 struct brw_sampler_default_color
*sdc
= (intel
->batch
.bo
->virtual +
236 brw
->wm
.sdc_offset
[i
]);
237 state_out(name
, sdc
, sdc_offset
, 0, "r %f\n", sdc
->color
[0]);
238 state_out(name
, sdc
, sdc_offset
, 1, "g %f\n", sdc
->color
[1]);
239 state_out(name
, sdc
, sdc_offset
, 2, "b %f\n", sdc
->color
[2]);
240 state_out(name
, sdc
, sdc_offset
, 3, "a %f\n", sdc
->color
[3]);
243 drm_intel_bo_unmap(intel
->batch
.bo
);
246 static void dump_gen7_sampler_state(struct brw_context
*brw
)
248 struct intel_context
*intel
= &brw
->intel
;
249 struct gl_context
*ctx
= &brw
->intel
.ctx
;
252 assert(intel
->gen
>= 7);
254 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
255 for (i
= 0; i
< BRW_MAX_TEX_UNIT
; i
++) {
258 struct gen7_sampler_state
*samp
;
261 if (!ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
262 fprintf(stderr
, "WM SAMP%d: disabled\n", i
);
266 offset
= (intel
->batch
.bo
->offset
+
267 brw
->wm
.sampler_offset
+
268 i
* sizeof(struct gen7_sampler_state
));
269 samp
= (struct gen7_sampler_state
*)
270 (intel
->batch
.bo
->virtual + brw
->wm
.sampler_offset
+
271 i
* sizeof(struct gen7_sampler_state
));
273 sprintf(name
, "WM SAMP%d", i
);
274 state_out(name
, samp
, offset
, 0, "filtering\n");
275 state_out(name
, samp
, offset
, 1, "wrapping, lod\n");
276 state_out(name
, samp
, offset
, 2, "default color pointer\n");
277 state_out(name
, samp
, offset
, 3, "chroma key, aniso\n");
279 sprintf(name
, " WM SDC%d", i
);
281 sdc_offset
= intel
->batch
.bo
->offset
+ brw
->wm
.sdc_offset
[i
];
282 struct brw_sampler_default_color
*sdc
=
283 intel
->batch
.bo
->virtual + brw
->wm
.sdc_offset
[i
];
284 state_out(name
, sdc
, sdc_offset
, 0, "r %f\n", sdc
->color
[0]);
285 state_out(name
, sdc
, sdc_offset
, 1, "g %f\n", sdc
->color
[1]);
286 state_out(name
, sdc
, sdc_offset
, 2, "b %f\n", sdc
->color
[2]);
287 state_out(name
, sdc
, sdc_offset
, 3, "a %f\n", sdc
->color
[3]);
289 drm_intel_bo_unmap(intel
->batch
.bo
);
293 static void dump_sf_viewport_state(struct brw_context
*brw
,
296 struct intel_context
*intel
= &brw
->intel
;
297 const char *name
= "SF VP";
298 struct brw_sf_viewport
*vp
;
301 assert(intel
->gen
< 7);
303 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
305 vp
= intel
->batch
.bo
->virtual + offset
;
306 vp_off
= intel
->batch
.bo
->offset
+ offset
;
308 state_out(name
, vp
, vp_off
, 0, "m00 = %f\n", vp
->viewport
.m00
);
309 state_out(name
, vp
, vp_off
, 1, "m11 = %f\n", vp
->viewport
.m11
);
310 state_out(name
, vp
, vp_off
, 2, "m22 = %f\n", vp
->viewport
.m22
);
311 state_out(name
, vp
, vp_off
, 3, "m30 = %f\n", vp
->viewport
.m30
);
312 state_out(name
, vp
, vp_off
, 4, "m31 = %f\n", vp
->viewport
.m31
);
313 state_out(name
, vp
, vp_off
, 5, "m32 = %f\n", vp
->viewport
.m32
);
315 state_out(name
, vp
, vp_off
, 6, "top left = %d,%d\n",
316 vp
->scissor
.xmin
, vp
->scissor
.ymin
);
317 state_out(name
, vp
, vp_off
, 7, "bottom right = %d,%d\n",
318 vp
->scissor
.xmax
, vp
->scissor
.ymax
);
320 drm_intel_bo_unmap(intel
->batch
.bo
);
323 static void dump_clip_viewport_state(struct brw_context
*brw
,
326 struct intel_context
*intel
= &brw
->intel
;
327 const char *name
= "CLIP VP";
328 struct brw_clipper_viewport
*vp
;
331 assert(intel
->gen
< 7);
333 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
335 vp
= intel
->batch
.bo
->virtual + offset
;
336 vp_off
= intel
->batch
.bo
->offset
+ offset
;
338 state_out(name
, vp
, vp_off
, 0, "xmin = %f\n", vp
->xmin
);
339 state_out(name
, vp
, vp_off
, 1, "xmax = %f\n", vp
->xmax
);
340 state_out(name
, vp
, vp_off
, 2, "ymin = %f\n", vp
->ymin
);
341 state_out(name
, vp
, vp_off
, 3, "ymax = %f\n", vp
->ymax
);
342 drm_intel_bo_unmap(intel
->batch
.bo
);
345 static void dump_sf_clip_viewport_state(struct brw_context
*brw
,
348 struct intel_context
*intel
= &brw
->intel
;
349 const char *name
= "SF_CLIP VP";
350 struct gen7_sf_clip_viewport
*vp
;
353 assert(intel
->gen
>= 7);
355 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
357 vp
= intel
->batch
.bo
->virtual + offset
;
358 vp_off
= intel
->batch
.bo
->offset
+ offset
;
360 state_out(name
, vp
, vp_off
, 0, "m00 = %f\n", vp
->viewport
.m00
);
361 state_out(name
, vp
, vp_off
, 1, "m11 = %f\n", vp
->viewport
.m11
);
362 state_out(name
, vp
, vp_off
, 2, "m22 = %f\n", vp
->viewport
.m22
);
363 state_out(name
, vp
, vp_off
, 3, "m30 = %f\n", vp
->viewport
.m30
);
364 state_out(name
, vp
, vp_off
, 4, "m31 = %f\n", vp
->viewport
.m31
);
365 state_out(name
, vp
, vp_off
, 5, "m32 = %f\n", vp
->viewport
.m32
);
366 state_out(name
, vp
, vp_off
, 6, "guardband xmin = %f\n", vp
->guardband
.xmin
);
367 state_out(name
, vp
, vp_off
, 7, "guardband xmax = %f\n", vp
->guardband
.xmax
);
368 state_out(name
, vp
, vp_off
, 8, "guardband ymin = %f\n", vp
->guardband
.ymin
);
369 state_out(name
, vp
, vp_off
, 9, "guardband ymax = %f\n", vp
->guardband
.ymax
);
370 drm_intel_bo_unmap(intel
->batch
.bo
);
374 static void dump_cc_viewport_state(struct brw_context
*brw
)
376 struct intel_context
*intel
= &brw
->intel
;
377 const char *name
= "CC VP";
378 struct brw_cc_viewport
*vp
;
381 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
383 vp
= intel
->batch
.bo
->virtual + brw
->cc
.vp_offset
;
384 vp_off
= intel
->batch
.bo
->offset
+ brw
->cc
.vp_offset
;
386 state_out(name
, vp
, vp_off
, 0, "min_depth = %f\n", vp
->min_depth
);
387 state_out(name
, vp
, vp_off
, 1, "max_depth = %f\n", vp
->max_depth
);
388 drm_intel_bo_unmap(intel
->batch
.bo
);
391 static void dump_depth_stencil_state(struct brw_context
*brw
)
393 struct intel_context
*intel
= &brw
->intel
;
394 const char *name
= "DEPTH STENCIL";
395 struct gen6_depth_stencil_state
*ds
;
398 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
400 ds
= intel
->batch
.bo
->virtual + brw
->cc
.depth_stencil_state_offset
;
401 ds_off
= intel
->batch
.bo
->offset
+ brw
->cc
.depth_stencil_state_offset
;
403 state_out(name
, ds
, ds_off
, 0, "stencil %sable, func %d, write %sable\n",
404 ds
->ds0
.stencil_enable
? "en" : "dis",
405 ds
->ds0
.stencil_func
,
406 ds
->ds0
.stencil_write_enable
? "en" : "dis");
407 state_out(name
, ds
, ds_off
, 1, "stencil test mask 0x%x, write mask 0x%x\n",
408 ds
->ds1
.stencil_test_mask
, ds
->ds1
.stencil_write_mask
);
409 state_out(name
, ds
, ds_off
, 2, "depth test %sable, func %d, write %sable\n",
410 ds
->ds2
.depth_test_enable
? "en" : "dis",
411 ds
->ds2
.depth_test_func
,
412 ds
->ds2
.depth_write_enable
? "en" : "dis");
413 drm_intel_bo_unmap(intel
->batch
.bo
);
416 static void dump_cc_state(struct brw_context
*brw
)
418 const char *name
= "CC";
419 struct gen6_color_calc_state
*cc
;
421 dri_bo
*bo
= brw
->intel
.batch
.bo
;
423 if (brw
->cc
.state_offset
== 0)
426 drm_intel_bo_map(bo
, GL_FALSE
);
427 cc
= bo
->virtual + brw
->cc
.state_offset
;
428 cc_off
= bo
->offset
+ brw
->cc
.state_offset
;
430 state_out(name
, cc
, cc_off
, 0, "alpha test format %s, round disable %d, stencil ref %d,"
431 "bf stencil ref %d\n",
432 cc
->cc0
.alpha_test_format
? "FLOAT32" : "UNORM8",
433 cc
->cc0
.round_disable
,
435 cc
->cc0
.bf_stencil_ref
);
436 state_out(name
, cc
, cc_off
, 1, "\n");
437 state_out(name
, cc
, cc_off
, 2, "constant red %f\n", cc
->constant_r
);
438 state_out(name
, cc
, cc_off
, 3, "constant green %f\n", cc
->constant_g
);
439 state_out(name
, cc
, cc_off
, 4, "constant blue %f\n", cc
->constant_b
);
440 state_out(name
, cc
, cc_off
, 5, "constant alpha %f\n", cc
->constant_a
);
442 drm_intel_bo_unmap(bo
);
446 static void dump_blend_state(struct brw_context
*brw
)
448 struct intel_context
*intel
= &brw
->intel
;
449 const char *name
= "BLEND";
450 struct gen6_blend_state
*blend
;
453 drm_intel_bo_map(intel
->batch
.bo
, GL_FALSE
);
455 blend
= intel
->batch
.bo
->virtual + brw
->cc
.blend_state_offset
;
456 blend_off
= intel
->batch
.bo
->offset
+ brw
->cc
.blend_state_offset
;
458 state_out(name
, blend
, blend_off
, 0, "\n");
459 state_out(name
, blend
, blend_off
, 1, "\n");
461 drm_intel_bo_unmap(intel
->batch
.bo
);
465 static void brw_debug_prog(struct brw_context
*brw
,
466 const char *name
, uint32_t prog_offset
)
471 drm_intel_bo_map(brw
->cache
.bo
, false);
473 data
= brw
->cache
.bo
->virtual + prog_offset
;
475 for (i
= 0; i
< brw
->cache
.bo
->size
/ 4 / 4; i
++) {
476 fprintf(stderr
, "%8s: 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
477 name
, (unsigned int)brw
->cache
.bo
->offset
+ i
* 4 * 4,
478 data
[i
* 4], data
[i
* 4 + 1], data
[i
* 4 + 2], data
[i
* 4 + 3]);
479 /* Stop at the end of the program. It'd be nice to keep track of the actual
480 * intended program size instead of guessing like this.
482 if (data
[i
* 4 + 0] == 0 &&
483 data
[i
* 4 + 1] == 0 &&
484 data
[i
* 4 + 2] == 0 &&
485 data
[i
* 4 + 3] == 0)
489 drm_intel_bo_unmap(brw
->cache
.bo
);
493 dump_state_batch(struct brw_context
*brw
)
495 struct intel_context
*intel
= &brw
->intel
;
498 for (i
= 0; i
< brw
->state_batch_count
; i
++) {
499 uint32_t offset
= brw
->state_batch_list
[i
].offset
;
501 switch (brw
->state_batch_list
[i
].type
) {
502 case AUB_TRACE_CLIP_VP_STATE
:
503 dump_clip_viewport_state(brw
, offset
);
505 case AUB_TRACE_SF_VP_STATE
:
506 if (intel
->gen
>= 7) {
507 dump_sf_clip_viewport_state(brw
, offset
);
509 dump_sf_viewport_state(brw
, offset
);
519 * Print additional debug information associated with the batchbuffer
520 * when DEBUG_BATCH is set.
522 * For 965, this means mapping the state buffers that would have been referenced
523 * by the batchbuffer and dumping them.
525 * The buffer offsets printed rely on the buffer containing the last offset
526 * it was validated at.
528 void brw_debug_batch(struct intel_context
*intel
)
530 struct brw_context
*brw
= brw_context(&intel
->ctx
);
532 state_struct_out("WM bind",
534 brw
->wm
.bind_bo_offset
,
535 4 * brw
->wm
.nr_surfaces
);
536 if (intel
->gen
< 7) {
537 dump_wm_surface_state(brw
);
538 dump_wm_sampler_state(brw
);
540 dump_gen7_surface_state(brw
);
541 dump_gen7_sampler_state(brw
);
545 state_struct_out("VS", intel
->batch
.bo
, brw
->vs
.state_offset
,
546 sizeof(struct brw_vs_unit_state
));
547 brw_debug_prog(brw
, "VS prog", brw
->vs
.prog_offset
);
550 state_struct_out("GS", intel
->batch
.bo
, brw
->gs
.state_offset
,
551 sizeof(struct brw_gs_unit_state
));
552 if (brw
->gs
.prog_active
) {
553 brw_debug_prog(brw
, "GS prog", brw
->gs
.prog_offset
);
556 if (intel
->gen
< 6) {
557 state_struct_out("SF", intel
->batch
.bo
, brw
->sf
.state_offset
,
558 sizeof(struct brw_sf_unit_state
));
559 brw_debug_prog(brw
, "SF prog", brw
->sf
.prog_offset
);
563 state_struct_out("WM", intel
->batch
.bo
, brw
->wm
.state_offset
,
564 sizeof(struct brw_wm_unit_state
));
565 brw_debug_prog(brw
, "WM prog", brw
->wm
.prog_offset
);
567 if (intel
->gen
>= 6) {
568 dump_cc_viewport_state(brw
);
569 dump_depth_stencil_state(brw
);
571 dump_blend_state(brw
);
574 dump_state_batch(brw
);