i965/vec4: Make with_writemask() non-static.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_dump.c
1 /*
2 * Copyright © 2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "main/mtypes.h"
29 #include "intel_batchbuffer.h"
30
31 #include "brw_context.h"
32 #include "brw_defines.h"
33
34 static void
35 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
36 int index, char *fmt, ...) PRINTFLIKE(5, 6);
37
38 static void
39 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
40 int index, char *fmt, ...)
41 {
42 uint32_t *data = brw->batch.bo->virtual + offset;
43 va_list va;
44
45 fprintf(stderr, "0x%08x: 0x%08x: %8s: ",
46 offset + index * 4, data[index], name);
47 va_start(va, fmt);
48 vfprintf(stderr, fmt, va);
49 va_end(va);
50 }
51
52 static const char *
53 get_965_surfacetype(unsigned int surfacetype)
54 {
55 switch (surfacetype) {
56 case 0: return "1D";
57 case 1: return "2D";
58 case 2: return "3D";
59 case 3: return "CUBE";
60 case 4: return "BUFFER";
61 case 7: return "NULL";
62 default: return "unknown";
63 }
64 }
65
66 static const char *
67 get_965_surface_format(unsigned int surface_format)
68 {
69 switch (surface_format) {
70 case 0x000: return "r32g32b32a32_float";
71 case 0x0c1: return "b8g8r8a8_unorm";
72 case 0x100: return "b5g6r5_unorm";
73 case 0x102: return "b5g5r5a1_unorm";
74 case 0x104: return "b4g4r4a4_unorm";
75 default: return "unknown";
76 }
77 }
78
79 static void dump_vs_state(struct brw_context *brw, uint32_t offset)
80 {
81 const char *name = "VS_STATE";
82 struct brw_vs_unit_state *vs = brw->batch.bo->virtual + offset;
83
84 batch_out(brw, name, offset, 0, "thread0\n");
85 batch_out(brw, name, offset, 1, "thread1\n");
86 batch_out(brw, name, offset, 2, "thread2\n");
87 batch_out(brw, name, offset, 3, "thread3\n");
88 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
89 vs->thread4.max_threads + 1);
90 batch_out(brw, name, offset, 5, "vs5\n");
91 batch_out(brw, name, offset, 6, "vs6\n");
92 }
93
94 static void dump_gs_state(struct brw_context *brw, uint32_t offset)
95 {
96 const char *name = "GS_STATE";
97 struct brw_gs_unit_state *gs = brw->batch.bo->virtual + offset;
98
99 batch_out(brw, name, offset, 0, "thread0\n");
100 batch_out(brw, name, offset, 1, "thread1\n");
101 batch_out(brw, name, offset, 2, "thread2\n");
102 batch_out(brw, name, offset, 3, "thread3\n");
103 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
104 gs->thread4.max_threads + 1);
105 batch_out(brw, name, offset, 5, "vs5\n");
106 batch_out(brw, name, offset, 6, "vs6\n");
107 }
108
109 static void dump_clip_state(struct brw_context *brw, uint32_t offset)
110 {
111 const char *name = "CLIP_STATE";
112 struct brw_clip_unit_state *clip = brw->batch.bo->virtual + offset;
113
114 batch_out(brw, name, offset, 0, "thread0\n");
115 batch_out(brw, name, offset, 1, "thread1\n");
116 batch_out(brw, name, offset, 2, "thread2\n");
117 batch_out(brw, name, offset, 3, "thread3\n");
118 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
119 clip->thread4.max_threads + 1);
120 batch_out(brw, name, offset, 5, "clip5\n");
121 batch_out(brw, name, offset, 6, "clip6\n");
122 batch_out(brw, name, offset, 7, "vp xmin %f\n", clip->viewport_xmin);
123 batch_out(brw, name, offset, 8, "vp xmax %f\n", clip->viewport_xmax);
124 batch_out(brw, name, offset, 9, "vp ymin %f\n", clip->viewport_ymin);
125 batch_out(brw, name, offset, 10, "vp ymax %f\n", clip->viewport_ymax);
126 }
127
128 static void dump_sf_state(struct brw_context *brw, uint32_t offset)
129 {
130 const char *name = "SF_STATE";
131 struct brw_sf_unit_state *sf = brw->batch.bo->virtual + offset;
132
133 batch_out(brw, name, offset, 0, "thread0\n");
134 batch_out(brw, name, offset, 1, "thread1\n");
135 batch_out(brw, name, offset, 2, "thread2\n");
136 batch_out(brw, name, offset, 3, "thread3\n");
137 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
138 sf->thread4.max_threads + 1);
139 batch_out(brw, name, offset, 5, "sf5: viewport offset\n");
140 batch_out(brw, name, offset, 6, "sf6\n");
141 batch_out(brw, name, offset, 7, "sf7\n");
142 }
143
144 static void dump_wm_state(struct brw_context *brw, uint32_t offset)
145 {
146 const char *name = "WM_STATE";
147 struct brw_wm_unit_state *wm = brw->batch.bo->virtual + offset;
148
149 batch_out(brw, name, offset, 0, "thread0\n");
150 batch_out(brw, name, offset, 1, "thread1\n");
151 batch_out(brw, name, offset, 2, "thread2\n");
152 batch_out(brw, name, offset, 3, "thread3\n");
153 batch_out(brw, name, offset, 4, "wm4\n");
154 batch_out(brw, name, offset, 5, "wm5: %s%s%s%s%s%s, %d threads\n",
155 wm->wm5.enable_8_pix ? "8pix" : "",
156 wm->wm5.enable_16_pix ? "16pix" : "",
157 wm->wm5.program_uses_depth ? ", uses depth" : "",
158 wm->wm5.program_computes_depth ? ", computes depth" : "",
159 wm->wm5.program_uses_killpixel ? ", kills" : "",
160 wm->wm5.thread_dispatch_enable ? "" : ", no dispatch",
161 wm->wm5.max_threads + 1);
162 batch_out(brw, name, offset, 6, "depth offset constant %f\n",
163 wm->global_depth_offset_constant);
164 batch_out(brw, name, offset, 7, "depth offset scale %f\n",
165 wm->global_depth_offset_scale);
166 batch_out(brw, name, offset, 8, "wm8: kernel 1 (gen5+)\n");
167 batch_out(brw, name, offset, 9, "wm9: kernel 2 (gen5+)\n");
168 batch_out(brw, name, offset, 10, "wm10: kernel 3 (gen5+)\n");
169 }
170
171 static void dump_surface_state(struct brw_context *brw, uint32_t offset)
172 {
173 const char *name = "SURF";
174 uint32_t *surf = brw->batch.bo->virtual + offset;
175
176 batch_out(brw, name, offset, 0, "%s %s\n",
177 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
178 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)));
179 batch_out(brw, name, offset, 1, "offset\n");
180 batch_out(brw, name, offset, 2, "%dx%d size, %d mips\n",
181 GET_FIELD(surf[2], BRW_SURFACE_WIDTH) + 1,
182 GET_FIELD(surf[2], BRW_SURFACE_HEIGHT) + 1,
183 GET_FIELD(surf[2], BRW_SURFACE_LOD));
184 batch_out(brw, name, offset, 3, "pitch %d, %s tiled\n",
185 GET_FIELD(surf[3], BRW_SURFACE_PITCH) + 1,
186 (surf[3] & BRW_SURFACE_TILED) ?
187 ((surf[3] & BRW_SURFACE_TILED_Y) ? "Y" : "X") : "not");
188 batch_out(brw, name, offset, 4, "mip base %d\n",
189 GET_FIELD(surf[4], BRW_SURFACE_MIN_LOD));
190 batch_out(brw, name, offset, 5, "x,y offset: %d,%d\n",
191 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
192 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
193 }
194
195 static void dump_gen7_surface_state(struct brw_context *brw, uint32_t offset)
196 {
197 const char *name = "SURF";
198 uint32_t *surf = brw->batch.bo->virtual + offset;
199
200 batch_out(brw, name, offset, 0, "%s %s\n",
201 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
202 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)));
203 batch_out(brw, name, offset, 1, "offset\n");
204 batch_out(brw, name, offset, 2, "%dx%d size, %d mips\n",
205 GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1,
206 GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1,
207 surf[5] & INTEL_MASK(3, 0));
208 batch_out(brw, name, offset, 3, "pitch %d, %stiled\n",
209 (surf[3] & INTEL_MASK(17, 0)) + 1,
210 (surf[0] & (1 << 14)) ? "" : "not ");
211 batch_out(brw, name, offset, 4, "mip base %d\n",
212 GET_FIELD(surf[5], GEN7_SURFACE_MIN_LOD));
213 batch_out(brw, name, offset, 5, "x,y offset: %d,%d\n",
214 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
215 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
216 }
217
218 static void
219 dump_sdc(struct brw_context *brw, uint32_t offset)
220 {
221 const char *name = "SDC";
222
223 if (brw->gen >= 5 && brw->gen <= 6) {
224 struct gen5_sampler_default_color *sdc = (brw->batch.bo->virtual +
225 offset);
226 batch_out(brw, name, offset, 0, "unorm rgba\n");
227 batch_out(brw, name, offset, 1, "r %f\n", sdc->f[0]);
228 batch_out(brw, name, offset, 2, "b %f\n", sdc->f[1]);
229 batch_out(brw, name, offset, 3, "g %f\n", sdc->f[2]);
230 batch_out(brw, name, offset, 4, "a %f\n", sdc->f[3]);
231 batch_out(brw, name, offset, 5, "half float rg\n");
232 batch_out(brw, name, offset, 6, "half float ba\n");
233 batch_out(brw, name, offset, 7, "u16 rg\n");
234 batch_out(brw, name, offset, 8, "u16 ba\n");
235 batch_out(brw, name, offset, 9, "s16 rg\n");
236 batch_out(brw, name, offset, 10, "s16 ba\n");
237 batch_out(brw, name, offset, 11, "s8 rgba\n");
238 } else {
239 struct brw_sampler_default_color *sdc = (brw->batch.bo->virtual +
240 offset);
241 batch_out(brw, name, offset, 0, "r %f\n", sdc->color[0]);
242 batch_out(brw, name, offset, 1, "g %f\n", sdc->color[1]);
243 batch_out(brw, name, offset, 2, "b %f\n", sdc->color[2]);
244 batch_out(brw, name, offset, 3, "a %f\n", sdc->color[3]);
245 }
246 }
247
248 static void dump_sampler_state(struct brw_context *brw,
249 uint32_t offset, uint32_t size)
250 {
251 int i;
252 struct brw_sampler_state *samp = brw->batch.bo->virtual + offset;
253
254 assert(brw->gen < 7);
255
256 for (i = 0; i < size / sizeof(*samp); i++) {
257 char name[20];
258
259 sprintf(name, "WM SAMP%d", i);
260 batch_out(brw, name, offset, 0, "filtering\n");
261 batch_out(brw, name, offset, 1, "wrapping, lod\n");
262 batch_out(brw, name, offset, 2, "default color pointer\n");
263 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
264
265 samp++;
266 offset += sizeof(*samp);
267 }
268 }
269
270 static void dump_gen7_sampler_state(struct brw_context *brw,
271 uint32_t offset, uint32_t size)
272 {
273 struct gen7_sampler_state *samp = brw->batch.bo->virtual + offset;
274 int i;
275
276 assert(brw->gen >= 7);
277
278 for (i = 0; i < size / sizeof(*samp); i++) {
279 char name[20];
280
281 sprintf(name, "WM SAMP%d", i);
282 batch_out(brw, name, offset, 0, "filtering\n");
283 batch_out(brw, name, offset, 1, "wrapping, lod\n");
284 batch_out(brw, name, offset, 2, "default color pointer\n");
285 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
286
287 samp++;
288 offset += sizeof(*samp);
289 }
290 }
291
292
293 static void dump_sf_viewport_state(struct brw_context *brw,
294 uint32_t offset)
295 {
296 const char *name = "SF VP";
297 struct brw_sf_viewport *vp = brw->batch.bo->virtual + offset;
298
299 assert(brw->gen < 7);
300
301 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
302 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
303 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
304 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
305 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
306 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
307
308 batch_out(brw, name, offset, 6, "top left = %d,%d\n",
309 vp->scissor.xmin, vp->scissor.ymin);
310 batch_out(brw, name, offset, 7, "bottom right = %d,%d\n",
311 vp->scissor.xmax, vp->scissor.ymax);
312 }
313
314 static void dump_clip_viewport_state(struct brw_context *brw,
315 uint32_t offset)
316 {
317 const char *name = "CLIP VP";
318 struct brw_clipper_viewport *vp = brw->batch.bo->virtual + offset;
319
320 assert(brw->gen < 7);
321
322 batch_out(brw, name, offset, 0, "xmin = %f\n", vp->xmin);
323 batch_out(brw, name, offset, 1, "xmax = %f\n", vp->xmax);
324 batch_out(brw, name, offset, 2, "ymin = %f\n", vp->ymin);
325 batch_out(brw, name, offset, 3, "ymax = %f\n", vp->ymax);
326 }
327
328 static void dump_sf_clip_viewport_state(struct brw_context *brw,
329 uint32_t offset)
330 {
331 const char *name = "SF_CLIP VP";
332 struct gen7_sf_clip_viewport *vp = brw->batch.bo->virtual + offset;
333
334 assert(brw->gen >= 7);
335
336 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
337 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
338 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
339 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
340 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
341 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
342 batch_out(brw, name, offset, 6, "guardband xmin = %f\n", vp->guardband.xmin);
343 batch_out(brw, name, offset, 7, "guardband xmax = %f\n", vp->guardband.xmax);
344 batch_out(brw, name, offset, 8, "guardband ymin = %f\n", vp->guardband.ymin);
345 batch_out(brw, name, offset, 9, "guardband ymax = %f\n", vp->guardband.ymax);
346 }
347
348
349 static void dump_cc_viewport_state(struct brw_context *brw, uint32_t offset)
350 {
351 const char *name = "CC VP";
352 struct brw_cc_viewport *vp = brw->batch.bo->virtual + offset;
353
354 batch_out(brw, name, offset, 0, "min_depth = %f\n", vp->min_depth);
355 batch_out(brw, name, offset, 1, "max_depth = %f\n", vp->max_depth);
356 }
357
358 static void dump_depth_stencil_state(struct brw_context *brw, uint32_t offset)
359 {
360 const char *name = "D_S";
361 struct gen6_depth_stencil_state *ds = brw->batch.bo->virtual + offset;
362
363 batch_out(brw, name, offset, 0,
364 "stencil %sable, func %d, write %sable\n",
365 ds->ds0.stencil_enable ? "en" : "dis",
366 ds->ds0.stencil_func,
367 ds->ds0.stencil_write_enable ? "en" : "dis");
368 batch_out(brw, name, offset, 1,
369 "stencil test mask 0x%x, write mask 0x%x\n",
370 ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
371 batch_out(brw, name, offset, 2,
372 "depth test %sable, func %d, write %sable\n",
373 ds->ds2.depth_test_enable ? "en" : "dis",
374 ds->ds2.depth_test_func,
375 ds->ds2.depth_write_enable ? "en" : "dis");
376 }
377
378 static void dump_cc_state_gen4(struct brw_context *brw, uint32_t offset)
379 {
380 const char *name = "CC";
381
382 batch_out(brw, name, offset, 0, "cc0\n");
383 batch_out(brw, name, offset, 1, "cc1\n");
384 batch_out(brw, name, offset, 2, "cc2\n");
385 batch_out(brw, name, offset, 3, "cc3\n");
386 batch_out(brw, name, offset, 4, "cc4: viewport offset\n");
387 batch_out(brw, name, offset, 5, "cc5\n");
388 batch_out(brw, name, offset, 6, "cc6\n");
389 batch_out(brw, name, offset, 7, "cc7\n");
390 }
391
392 static void dump_cc_state_gen6(struct brw_context *brw, uint32_t offset)
393 {
394 const char *name = "CC";
395 struct gen6_color_calc_state *cc = brw->batch.bo->virtual + offset;
396
397 batch_out(brw, name, offset, 0,
398 "alpha test format %s, round disable %d, stencil ref %d, "
399 "bf stencil ref %d\n",
400 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
401 cc->cc0.round_disable,
402 cc->cc0.stencil_ref,
403 cc->cc0.bf_stencil_ref);
404 batch_out(brw, name, offset, 1, "\n");
405 batch_out(brw, name, offset, 2, "constant red %f\n", cc->constant_r);
406 batch_out(brw, name, offset, 3, "constant green %f\n", cc->constant_g);
407 batch_out(brw, name, offset, 4, "constant blue %f\n", cc->constant_b);
408 batch_out(brw, name, offset, 5, "constant alpha %f\n", cc->constant_a);
409 }
410
411 static void dump_blend_state(struct brw_context *brw, uint32_t offset)
412 {
413 const char *name = "BLEND";
414
415 batch_out(brw, name, offset, 0, "\n");
416 batch_out(brw, name, offset, 1, "\n");
417 }
418
419 static void
420 dump_scissor(struct brw_context *brw, uint32_t offset)
421 {
422 const char *name = "SCISSOR";
423 struct gen6_scissor_rect *scissor = brw->batch.bo->virtual + offset;
424
425 batch_out(brw, name, offset, 0, "xmin %d, ymin %d\n",
426 scissor->xmin, scissor->ymin);
427 batch_out(brw, name, offset, 1, "xmax %d, ymax %d\n",
428 scissor->xmax, scissor->ymax);
429 }
430
431 static void
432 dump_vs_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
433 {
434 const char *name = "VS_CONST";
435 uint32_t *as_uint = brw->batch.bo->virtual + offset;
436 float *as_float = brw->batch.bo->virtual + offset;
437 int i;
438
439 for (i = 0; i < size / 4; i += 4) {
440 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
441 i / 4,
442 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
443 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
444 }
445 }
446
447 static void
448 dump_wm_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
449 {
450 const char *name = "WM_CONST";
451 uint32_t *as_uint = brw->batch.bo->virtual + offset;
452 float *as_float = brw->batch.bo->virtual + offset;
453 int i;
454
455 for (i = 0; i < size / 4; i += 4) {
456 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
457 i / 4,
458 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
459 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
460 }
461 }
462
463 static void dump_binding_table(struct brw_context *brw, uint32_t offset,
464 uint32_t size)
465 {
466 char name[20];
467 int i;
468 uint32_t *data = brw->batch.bo->virtual + offset;
469
470 for (i = 0; i < size / 4; i++) {
471 if (data[i] == 0)
472 continue;
473
474 sprintf(name, "BIND%d", i);
475 batch_out(brw, name, offset, i, "surface state address\n");
476 }
477 }
478
479 static void
480 dump_prog_cache(struct brw_context *brw)
481 {
482 struct brw_cache *cache = &brw->cache;
483 unsigned int b, i;
484 uint32_t *data;
485
486 drm_intel_bo_map(brw->cache.bo, false);
487
488 for (b = 0; b < cache->size; b++) {
489 struct brw_cache_item *item;
490
491 for (item = cache->items[b]; item; item = item->next) {
492 const char *name;
493 uint32_t offset = item->offset;
494
495 data = brw->cache.bo->virtual + item->offset;
496
497 switch (item->cache_id) {
498 case BRW_VS_PROG:
499 name = "VS kernel";
500 break;
501 case BRW_FF_GS_PROG:
502 name = "Fixed-function GS kernel";
503 break;
504 case BRW_GS_PROG:
505 name = "GS kernel";
506 break;
507 case BRW_CLIP_PROG:
508 name = "CLIP kernel";
509 break;
510 case BRW_SF_PROG:
511 name = "SF kernel";
512 break;
513 case BRW_WM_PROG:
514 name = "WM kernel";
515 break;
516 default:
517 name = "unknown";
518 break;
519 }
520
521 for (i = 0; i < item->size / 4 / 4; i++) {
522 fprintf(stderr, "0x%08x: %8s: 0x%08x 0x%08x 0x%08x 0x%08x ",
523 offset + i * 4 * 4,
524 name,
525 data[i * 4], data[i * 4 + 1], data[i * 4 + 2], data[i * 4 + 3]);
526
527 brw_disasm(stderr, (void *)(data + i * 4), brw->gen);
528 }
529 }
530 }
531
532 drm_intel_bo_unmap(brw->cache.bo);
533 }
534
535 static void
536 dump_state_batch(struct brw_context *brw)
537 {
538 int i;
539
540 for (i = 0; i < brw->state_batch_count; i++) {
541 uint32_t offset = brw->state_batch_list[i].offset;
542 uint32_t size = brw->state_batch_list[i].size;
543
544 switch (brw->state_batch_list[i].type) {
545 case AUB_TRACE_VS_STATE:
546 dump_vs_state(brw, offset);
547 break;
548 case AUB_TRACE_GS_STATE:
549 dump_gs_state(brw, offset);
550 break;
551 case AUB_TRACE_CLIP_STATE:
552 dump_clip_state(brw, offset);
553 break;
554 case AUB_TRACE_SF_STATE:
555 dump_sf_state(brw, offset);
556 break;
557 case AUB_TRACE_WM_STATE:
558 dump_wm_state(brw, offset);
559 break;
560 case AUB_TRACE_CLIP_VP_STATE:
561 dump_clip_viewport_state(brw, offset);
562 break;
563 case AUB_TRACE_SF_VP_STATE:
564 if (brw->gen >= 7) {
565 dump_sf_clip_viewport_state(brw, offset);
566 } else {
567 dump_sf_viewport_state(brw, offset);
568 }
569 break;
570 case AUB_TRACE_CC_VP_STATE:
571 dump_cc_viewport_state(brw, offset);
572 break;
573 case AUB_TRACE_DEPTH_STENCIL_STATE:
574 dump_depth_stencil_state(brw, offset);
575 break;
576 case AUB_TRACE_CC_STATE:
577 if (brw->gen >= 6)
578 dump_cc_state_gen6(brw, offset);
579 else
580 dump_cc_state_gen4(brw, offset);
581 break;
582 case AUB_TRACE_BLEND_STATE:
583 dump_blend_state(brw, offset);
584 break;
585 case AUB_TRACE_BINDING_TABLE:
586 dump_binding_table(brw, offset, size);
587 break;
588 case AUB_TRACE_SURFACE_STATE:
589 if (brw->gen < 7) {
590 dump_surface_state(brw, offset);
591 } else {
592 dump_gen7_surface_state(brw, offset);
593 }
594 break;
595 case AUB_TRACE_SAMPLER_STATE:
596 if (brw->gen < 7) {
597 dump_sampler_state(brw, offset, size);
598 } else {
599 dump_gen7_sampler_state(brw, offset, size);
600 }
601 break;
602 case AUB_TRACE_SAMPLER_DEFAULT_COLOR:
603 dump_sdc(brw, offset);
604 break;
605 case AUB_TRACE_SCISSOR_STATE:
606 dump_scissor(brw, offset);
607 break;
608 case AUB_TRACE_VS_CONSTANTS:
609 dump_vs_constants(brw, offset, size);
610 break;
611 case AUB_TRACE_WM_CONSTANTS:
612 dump_wm_constants(brw, offset, size);
613 break;
614 default:
615 break;
616 }
617 }
618 }
619
620 /**
621 * Print additional debug information associated with the batchbuffer
622 * when DEBUG_BATCH is set.
623 *
624 * For 965, this means mapping the state buffers that would have been referenced
625 * by the batchbuffer and dumping them.
626 *
627 * The buffer offsets printed rely on the buffer containing the last offset
628 * it was validated at.
629 */
630 void brw_debug_batch(struct brw_context *brw)
631 {
632 drm_intel_bo_map(brw->batch.bo, false);
633 dump_state_batch(brw);
634 drm_intel_bo_unmap(brw->batch.bo);
635
636 if (0)
637 dump_prog_cache(brw);
638 }