i965/disasm: Disassemble the compaction control bit.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_dump.c
1 /*
2 * Copyright © 2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "main/mtypes.h"
29 #include "intel_batchbuffer.h"
30
31 #include "brw_context.h"
32 #include "brw_defines.h"
33
34 static void
35 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
36 int index, char *fmt, ...) PRINTFLIKE(5, 6);
37
38 static void
39 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
40 int index, char *fmt, ...)
41 {
42 uint32_t *data = brw->batch.bo->virtual + offset;
43 va_list va;
44
45 fprintf(stderr, "0x%08x: 0x%08x: %8s: ",
46 offset + index * 4, data[index], name);
47 va_start(va, fmt);
48 vfprintf(stderr, fmt, va);
49 va_end(va);
50 }
51
52 static const char *
53 get_965_surfacetype(unsigned int surfacetype)
54 {
55 switch (surfacetype) {
56 case 0: return "1D";
57 case 1: return "2D";
58 case 2: return "3D";
59 case 3: return "CUBE";
60 case 4: return "BUFFER";
61 case 7: return "NULL";
62 default: return "unknown";
63 }
64 }
65
66 static const char *
67 get_965_surface_format(unsigned int surface_format)
68 {
69 switch (surface_format) {
70 case 0x000: return "r32g32b32a32_float";
71 case 0x0c1: return "b8g8r8a8_unorm";
72 case 0x100: return "b5g6r5_unorm";
73 case 0x102: return "b5g5r5a1_unorm";
74 case 0x104: return "b4g4r4a4_unorm";
75 default: return "unknown";
76 }
77 }
78
79 static void dump_vs_state(struct brw_context *brw, uint32_t offset)
80 {
81 const char *name = "VS_STATE";
82 struct brw_vs_unit_state *vs = brw->batch.bo->virtual + offset;
83
84 batch_out(brw, name, offset, 0, "thread0\n");
85 batch_out(brw, name, offset, 1, "thread1\n");
86 batch_out(brw, name, offset, 2, "thread2\n");
87 batch_out(brw, name, offset, 3, "thread3\n");
88 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
89 vs->thread4.max_threads + 1);
90 batch_out(brw, name, offset, 5, "vs5\n");
91 batch_out(brw, name, offset, 6, "vs6\n");
92 }
93
94 static void dump_gs_state(struct brw_context *brw, uint32_t offset)
95 {
96 const char *name = "GS_STATE";
97 struct brw_gs_unit_state *gs = brw->batch.bo->virtual + offset;
98
99 batch_out(brw, name, offset, 0, "thread0\n");
100 batch_out(brw, name, offset, 1, "thread1\n");
101 batch_out(brw, name, offset, 2, "thread2\n");
102 batch_out(brw, name, offset, 3, "thread3\n");
103 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
104 gs->thread4.max_threads + 1);
105 batch_out(brw, name, offset, 5, "vs5\n");
106 batch_out(brw, name, offset, 6, "vs6\n");
107 }
108
109 static void dump_clip_state(struct brw_context *brw, uint32_t offset)
110 {
111 const char *name = "CLIP_STATE";
112 struct brw_clip_unit_state *clip = brw->batch.bo->virtual + offset;
113
114 batch_out(brw, name, offset, 0, "thread0\n");
115 batch_out(brw, name, offset, 1, "thread1\n");
116 batch_out(brw, name, offset, 2, "thread2\n");
117 batch_out(brw, name, offset, 3, "thread3\n");
118 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
119 clip->thread4.max_threads + 1);
120 batch_out(brw, name, offset, 5, "clip5\n");
121 batch_out(brw, name, offset, 6, "clip6\n");
122 batch_out(brw, name, offset, 7, "vp xmin %f\n", clip->viewport_xmin);
123 batch_out(brw, name, offset, 8, "vp xmax %f\n", clip->viewport_xmax);
124 batch_out(brw, name, offset, 9, "vp ymin %f\n", clip->viewport_ymin);
125 batch_out(brw, name, offset, 10, "vp ymax %f\n", clip->viewport_ymax);
126 }
127
128 static void dump_sf_state(struct brw_context *brw, uint32_t offset)
129 {
130 const char *name = "SF_STATE";
131 struct brw_sf_unit_state *sf = brw->batch.bo->virtual + offset;
132
133 batch_out(brw, name, offset, 0, "thread0\n");
134 batch_out(brw, name, offset, 1, "thread1\n");
135 batch_out(brw, name, offset, 2, "thread2\n");
136 batch_out(brw, name, offset, 3, "thread3\n");
137 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
138 sf->thread4.max_threads + 1);
139 batch_out(brw, name, offset, 5, "sf5: viewport offset\n");
140 batch_out(brw, name, offset, 6, "sf6\n");
141 batch_out(brw, name, offset, 7, "sf7\n");
142 }
143
144 static void dump_wm_state(struct brw_context *brw, uint32_t offset)
145 {
146 const char *name = "WM_STATE";
147 struct brw_wm_unit_state *wm = brw->batch.bo->virtual + offset;
148
149 batch_out(brw, name, offset, 0, "thread0\n");
150 batch_out(brw, name, offset, 1, "thread1\n");
151 batch_out(brw, name, offset, 2, "thread2\n");
152 batch_out(brw, name, offset, 3, "thread3\n");
153 batch_out(brw, name, offset, 4, "wm4\n");
154 batch_out(brw, name, offset, 5, "wm5: %s%s%s%s%s%s, %d threads\n",
155 wm->wm5.enable_8_pix ? "8pix" : "",
156 wm->wm5.enable_16_pix ? "16pix" : "",
157 wm->wm5.program_uses_depth ? ", uses depth" : "",
158 wm->wm5.program_computes_depth ? ", computes depth" : "",
159 wm->wm5.program_uses_killpixel ? ", kills" : "",
160 wm->wm5.thread_dispatch_enable ? "" : ", no dispatch",
161 wm->wm5.max_threads + 1);
162 batch_out(brw, name, offset, 6, "depth offset constant %f\n",
163 wm->global_depth_offset_constant);
164 batch_out(brw, name, offset, 7, "depth offset scale %f\n",
165 wm->global_depth_offset_scale);
166 batch_out(brw, name, offset, 8, "wm8: kernel 1 (gen5+)\n");
167 batch_out(brw, name, offset, 9, "wm9: kernel 2 (gen5+)\n");
168 batch_out(brw, name, offset, 10, "wm10: kernel 3 (gen5+)\n");
169 }
170
171 static void dump_surface_state(struct brw_context *brw, uint32_t offset)
172 {
173 const char *name = "SURF";
174 uint32_t *surf = brw->batch.bo->virtual + offset;
175
176 batch_out(brw, name, offset, 0, "%s %s\n",
177 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
178 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)));
179 batch_out(brw, name, offset, 1, "offset\n");
180 batch_out(brw, name, offset, 2, "%dx%d size, %d mips\n",
181 GET_FIELD(surf[2], BRW_SURFACE_WIDTH) + 1,
182 GET_FIELD(surf[2], BRW_SURFACE_HEIGHT) + 1,
183 GET_FIELD(surf[2], BRW_SURFACE_LOD));
184 batch_out(brw, name, offset, 3, "pitch %d, %s tiled\n",
185 GET_FIELD(surf[3], BRW_SURFACE_PITCH) + 1,
186 (surf[3] & BRW_SURFACE_TILED) ?
187 ((surf[3] & BRW_SURFACE_TILED_Y) ? "Y" : "X") : "not");
188 batch_out(brw, name, offset, 4, "mip base %d\n",
189 GET_FIELD(surf[4], BRW_SURFACE_MIN_LOD));
190 batch_out(brw, name, offset, 5, "x,y offset: %d,%d\n",
191 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
192 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
193 }
194
195 static void dump_gen7_surface_state(struct brw_context *brw, uint32_t offset)
196 {
197 const char *name = "SURF";
198 uint32_t *surf = brw->batch.bo->virtual + offset;
199
200 batch_out(brw, name, offset, 0, "%s %s %s\n",
201 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
202 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)),
203 (surf[0] & GEN7_SURFACE_IS_ARRAY) ? "array" : "");
204 batch_out(brw, name, offset, 1, "offset\n");
205 batch_out(brw, name, offset, 2, "%dx%d size, %d mips, %d slices\n",
206 GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1,
207 GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1,
208 surf[5] & INTEL_MASK(3, 0),
209 GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1);
210 batch_out(brw, name, offset, 3, "pitch %d, %stiled\n",
211 (surf[3] & INTEL_MASK(17, 0)) + 1,
212 (surf[0] & (1 << 14)) ? "" : "not ");
213 batch_out(brw, name, offset, 4, "min array element %d, array extent %d\n",
214 GET_FIELD(surf[4], GEN7_SURFACE_MIN_ARRAY_ELEMENT),
215 GET_FIELD(surf[4], GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT) + 1);
216 batch_out(brw, name, offset, 5, "mip base %d\n",
217 GET_FIELD(surf[5], GEN7_SURFACE_MIN_LOD));
218 batch_out(brw, name, offset, 6, "x,y offset: %d,%d\n",
219 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
220 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
221 batch_out(brw, name, offset, 7, "\n");
222 }
223
224 static void
225 dump_sdc(struct brw_context *brw, uint32_t offset)
226 {
227 const char *name = "SDC";
228
229 if (brw->gen >= 5 && brw->gen <= 6) {
230 struct gen5_sampler_default_color *sdc = (brw->batch.bo->virtual +
231 offset);
232 batch_out(brw, name, offset, 0, "unorm rgba\n");
233 batch_out(brw, name, offset, 1, "r %f\n", sdc->f[0]);
234 batch_out(brw, name, offset, 2, "b %f\n", sdc->f[1]);
235 batch_out(brw, name, offset, 3, "g %f\n", sdc->f[2]);
236 batch_out(brw, name, offset, 4, "a %f\n", sdc->f[3]);
237 batch_out(brw, name, offset, 5, "half float rg\n");
238 batch_out(brw, name, offset, 6, "half float ba\n");
239 batch_out(brw, name, offset, 7, "u16 rg\n");
240 batch_out(brw, name, offset, 8, "u16 ba\n");
241 batch_out(brw, name, offset, 9, "s16 rg\n");
242 batch_out(brw, name, offset, 10, "s16 ba\n");
243 batch_out(brw, name, offset, 11, "s8 rgba\n");
244 } else {
245 struct brw_sampler_default_color *sdc = (brw->batch.bo->virtual +
246 offset);
247 batch_out(brw, name, offset, 0, "r %f\n", sdc->color[0]);
248 batch_out(brw, name, offset, 1, "g %f\n", sdc->color[1]);
249 batch_out(brw, name, offset, 2, "b %f\n", sdc->color[2]);
250 batch_out(brw, name, offset, 3, "a %f\n", sdc->color[3]);
251 }
252 }
253
254 static void dump_sampler_state(struct brw_context *brw,
255 uint32_t offset, uint32_t size)
256 {
257 int i;
258 struct brw_sampler_state *samp = brw->batch.bo->virtual + offset;
259
260 assert(brw->gen < 7);
261
262 for (i = 0; i < size / sizeof(*samp); i++) {
263 char name[20];
264
265 sprintf(name, "WM SAMP%d", i);
266 batch_out(brw, name, offset, 0, "filtering\n");
267 batch_out(brw, name, offset, 1, "wrapping, lod\n");
268 batch_out(brw, name, offset, 2, "default color pointer\n");
269 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
270
271 samp++;
272 offset += sizeof(*samp);
273 }
274 }
275
276 static void dump_gen7_sampler_state(struct brw_context *brw,
277 uint32_t offset, uint32_t size)
278 {
279 struct gen7_sampler_state *samp = brw->batch.bo->virtual + offset;
280 int i;
281
282 assert(brw->gen >= 7);
283
284 for (i = 0; i < size / sizeof(*samp); i++) {
285 char name[20];
286
287 sprintf(name, "WM SAMP%d", i);
288 batch_out(brw, name, offset, 0, "filtering\n");
289 batch_out(brw, name, offset, 1, "wrapping, lod\n");
290 batch_out(brw, name, offset, 2, "default color pointer\n");
291 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
292
293 samp++;
294 offset += sizeof(*samp);
295 }
296 }
297
298
299 static void dump_sf_viewport_state(struct brw_context *brw,
300 uint32_t offset)
301 {
302 const char *name = "SF VP";
303 struct brw_sf_viewport *vp = brw->batch.bo->virtual + offset;
304
305 assert(brw->gen < 7);
306
307 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
308 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
309 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
310 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
311 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
312 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
313
314 batch_out(brw, name, offset, 6, "top left = %d,%d\n",
315 vp->scissor.xmin, vp->scissor.ymin);
316 batch_out(brw, name, offset, 7, "bottom right = %d,%d\n",
317 vp->scissor.xmax, vp->scissor.ymax);
318 }
319
320 static void dump_clip_viewport_state(struct brw_context *brw,
321 uint32_t offset)
322 {
323 const char *name = "CLIP VP";
324 struct brw_clipper_viewport *vp = brw->batch.bo->virtual + offset;
325
326 assert(brw->gen < 7);
327
328 batch_out(brw, name, offset, 0, "xmin = %f\n", vp->xmin);
329 batch_out(brw, name, offset, 1, "xmax = %f\n", vp->xmax);
330 batch_out(brw, name, offset, 2, "ymin = %f\n", vp->ymin);
331 batch_out(brw, name, offset, 3, "ymax = %f\n", vp->ymax);
332 }
333
334 static void dump_sf_clip_viewport_state(struct brw_context *brw,
335 uint32_t offset)
336 {
337 const char *name = "SF_CLIP VP";
338 struct gen7_sf_clip_viewport *vp = brw->batch.bo->virtual + offset;
339
340 assert(brw->gen >= 7);
341
342 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
343 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
344 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
345 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
346 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
347 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
348 batch_out(brw, name, offset, 6, "guardband xmin = %f\n", vp->guardband.xmin);
349 batch_out(brw, name, offset, 7, "guardband xmax = %f\n", vp->guardband.xmax);
350 batch_out(brw, name, offset, 8, "guardband ymin = %f\n", vp->guardband.ymin);
351 batch_out(brw, name, offset, 9, "guardband ymax = %f\n", vp->guardband.ymax);
352 }
353
354
355 static void dump_cc_viewport_state(struct brw_context *brw, uint32_t offset)
356 {
357 const char *name = "CC VP";
358 struct brw_cc_viewport *vp = brw->batch.bo->virtual + offset;
359
360 batch_out(brw, name, offset, 0, "min_depth = %f\n", vp->min_depth);
361 batch_out(brw, name, offset, 1, "max_depth = %f\n", vp->max_depth);
362 }
363
364 static void dump_depth_stencil_state(struct brw_context *brw, uint32_t offset)
365 {
366 const char *name = "D_S";
367 struct gen6_depth_stencil_state *ds = brw->batch.bo->virtual + offset;
368
369 batch_out(brw, name, offset, 0,
370 "stencil %sable, func %d, write %sable\n",
371 ds->ds0.stencil_enable ? "en" : "dis",
372 ds->ds0.stencil_func,
373 ds->ds0.stencil_write_enable ? "en" : "dis");
374 batch_out(brw, name, offset, 1,
375 "stencil test mask 0x%x, write mask 0x%x\n",
376 ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
377 batch_out(brw, name, offset, 2,
378 "depth test %sable, func %d, write %sable\n",
379 ds->ds2.depth_test_enable ? "en" : "dis",
380 ds->ds2.depth_test_func,
381 ds->ds2.depth_write_enable ? "en" : "dis");
382 }
383
384 static void dump_cc_state_gen4(struct brw_context *brw, uint32_t offset)
385 {
386 const char *name = "CC";
387
388 batch_out(brw, name, offset, 0, "cc0\n");
389 batch_out(brw, name, offset, 1, "cc1\n");
390 batch_out(brw, name, offset, 2, "cc2\n");
391 batch_out(brw, name, offset, 3, "cc3\n");
392 batch_out(brw, name, offset, 4, "cc4: viewport offset\n");
393 batch_out(brw, name, offset, 5, "cc5\n");
394 batch_out(brw, name, offset, 6, "cc6\n");
395 batch_out(brw, name, offset, 7, "cc7\n");
396 }
397
398 static void dump_cc_state_gen6(struct brw_context *brw, uint32_t offset)
399 {
400 const char *name = "CC";
401 struct gen6_color_calc_state *cc = brw->batch.bo->virtual + offset;
402
403 batch_out(brw, name, offset, 0,
404 "alpha test format %s, round disable %d, stencil ref %d, "
405 "bf stencil ref %d\n",
406 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
407 cc->cc0.round_disable,
408 cc->cc0.stencil_ref,
409 cc->cc0.bf_stencil_ref);
410 batch_out(brw, name, offset, 1, "\n");
411 batch_out(brw, name, offset, 2, "constant red %f\n", cc->constant_r);
412 batch_out(brw, name, offset, 3, "constant green %f\n", cc->constant_g);
413 batch_out(brw, name, offset, 4, "constant blue %f\n", cc->constant_b);
414 batch_out(brw, name, offset, 5, "constant alpha %f\n", cc->constant_a);
415 }
416
417 static void dump_blend_state(struct brw_context *brw, uint32_t offset)
418 {
419 const char *name = "BLEND";
420
421 batch_out(brw, name, offset, 0, "\n");
422 batch_out(brw, name, offset, 1, "\n");
423 }
424
425 static void
426 dump_scissor(struct brw_context *brw, uint32_t offset)
427 {
428 const char *name = "SCISSOR";
429 struct gen6_scissor_rect *scissor = brw->batch.bo->virtual + offset;
430
431 batch_out(brw, name, offset, 0, "xmin %d, ymin %d\n",
432 scissor->xmin, scissor->ymin);
433 batch_out(brw, name, offset, 1, "xmax %d, ymax %d\n",
434 scissor->xmax, scissor->ymax);
435 }
436
437 static void
438 dump_vs_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
439 {
440 const char *name = "VS_CONST";
441 uint32_t *as_uint = brw->batch.bo->virtual + offset;
442 float *as_float = brw->batch.bo->virtual + offset;
443 int i;
444
445 for (i = 0; i < size / 4; i += 4) {
446 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
447 i / 4,
448 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
449 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
450 }
451 }
452
453 static void
454 dump_wm_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
455 {
456 const char *name = "WM_CONST";
457 uint32_t *as_uint = brw->batch.bo->virtual + offset;
458 float *as_float = brw->batch.bo->virtual + offset;
459 int i;
460
461 for (i = 0; i < size / 4; i += 4) {
462 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
463 i / 4,
464 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
465 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
466 }
467 }
468
469 static void dump_binding_table(struct brw_context *brw, uint32_t offset,
470 uint32_t size)
471 {
472 char name[20];
473 int i;
474 uint32_t *data = brw->batch.bo->virtual + offset;
475
476 for (i = 0; i < size / 4; i++) {
477 if (data[i] == 0)
478 continue;
479
480 sprintf(name, "BIND%d", i);
481 batch_out(brw, name, offset, i, "surface state address\n");
482 }
483 }
484
485 static void
486 dump_prog_cache(struct brw_context *brw)
487 {
488 struct brw_cache *cache = &brw->cache;
489 unsigned int b, i;
490 uint32_t *data;
491
492 drm_intel_bo_map(brw->cache.bo, false);
493
494 for (b = 0; b < cache->size; b++) {
495 struct brw_cache_item *item;
496
497 for (item = cache->items[b]; item; item = item->next) {
498 const char *name;
499 uint32_t offset = item->offset;
500
501 data = brw->cache.bo->virtual + item->offset;
502
503 switch (item->cache_id) {
504 case BRW_VS_PROG:
505 name = "VS kernel";
506 break;
507 case BRW_FF_GS_PROG:
508 name = "Fixed-function GS kernel";
509 break;
510 case BRW_GS_PROG:
511 name = "GS kernel";
512 break;
513 case BRW_CLIP_PROG:
514 name = "CLIP kernel";
515 break;
516 case BRW_SF_PROG:
517 name = "SF kernel";
518 break;
519 case BRW_WM_PROG:
520 name = "WM kernel";
521 break;
522 default:
523 name = "unknown";
524 break;
525 }
526
527 for (i = 0; i < item->size / 4 / 4; i++) {
528 fprintf(stderr, "0x%08x: %8s: 0x%08x 0x%08x 0x%08x 0x%08x ",
529 offset + i * 4 * 4,
530 name,
531 data[i * 4], data[i * 4 + 1], data[i * 4 + 2], data[i * 4 + 3]);
532
533 brw_disasm(stderr, (void *)(data + i * 4), brw->gen, false);
534 }
535 }
536 }
537
538 drm_intel_bo_unmap(brw->cache.bo);
539 }
540
541 static void
542 dump_state_batch(struct brw_context *brw)
543 {
544 int i;
545
546 for (i = 0; i < brw->state_batch_count; i++) {
547 uint32_t offset = brw->state_batch_list[i].offset;
548 uint32_t size = brw->state_batch_list[i].size;
549
550 switch (brw->state_batch_list[i].type) {
551 case AUB_TRACE_VS_STATE:
552 dump_vs_state(brw, offset);
553 break;
554 case AUB_TRACE_GS_STATE:
555 dump_gs_state(brw, offset);
556 break;
557 case AUB_TRACE_CLIP_STATE:
558 dump_clip_state(brw, offset);
559 break;
560 case AUB_TRACE_SF_STATE:
561 dump_sf_state(brw, offset);
562 break;
563 case AUB_TRACE_WM_STATE:
564 dump_wm_state(brw, offset);
565 break;
566 case AUB_TRACE_CLIP_VP_STATE:
567 dump_clip_viewport_state(brw, offset);
568 break;
569 case AUB_TRACE_SF_VP_STATE:
570 if (brw->gen >= 7) {
571 dump_sf_clip_viewport_state(brw, offset);
572 } else {
573 dump_sf_viewport_state(brw, offset);
574 }
575 break;
576 case AUB_TRACE_CC_VP_STATE:
577 dump_cc_viewport_state(brw, offset);
578 break;
579 case AUB_TRACE_DEPTH_STENCIL_STATE:
580 dump_depth_stencil_state(brw, offset);
581 break;
582 case AUB_TRACE_CC_STATE:
583 if (brw->gen >= 6)
584 dump_cc_state_gen6(brw, offset);
585 else
586 dump_cc_state_gen4(brw, offset);
587 break;
588 case AUB_TRACE_BLEND_STATE:
589 dump_blend_state(brw, offset);
590 break;
591 case AUB_TRACE_BINDING_TABLE:
592 dump_binding_table(brw, offset, size);
593 break;
594 case AUB_TRACE_SURFACE_STATE:
595 if (brw->gen < 7) {
596 dump_surface_state(brw, offset);
597 } else {
598 dump_gen7_surface_state(brw, offset);
599 }
600 break;
601 case AUB_TRACE_SAMPLER_STATE:
602 if (brw->gen < 7) {
603 dump_sampler_state(brw, offset, size);
604 } else {
605 dump_gen7_sampler_state(brw, offset, size);
606 }
607 break;
608 case AUB_TRACE_SAMPLER_DEFAULT_COLOR:
609 dump_sdc(brw, offset);
610 break;
611 case AUB_TRACE_SCISSOR_STATE:
612 dump_scissor(brw, offset);
613 break;
614 case AUB_TRACE_VS_CONSTANTS:
615 dump_vs_constants(brw, offset, size);
616 break;
617 case AUB_TRACE_WM_CONSTANTS:
618 dump_wm_constants(brw, offset, size);
619 break;
620 default:
621 break;
622 }
623 }
624 }
625
626 /**
627 * Print additional debug information associated with the batchbuffer
628 * when DEBUG_BATCH is set.
629 *
630 * For 965, this means mapping the state buffers that would have been referenced
631 * by the batchbuffer and dumping them.
632 *
633 * The buffer offsets printed rely on the buffer containing the last offset
634 * it was validated at.
635 */
636 void brw_debug_batch(struct brw_context *brw)
637 {
638 drm_intel_bo_map(brw->batch.bo, false);
639 dump_state_batch(brw);
640 drm_intel_bo_unmap(brw->batch.bo);
641
642 if (0)
643 dump_prog_cache(brw);
644 }