src/mesa/drivers/dri/i965/brw_state_dump.c

   1 /*
   2  * Copyright © 2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "main/mtypes.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32
  33 /**
  34  * Prints out a header, the contents, and the message associated with
  35  * the hardware state data given.
  36  *
  37  * \param name Name of the state object
  38  * \param data Pointer to the base of the state object
  39  * \param hw_offset Hardware offset of the base of the state data.
  40  * \param index Index of the DWORD being output.
  41  */
  42 static void
  43 state_out(const char *name, void *data, uint32_t hw_offset, int index,
  44           char *fmt, ...)
  45 {
  46     va_list va;
  47
  48     fprintf(stderr, "%8s: 0x%08x: 0x%08x: ",
  49             name, hw_offset + index * 4, ((uint32_t *)data)[index]);
  50     va_start(va, fmt);
  51     vfprintf(stderr, fmt, va);
  52     va_end(va);
  53 }
  54
  55 /** Generic, undecoded state buffer debug printout */
  56 static void
  57 state_struct_out(const char *name, drm_intel_bo *buffer, unsigned int state_size)
  58 {
  59    int i;
  60
  61    if (buffer == NULL)
  62       return;
  63
  64    drm_intel_bo_map(buffer, GL_FALSE);
  65    for (i = 0; i < state_size / 4; i++) {
  66       state_out(name, buffer->virtual, buffer->offset, i,
  67                 "dword %d\n", i);
  68    }
  69    drm_intel_bo_unmap(buffer);
  70 }
  71
  72 static const char *
  73 get_965_surfacetype(unsigned int surfacetype)
  74 {
  75     switch (surfacetype) {
  76     case 0: return "1D";
  77     case 1: return "2D";
  78     case 2: return "3D";
  79     case 3: return "CUBE";
  80     case 4: return "BUFFER";
  81     case 7: return "NULL";
  82     default: return "unknown";
  83     }
  84 }
  85
  86 static const char *
  87 get_965_surface_format(unsigned int surface_format)
  88 {
  89     switch (surface_format) {
  90     case 0x000: return "r32g32b32a32_float";
  91     case 0x0c1: return "b8g8r8a8_unorm";
  92     case 0x100: return "b5g6r5_unorm";
  93     case 0x102: return "b5g5r5a1_unorm";
  94     case 0x104: return "b4g4r4a4_unorm";
  95     default: return "unknown";
  96     }
  97 }
  98
  99 static void dump_wm_surface_state(struct brw_context *brw)
 100 {
 101    int i;
 102
 103    for (i = 0; i < brw->wm.nr_surfaces; i++) {
 104       drm_intel_bo *surf_bo = brw->wm.surf_bo[i];
 105       unsigned int surfoff;
 106       struct brw_surface_state *surf;
 107       char name[20];
 108
 109       if (surf_bo == NULL) {
 110          fprintf(stderr, "  WM SS%d: NULL\n", i);
 111          continue;
 112       }
 113       drm_intel_bo_map(surf_bo, GL_FALSE);
 114       surfoff = surf_bo->offset + brw->wm.surf_offset[i];
 115       surf = (struct brw_surface_state *)(surf_bo->virtual + brw->wm.surf_offset[i]);
 116
 117       sprintf(name, "WM SS%d", i);
 118       state_out(name, surf, surfoff, 0, "%s %s\n",
 119                 get_965_surfacetype(surf->ss0.surface_type),
 120                 get_965_surface_format(surf->ss0.surface_format));
 121       state_out(name, surf, surfoff, 1, "offset\n");
 122       state_out(name, surf, surfoff, 2, "%dx%d size, %d mips\n",
 123                 surf->ss2.width + 1, surf->ss2.height + 1, surf->ss2.mip_count);
 124       state_out(name, surf, surfoff, 3, "pitch %d, %stiled\n",
 125                 surf->ss3.pitch + 1, surf->ss3.tiled_surface ? "" : "not ");
 126       state_out(name, surf, surfoff, 4, "mip base %d\n",
 127                 surf->ss4.min_lod);
 128       state_out(name, surf, surfoff, 5, "x,y offset: %d,%d\n",
 129                 surf->ss5.x_offset, surf->ss5.y_offset);
 130
 131       drm_intel_bo_unmap(surf_bo);
 132    }
 133 }
 134
 135 static void dump_sf_viewport_state(struct brw_context *brw)
 136 {
 137    const char *name = "SF VP";
 138    struct brw_sf_viewport *vp;
 139    uint32_t vp_off;
 140
 141    if (brw->sf.vp_bo == NULL)
 142       return;
 143
 144    drm_intel_bo_map(brw->sf.vp_bo, GL_FALSE);
 145
 146    vp = brw->sf.vp_bo->virtual;
 147    vp_off = brw->sf.vp_bo->offset;
 148
 149    state_out(name, vp, vp_off, 0, "m00 = %f\n", vp->viewport.m00);
 150    state_out(name, vp, vp_off, 1, "m11 = %f\n", vp->viewport.m11);
 151    state_out(name, vp, vp_off, 2, "m22 = %f\n", vp->viewport.m22);
 152    state_out(name, vp, vp_off, 3, "m30 = %f\n", vp->viewport.m30);
 153    state_out(name, vp, vp_off, 4, "m31 = %f\n", vp->viewport.m31);
 154    state_out(name, vp, vp_off, 5, "m32 = %f\n", vp->viewport.m32);
 155
 156    state_out(name, vp, vp_off, 6, "top left = %d,%d\n",
 157              vp->scissor.xmin, vp->scissor.ymin);
 158    state_out(name, vp, vp_off, 7, "bottom right = %d,%d\n",
 159              vp->scissor.xmax, vp->scissor.ymax);
 160
 161    drm_intel_bo_unmap(brw->sf.vp_bo);
 162 }
 163
 164 static void dump_clip_viewport_state(struct brw_context *brw)
 165 {
 166    const char *name = "CLIP VP";
 167    struct brw_clipper_viewport *vp;
 168    uint32_t vp_off;
 169
 170    if (brw->clip.vp_bo == NULL)
 171       return;
 172
 173    drm_intel_bo_map(brw->clip.vp_bo, GL_FALSE);
 174
 175    vp = brw->clip.vp_bo->virtual;
 176    vp_off = brw->clip.vp_bo->offset;
 177
 178    state_out(name, vp, vp_off, 0, "xmin = %f\n", vp->xmin);
 179    state_out(name, vp, vp_off, 1, "xmax = %f\n", vp->xmax);
 180    state_out(name, vp, vp_off, 2, "ymin = %f\n", vp->ymin);
 181    state_out(name, vp, vp_off, 3, "ymax = %f\n", vp->ymax);
 182    drm_intel_bo_unmap(brw->clip.vp_bo);
 183 }
 184
 185 static void dump_cc_viewport_state(struct brw_context *brw)
 186 {
 187    const char *name = "CC VP";
 188    struct brw_cc_viewport *vp;
 189    uint32_t vp_off;
 190
 191    if (brw->cc.vp_bo == NULL)
 192       return;
 193
 194    drm_intel_bo_map(brw->cc.vp_bo, GL_FALSE);
 195
 196    vp = brw->cc.vp_bo->virtual;
 197    vp_off = brw->cc.vp_bo->offset;
 198
 199    state_out(name, vp, vp_off, 0, "min_depth = %f\n", vp->min_depth);
 200    state_out(name, vp, vp_off, 1, "max_depth = %f\n", vp->max_depth);
 201    drm_intel_bo_unmap(brw->cc.vp_bo);
 202 }
 203
 204 static void dump_depth_stencil_state(struct brw_context *brw)
 205 {
 206    const char *name = "DEPTH STENCIL";
 207    struct gen6_depth_stencil_state *ds;
 208    uint32_t ds_off;
 209
 210    if (brw->cc.depth_stencil_state_bo == NULL)
 211         return;
 212
 213    drm_intel_bo_map(brw->cc.depth_stencil_state_bo, GL_FALSE);
 214
 215    ds = brw->cc.depth_stencil_state_bo->virtual;
 216    ds_off = brw->cc.depth_stencil_state_bo->offset;
 217
 218    state_out(name, ds, ds_off, 0, "stencil %sable, func %d, write %sable\n",
 219                 ds->ds0.stencil_enable ? "en" : "dis",
 220                 ds->ds0.stencil_func,
 221                 ds->ds0.stencil_write_enable ? "en" : "dis");
 222    state_out(name, ds, ds_off, 1, "stencil test mask 0x%x, write mask 0x%x\n",
 223                 ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
 224    state_out(name, ds, ds_off, 2, "depth test %sable, func %d, write %sable\n",
 225                 ds->ds2.depth_test_enable ? "en" : "dis",
 226                 ds->ds2.depth_test_func,
 227                 ds->ds2.depth_write_enable ? "en" : "dis");
 228    drm_intel_bo_unmap(brw->cc.depth_stencil_state_bo);
 229 }
 230
 231 static void dump_cc_state(struct brw_context *brw)
 232 {
 233    const char *name = "CC";
 234    struct gen6_color_calc_state *cc;
 235    uint32_t cc_off;
 236
 237    if (brw->cc.state_bo == NULL)
 238         return;
 239
 240    drm_intel_bo_map(brw->cc.state_bo, GL_FALSE);
 241    cc = brw->cc.state_bo->virtual;
 242    cc_off = brw->cc.state_bo->offset;
 243
 244    state_out(name, cc, cc_off, 0, "alpha test format %s, round disable %d, stencil ref %d,"
 245                 "bf stencil ref %d\n",
 246                 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
 247                 cc->cc0.round_disable,
 248                 cc->cc0.stencil_ref,
 249                 cc->cc0.bf_stencil_ref);
 250    state_out(name, cc, cc_off, 1, "\n");
 251    state_out(name, cc, cc_off, 2, "constant red %f\n", cc->constant_r);
 252    state_out(name, cc, cc_off, 3, "constant green %f\n", cc->constant_g);
 253    state_out(name, cc, cc_off, 4, "constant blue %f\n", cc->constant_b);
 254    state_out(name, cc, cc_off, 5, "constant alpha %f\n", cc->constant_a);
 255
 256    drm_intel_bo_unmap(brw->cc.state_bo);
 257
 258 }
 259
 260 static void dump_blend_state(struct brw_context *brw)
 261 {
 262    const char *name = "BLEND";
 263    struct gen6_blend_state *blend;
 264    uint32_t blend_off;
 265
 266    if (brw->cc.blend_state_bo == NULL)
 267         return;
 268
 269    drm_intel_bo_map(brw->cc.blend_state_bo, GL_FALSE);
 270
 271    blend = brw->cc.blend_state_bo->virtual;
 272    blend_off = brw->cc.blend_state_bo->offset;
 273
 274    state_out(name, blend, blend_off, 0, "\n");
 275    state_out(name, blend, blend_off, 1, "\n");
 276
 277    drm_intel_bo_unmap(brw->cc.blend_state_bo);
 278
 279 }
 280
 281 static void brw_debug_prog(const char *name, drm_intel_bo *prog)
 282 {
 283    unsigned int i;
 284    uint32_t *data;
 285
 286    if (prog == NULL)
 287       return;
 288
 289    drm_intel_bo_map(prog, GL_FALSE);
 290
 291    data = prog->virtual;
 292
 293    for (i = 0; i < prog->size / 4 / 4; i++) {
 294       fprintf(stderr, "%8s: 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 295               name, (unsigned int)prog->offset + i * 4 * 4,
 296               data[i * 4], data[i * 4 + 1], data[i * 4 + 2], data[i * 4 + 3]);
 297       /* Stop at the end of the program.  It'd be nice to keep track of the actual
 298        * intended program size instead of guessing like this.
 299        */
 300       if (data[i * 4 + 0] == 0 &&
 301           data[i * 4 + 1] == 0 &&
 302           data[i * 4 + 2] == 0 &&
 303           data[i * 4 + 3] == 0)
 304          break;
 305    }
 306
 307    drm_intel_bo_unmap(prog);
 308 }
 309
 310
 311 /**
 312  * Print additional debug information associated with the batchbuffer
 313  * when DEBUG_BATCH is set.
 314  *
 315  * For 965, this means mapping the state buffers that would have been referenced
 316  * by the batchbuffer and dumping them.
 317  *
 318  * The buffer offsets printed rely on the buffer containing the last offset
 319  * it was validated at.
 320  */
 321 void brw_debug_batch(struct intel_context *intel)
 322 {
 323    struct brw_context *brw = brw_context(&intel->ctx);
 324
 325    state_struct_out("WM bind", brw->wm.bind_bo, 4 * brw->wm.nr_surfaces);
 326    dump_wm_surface_state(brw);
 327
 328    if (intel->gen < 6)
 329        state_struct_out("VS", brw->vs.state_bo, sizeof(struct brw_vs_unit_state));
 330    brw_debug_prog("VS prog", brw->vs.prog_bo);
 331
 332    if (intel->gen < 6)
 333        state_struct_out("GS", brw->gs.state_bo, sizeof(struct brw_gs_unit_state));
 334    brw_debug_prog("GS prog", brw->gs.prog_bo);
 335
 336    if (intel->gen < 6) {
 337        state_struct_out("SF", brw->sf.state_bo, sizeof(struct brw_sf_unit_state));
 338        brw_debug_prog("SF prog", brw->sf.prog_bo);
 339    }
 340    dump_sf_viewport_state(brw);
 341
 342    if (intel->gen < 6)
 343        state_struct_out("WM", brw->wm.state_bo, sizeof(struct brw_wm_unit_state));
 344    brw_debug_prog("WM prog", brw->wm.prog_bo);
 345
 346    if (intel->gen >= 6) {
 347         dump_cc_viewport_state(brw);
 348         dump_clip_viewport_state(brw);
 349         dump_depth_stencil_state(brw);
 350         dump_cc_state(brw);
 351         dump_blend_state(brw);
 352    }
 353 }