i965: Use unreachable() instead of unconditional assert().
[mesa.git] / src / mesa / drivers / dri / i965 / brw_state_dump.c
1 /*
2 * Copyright © 2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include "main/mtypes.h"
29 #include "intel_batchbuffer.h"
30
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_eu.h"
34
35 static void
36 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
37 int index, char *fmt, ...) PRINTFLIKE(5, 6);
38
39 static void
40 batch_out(struct brw_context *brw, const char *name, uint32_t offset,
41 int index, char *fmt, ...)
42 {
43 uint32_t *data = brw->batch.bo->virtual + offset;
44 va_list va;
45
46 fprintf(stderr, "0x%08x: 0x%08x: %8s: ",
47 offset + index * 4, data[index], name);
48 va_start(va, fmt);
49 vfprintf(stderr, fmt, va);
50 va_end(va);
51 }
52
53 static const char *
54 get_965_surfacetype(unsigned int surfacetype)
55 {
56 switch (surfacetype) {
57 case 0: return "1D";
58 case 1: return "2D";
59 case 2: return "3D";
60 case 3: return "CUBE";
61 case 4: return "BUFFER";
62 case 7: return "NULL";
63 default: return "unknown";
64 }
65 }
66
67 static const char *
68 get_965_surface_format(unsigned int surface_format)
69 {
70 switch (surface_format) {
71 case 0x000: return "r32g32b32a32_float";
72 case 0x0c1: return "b8g8r8a8_unorm";
73 case 0x100: return "b5g6r5_unorm";
74 case 0x102: return "b5g5r5a1_unorm";
75 case 0x104: return "b4g4r4a4_unorm";
76 default: return "unknown";
77 }
78 }
79
80 static void dump_vs_state(struct brw_context *brw, uint32_t offset)
81 {
82 const char *name = "VS_STATE";
83 struct brw_vs_unit_state *vs = brw->batch.bo->virtual + offset;
84
85 batch_out(brw, name, offset, 0, "thread0\n");
86 batch_out(brw, name, offset, 1, "thread1\n");
87 batch_out(brw, name, offset, 2, "thread2\n");
88 batch_out(brw, name, offset, 3, "thread3\n");
89 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
90 vs->thread4.max_threads + 1);
91 batch_out(brw, name, offset, 5, "vs5\n");
92 batch_out(brw, name, offset, 6, "vs6\n");
93 }
94
95 static void dump_gs_state(struct brw_context *brw, uint32_t offset)
96 {
97 const char *name = "GS_STATE";
98 struct brw_gs_unit_state *gs = brw->batch.bo->virtual + offset;
99
100 batch_out(brw, name, offset, 0, "thread0\n");
101 batch_out(brw, name, offset, 1, "thread1\n");
102 batch_out(brw, name, offset, 2, "thread2\n");
103 batch_out(brw, name, offset, 3, "thread3\n");
104 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
105 gs->thread4.max_threads + 1);
106 batch_out(brw, name, offset, 5, "vs5\n");
107 batch_out(brw, name, offset, 6, "vs6\n");
108 }
109
110 static void dump_clip_state(struct brw_context *brw, uint32_t offset)
111 {
112 const char *name = "CLIP_STATE";
113 struct brw_clip_unit_state *clip = brw->batch.bo->virtual + offset;
114
115 batch_out(brw, name, offset, 0, "thread0\n");
116 batch_out(brw, name, offset, 1, "thread1\n");
117 batch_out(brw, name, offset, 2, "thread2\n");
118 batch_out(brw, name, offset, 3, "thread3\n");
119 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
120 clip->thread4.max_threads + 1);
121 batch_out(brw, name, offset, 5, "clip5\n");
122 batch_out(brw, name, offset, 6, "clip6\n");
123 batch_out(brw, name, offset, 7, "vp xmin %f\n", clip->viewport_xmin);
124 batch_out(brw, name, offset, 8, "vp xmax %f\n", clip->viewport_xmax);
125 batch_out(brw, name, offset, 9, "vp ymin %f\n", clip->viewport_ymin);
126 batch_out(brw, name, offset, 10, "vp ymax %f\n", clip->viewport_ymax);
127 }
128
129 static void dump_sf_state(struct brw_context *brw, uint32_t offset)
130 {
131 const char *name = "SF_STATE";
132 struct brw_sf_unit_state *sf = brw->batch.bo->virtual + offset;
133
134 batch_out(brw, name, offset, 0, "thread0\n");
135 batch_out(brw, name, offset, 1, "thread1\n");
136 batch_out(brw, name, offset, 2, "thread2\n");
137 batch_out(brw, name, offset, 3, "thread3\n");
138 batch_out(brw, name, offset, 4, "thread4: %d threads\n",
139 sf->thread4.max_threads + 1);
140 batch_out(brw, name, offset, 5, "sf5: viewport offset\n");
141 batch_out(brw, name, offset, 6, "sf6\n");
142 batch_out(brw, name, offset, 7, "sf7\n");
143 }
144
145 static void dump_wm_state(struct brw_context *brw, uint32_t offset)
146 {
147 const char *name = "WM_STATE";
148 struct brw_wm_unit_state *wm = brw->batch.bo->virtual + offset;
149
150 batch_out(brw, name, offset, 0, "thread0\n");
151 batch_out(brw, name, offset, 1, "thread1\n");
152 batch_out(brw, name, offset, 2, "thread2\n");
153 batch_out(brw, name, offset, 3, "thread3\n");
154 batch_out(brw, name, offset, 4, "wm4\n");
155 batch_out(brw, name, offset, 5, "wm5: %s%s%s%s%s%s, %d threads\n",
156 wm->wm5.enable_8_pix ? "8pix" : "",
157 wm->wm5.enable_16_pix ? "16pix" : "",
158 wm->wm5.program_uses_depth ? ", uses depth" : "",
159 wm->wm5.program_computes_depth ? ", computes depth" : "",
160 wm->wm5.program_uses_killpixel ? ", kills" : "",
161 wm->wm5.thread_dispatch_enable ? "" : ", no dispatch",
162 wm->wm5.max_threads + 1);
163 batch_out(brw, name, offset, 6, "depth offset constant %f\n",
164 wm->global_depth_offset_constant);
165 batch_out(brw, name, offset, 7, "depth offset scale %f\n",
166 wm->global_depth_offset_scale);
167 batch_out(brw, name, offset, 8, "wm8: kernel 1 (gen5+)\n");
168 batch_out(brw, name, offset, 9, "wm9: kernel 2 (gen5+)\n");
169 batch_out(brw, name, offset, 10, "wm10: kernel 3 (gen5+)\n");
170 }
171
172 static void dump_surface_state(struct brw_context *brw, uint32_t offset)
173 {
174 const char *name = "SURF";
175 uint32_t *surf = brw->batch.bo->virtual + offset;
176
177 batch_out(brw, name, offset, 0, "%s %s\n",
178 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
179 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)));
180 batch_out(brw, name, offset, 1, "offset\n");
181 batch_out(brw, name, offset, 2, "%dx%d size, %d mips\n",
182 GET_FIELD(surf[2], BRW_SURFACE_WIDTH) + 1,
183 GET_FIELD(surf[2], BRW_SURFACE_HEIGHT) + 1,
184 GET_FIELD(surf[2], BRW_SURFACE_LOD));
185 batch_out(brw, name, offset, 3, "pitch %d, %s tiled\n",
186 GET_FIELD(surf[3], BRW_SURFACE_PITCH) + 1,
187 (surf[3] & BRW_SURFACE_TILED) ?
188 ((surf[3] & BRW_SURFACE_TILED_Y) ? "Y" : "X") : "not");
189 batch_out(brw, name, offset, 4, "mip base %d\n",
190 GET_FIELD(surf[4], BRW_SURFACE_MIN_LOD));
191 batch_out(brw, name, offset, 5, "x,y offset: %d,%d\n",
192 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
193 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
194 }
195
196 static void dump_gen7_surface_state(struct brw_context *brw, uint32_t offset)
197 {
198 const char *name = "SURF";
199 uint32_t *surf = brw->batch.bo->virtual + offset;
200
201 batch_out(brw, name, offset, 0, "%s %s %s\n",
202 get_965_surfacetype(GET_FIELD(surf[0], BRW_SURFACE_TYPE)),
203 get_965_surface_format(GET_FIELD(surf[0], BRW_SURFACE_FORMAT)),
204 (surf[0] & GEN7_SURFACE_IS_ARRAY) ? "array" : "");
205 batch_out(brw, name, offset, 1, "offset\n");
206 batch_out(brw, name, offset, 2, "%dx%d size, %d mips, %d slices\n",
207 GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1,
208 GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1,
209 surf[5] & INTEL_MASK(3, 0),
210 GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1);
211 batch_out(brw, name, offset, 3, "pitch %d, %stiled\n",
212 (surf[3] & INTEL_MASK(17, 0)) + 1,
213 (surf[0] & (1 << 14)) ? "" : "not ");
214 batch_out(brw, name, offset, 4, "min array element %d, array extent %d\n",
215 GET_FIELD(surf[4], GEN7_SURFACE_MIN_ARRAY_ELEMENT),
216 GET_FIELD(surf[4], GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT) + 1);
217 batch_out(brw, name, offset, 5, "mip base %d\n",
218 GET_FIELD(surf[5], GEN7_SURFACE_MIN_LOD));
219 batch_out(brw, name, offset, 6, "x,y offset: %d,%d\n",
220 GET_FIELD(surf[5], BRW_SURFACE_X_OFFSET),
221 GET_FIELD(surf[5], BRW_SURFACE_Y_OFFSET));
222 batch_out(brw, name, offset, 7, "\n");
223 }
224
225 static void
226 dump_sdc(struct brw_context *brw, uint32_t offset)
227 {
228 const char *name = "SDC";
229
230 if (brw->gen >= 5 && brw->gen <= 6) {
231 struct gen5_sampler_default_color *sdc = (brw->batch.bo->virtual +
232 offset);
233 batch_out(brw, name, offset, 0, "unorm rgba\n");
234 batch_out(brw, name, offset, 1, "r %f\n", sdc->f[0]);
235 batch_out(brw, name, offset, 2, "b %f\n", sdc->f[1]);
236 batch_out(brw, name, offset, 3, "g %f\n", sdc->f[2]);
237 batch_out(brw, name, offset, 4, "a %f\n", sdc->f[3]);
238 batch_out(brw, name, offset, 5, "half float rg\n");
239 batch_out(brw, name, offset, 6, "half float ba\n");
240 batch_out(brw, name, offset, 7, "u16 rg\n");
241 batch_out(brw, name, offset, 8, "u16 ba\n");
242 batch_out(brw, name, offset, 9, "s16 rg\n");
243 batch_out(brw, name, offset, 10, "s16 ba\n");
244 batch_out(brw, name, offset, 11, "s8 rgba\n");
245 } else {
246 struct brw_sampler_default_color *sdc = (brw->batch.bo->virtual +
247 offset);
248 batch_out(brw, name, offset, 0, "r %f\n", sdc->color[0]);
249 batch_out(brw, name, offset, 1, "g %f\n", sdc->color[1]);
250 batch_out(brw, name, offset, 2, "b %f\n", sdc->color[2]);
251 batch_out(brw, name, offset, 3, "a %f\n", sdc->color[3]);
252 }
253 }
254
255 static void dump_sampler_state(struct brw_context *brw,
256 uint32_t offset, uint32_t size)
257 {
258 int i;
259 struct brw_sampler_state *samp = brw->batch.bo->virtual + offset;
260
261 assert(brw->gen < 7);
262
263 for (i = 0; i < size / sizeof(*samp); i++) {
264 char name[20];
265
266 sprintf(name, "WM SAMP%d", i);
267 batch_out(brw, name, offset, 0, "filtering\n");
268 batch_out(brw, name, offset, 1, "wrapping, lod\n");
269 batch_out(brw, name, offset, 2, "default color pointer\n");
270 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
271
272 samp++;
273 offset += sizeof(*samp);
274 }
275 }
276
277 static void dump_gen7_sampler_state(struct brw_context *brw,
278 uint32_t offset, uint32_t size)
279 {
280 struct gen7_sampler_state *samp = brw->batch.bo->virtual + offset;
281 int i;
282
283 assert(brw->gen >= 7);
284
285 for (i = 0; i < size / sizeof(*samp); i++) {
286 char name[20];
287
288 sprintf(name, "WM SAMP%d", i);
289 batch_out(brw, name, offset, 0, "filtering\n");
290 batch_out(brw, name, offset, 1, "wrapping, lod\n");
291 batch_out(brw, name, offset, 2, "default color pointer\n");
292 batch_out(brw, name, offset, 3, "chroma key, aniso\n");
293
294 samp++;
295 offset += sizeof(*samp);
296 }
297 }
298
299
300 static void dump_sf_viewport_state(struct brw_context *brw,
301 uint32_t offset)
302 {
303 const char *name = "SF VP";
304 struct brw_sf_viewport *vp = brw->batch.bo->virtual + offset;
305
306 assert(brw->gen < 7);
307
308 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
309 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
310 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
311 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
312 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
313 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
314
315 batch_out(brw, name, offset, 6, "top left = %d,%d\n",
316 vp->scissor.xmin, vp->scissor.ymin);
317 batch_out(brw, name, offset, 7, "bottom right = %d,%d\n",
318 vp->scissor.xmax, vp->scissor.ymax);
319 }
320
321 static void dump_clip_viewport_state(struct brw_context *brw,
322 uint32_t offset)
323 {
324 const char *name = "CLIP VP";
325 struct brw_clipper_viewport *vp = brw->batch.bo->virtual + offset;
326
327 assert(brw->gen < 7);
328
329 batch_out(brw, name, offset, 0, "xmin = %f\n", vp->xmin);
330 batch_out(brw, name, offset, 1, "xmax = %f\n", vp->xmax);
331 batch_out(brw, name, offset, 2, "ymin = %f\n", vp->ymin);
332 batch_out(brw, name, offset, 3, "ymax = %f\n", vp->ymax);
333 }
334
335 static void dump_sf_clip_viewport_state(struct brw_context *brw,
336 uint32_t offset)
337 {
338 const char *name = "SF_CLIP VP";
339 struct gen7_sf_clip_viewport *vp = brw->batch.bo->virtual + offset;
340
341 assert(brw->gen >= 7);
342
343 batch_out(brw, name, offset, 0, "m00 = %f\n", vp->viewport.m00);
344 batch_out(brw, name, offset, 1, "m11 = %f\n", vp->viewport.m11);
345 batch_out(brw, name, offset, 2, "m22 = %f\n", vp->viewport.m22);
346 batch_out(brw, name, offset, 3, "m30 = %f\n", vp->viewport.m30);
347 batch_out(brw, name, offset, 4, "m31 = %f\n", vp->viewport.m31);
348 batch_out(brw, name, offset, 5, "m32 = %f\n", vp->viewport.m32);
349 batch_out(brw, name, offset, 6, "guardband xmin = %f\n", vp->guardband.xmin);
350 batch_out(brw, name, offset, 7, "guardband xmax = %f\n", vp->guardband.xmax);
351 batch_out(brw, name, offset, 8, "guardband ymin = %f\n", vp->guardband.ymin);
352 batch_out(brw, name, offset, 9, "guardband ymax = %f\n", vp->guardband.ymax);
353 }
354
355
356 static void dump_cc_viewport_state(struct brw_context *brw, uint32_t offset)
357 {
358 const char *name = "CC VP";
359 struct brw_cc_viewport *vp = brw->batch.bo->virtual + offset;
360
361 batch_out(brw, name, offset, 0, "min_depth = %f\n", vp->min_depth);
362 batch_out(brw, name, offset, 1, "max_depth = %f\n", vp->max_depth);
363 }
364
365 static void dump_depth_stencil_state(struct brw_context *brw, uint32_t offset)
366 {
367 const char *name = "D_S";
368 struct gen6_depth_stencil_state *ds = brw->batch.bo->virtual + offset;
369
370 batch_out(brw, name, offset, 0,
371 "stencil %sable, func %d, write %sable\n",
372 ds->ds0.stencil_enable ? "en" : "dis",
373 ds->ds0.stencil_func,
374 ds->ds0.stencil_write_enable ? "en" : "dis");
375 batch_out(brw, name, offset, 1,
376 "stencil test mask 0x%x, write mask 0x%x\n",
377 ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
378 batch_out(brw, name, offset, 2,
379 "depth test %sable, func %d, write %sable\n",
380 ds->ds2.depth_test_enable ? "en" : "dis",
381 ds->ds2.depth_test_func,
382 ds->ds2.depth_write_enable ? "en" : "dis");
383 }
384
385 static void dump_cc_state_gen4(struct brw_context *brw, uint32_t offset)
386 {
387 const char *name = "CC";
388
389 batch_out(brw, name, offset, 0, "cc0\n");
390 batch_out(brw, name, offset, 1, "cc1\n");
391 batch_out(brw, name, offset, 2, "cc2\n");
392 batch_out(brw, name, offset, 3, "cc3\n");
393 batch_out(brw, name, offset, 4, "cc4: viewport offset\n");
394 batch_out(brw, name, offset, 5, "cc5\n");
395 batch_out(brw, name, offset, 6, "cc6\n");
396 batch_out(brw, name, offset, 7, "cc7\n");
397 }
398
399 static void dump_cc_state_gen6(struct brw_context *brw, uint32_t offset)
400 {
401 const char *name = "CC";
402 struct gen6_color_calc_state *cc = brw->batch.bo->virtual + offset;
403
404 batch_out(brw, name, offset, 0,
405 "alpha test format %s, round disable %d, stencil ref %d, "
406 "bf stencil ref %d\n",
407 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
408 cc->cc0.round_disable,
409 cc->cc0.stencil_ref,
410 cc->cc0.bf_stencil_ref);
411 batch_out(brw, name, offset, 1, "\n");
412 batch_out(brw, name, offset, 2, "constant red %f\n", cc->constant_r);
413 batch_out(brw, name, offset, 3, "constant green %f\n", cc->constant_g);
414 batch_out(brw, name, offset, 4, "constant blue %f\n", cc->constant_b);
415 batch_out(brw, name, offset, 5, "constant alpha %f\n", cc->constant_a);
416 }
417
418 static void dump_blend_state(struct brw_context *brw, uint32_t offset)
419 {
420 const char *name = "BLEND";
421
422 batch_out(brw, name, offset, 0, "\n");
423 batch_out(brw, name, offset, 1, "\n");
424 }
425
426 static void
427 dump_scissor(struct brw_context *brw, uint32_t offset)
428 {
429 const char *name = "SCISSOR";
430 struct gen6_scissor_rect *scissor = brw->batch.bo->virtual + offset;
431
432 batch_out(brw, name, offset, 0, "xmin %d, ymin %d\n",
433 scissor->xmin, scissor->ymin);
434 batch_out(brw, name, offset, 1, "xmax %d, ymax %d\n",
435 scissor->xmax, scissor->ymax);
436 }
437
438 static void
439 dump_vs_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
440 {
441 const char *name = "VS_CONST";
442 uint32_t *as_uint = brw->batch.bo->virtual + offset;
443 float *as_float = brw->batch.bo->virtual + offset;
444 int i;
445
446 for (i = 0; i < size / 4; i += 4) {
447 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
448 i / 4,
449 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
450 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
451 }
452 }
453
454 static void
455 dump_wm_constants(struct brw_context *brw, uint32_t offset, uint32_t size)
456 {
457 const char *name = "WM_CONST";
458 uint32_t *as_uint = brw->batch.bo->virtual + offset;
459 float *as_float = brw->batch.bo->virtual + offset;
460 int i;
461
462 for (i = 0; i < size / 4; i += 4) {
463 batch_out(brw, name, offset, i, "%3d: (% f % f % f % f) (0x%08x 0x%08x 0x%08x 0x%08x)\n",
464 i / 4,
465 as_float[i], as_float[i + 1], as_float[i + 2], as_float[i + 3],
466 as_uint[i], as_uint[i + 1], as_uint[i + 2], as_uint[i + 3]);
467 }
468 }
469
470 static void dump_binding_table(struct brw_context *brw, uint32_t offset,
471 uint32_t size)
472 {
473 char name[20];
474 int i;
475 uint32_t *data = brw->batch.bo->virtual + offset;
476
477 for (i = 0; i < size / 4; i++) {
478 if (data[i] == 0)
479 continue;
480
481 sprintf(name, "BIND%d", i);
482 batch_out(brw, name, offset, i, "surface state address\n");
483 }
484 }
485
486 static void
487 dump_prog_cache(struct brw_context *brw)
488 {
489 struct brw_cache *cache = &brw->cache;
490 unsigned int b;
491
492 drm_intel_bo_map(brw->cache.bo, false);
493
494 for (b = 0; b < cache->size; b++) {
495 struct brw_cache_item *item;
496
497 for (item = cache->items[b]; item; item = item->next) {
498 const char *name;
499
500 switch (item->cache_id) {
501 case BRW_VS_PROG:
502 name = "VS kernel";
503 break;
504 case BRW_FF_GS_PROG:
505 name = "Fixed-function GS kernel";
506 break;
507 case BRW_GS_PROG:
508 name = "GS kernel";
509 break;
510 case BRW_CLIP_PROG:
511 name = "CLIP kernel";
512 break;
513 case BRW_SF_PROG:
514 name = "SF kernel";
515 break;
516 case BRW_WM_PROG:
517 name = "WM kernel";
518 break;
519 default:
520 name = "unknown";
521 break;
522 }
523
524 fprintf(stderr, "%s:\n", name);
525 brw_disassemble(brw, brw->cache.bo->virtual, item->offset, item->size,
526 stderr);
527 }
528 }
529
530 drm_intel_bo_unmap(brw->cache.bo);
531 }
532
533 static void
534 dump_state_batch(struct brw_context *brw)
535 {
536 int i;
537
538 for (i = 0; i < brw->state_batch_count; i++) {
539 uint32_t offset = brw->state_batch_list[i].offset;
540 uint32_t size = brw->state_batch_list[i].size;
541
542 switch (brw->state_batch_list[i].type) {
543 case AUB_TRACE_VS_STATE:
544 dump_vs_state(brw, offset);
545 break;
546 case AUB_TRACE_GS_STATE:
547 dump_gs_state(brw, offset);
548 break;
549 case AUB_TRACE_CLIP_STATE:
550 dump_clip_state(brw, offset);
551 break;
552 case AUB_TRACE_SF_STATE:
553 dump_sf_state(brw, offset);
554 break;
555 case AUB_TRACE_WM_STATE:
556 dump_wm_state(brw, offset);
557 break;
558 case AUB_TRACE_CLIP_VP_STATE:
559 dump_clip_viewport_state(brw, offset);
560 break;
561 case AUB_TRACE_SF_VP_STATE:
562 if (brw->gen >= 7) {
563 dump_sf_clip_viewport_state(brw, offset);
564 } else {
565 dump_sf_viewport_state(brw, offset);
566 }
567 break;
568 case AUB_TRACE_CC_VP_STATE:
569 dump_cc_viewport_state(brw, offset);
570 break;
571 case AUB_TRACE_DEPTH_STENCIL_STATE:
572 dump_depth_stencil_state(brw, offset);
573 break;
574 case AUB_TRACE_CC_STATE:
575 if (brw->gen >= 6)
576 dump_cc_state_gen6(brw, offset);
577 else
578 dump_cc_state_gen4(brw, offset);
579 break;
580 case AUB_TRACE_BLEND_STATE:
581 dump_blend_state(brw, offset);
582 break;
583 case AUB_TRACE_BINDING_TABLE:
584 dump_binding_table(brw, offset, size);
585 break;
586 case AUB_TRACE_SURFACE_STATE:
587 if (brw->gen < 7) {
588 dump_surface_state(brw, offset);
589 } else {
590 dump_gen7_surface_state(brw, offset);
591 }
592 break;
593 case AUB_TRACE_SAMPLER_STATE:
594 if (brw->gen < 7) {
595 dump_sampler_state(brw, offset, size);
596 } else {
597 dump_gen7_sampler_state(brw, offset, size);
598 }
599 break;
600 case AUB_TRACE_SAMPLER_DEFAULT_COLOR:
601 dump_sdc(brw, offset);
602 break;
603 case AUB_TRACE_SCISSOR_STATE:
604 dump_scissor(brw, offset);
605 break;
606 case AUB_TRACE_VS_CONSTANTS:
607 dump_vs_constants(brw, offset, size);
608 break;
609 case AUB_TRACE_WM_CONSTANTS:
610 dump_wm_constants(brw, offset, size);
611 break;
612 default:
613 break;
614 }
615 }
616 }
617
618 /**
619 * Print additional debug information associated with the batchbuffer
620 * when DEBUG_BATCH is set.
621 *
622 * For 965, this means mapping the state buffers that would have been referenced
623 * by the batchbuffer and dumping them.
624 *
625 * The buffer offsets printed rely on the buffer containing the last offset
626 * it was validated at.
627 */
628 void brw_debug_batch(struct brw_context *brw)
629 {
630 drm_intel_bo_map(brw->batch.bo, false);
631 dump_state_batch(brw);
632 drm_intel_bo_unmap(brw->batch.bo);
633
634 if (0)
635 dump_prog_cache(brw);
636 }