src/mesa/drivers/dri/i965/brw_state_dump.c

   1 /*
   2  * Copyright © 2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "main/mtypes.h"
  29 #include "intel_batchbuffer.h"
  30
  31 #include "brw_context.h"
  32 #include "brw_defines.h"
  33
  34 /**
  35  * Prints out a header, the contents, and the message associated with
  36  * the hardware state data given.
  37  *
  38  * \param name Name of the state object
  39  * \param data Pointer to the base of the state object
  40  * \param hw_offset Hardware offset of the base of the state data.
  41  * \param index Index of the DWORD being output.
  42  */
  43 static void
  44 state_out(const char *name, void *data, uint32_t hw_offset, int index,
  45           char *fmt, ...)
  46 {
  47     va_list va;
  48
  49     fprintf(stderr, "%8s: 0x%08x: 0x%08x: ",
  50             name, hw_offset + index * 4, ((uint32_t *)data)[index]);
  51     va_start(va, fmt);
  52     vfprintf(stderr, fmt, va);
  53     va_end(va);
  54 }
  55
  56 /** Generic, undecoded state buffer debug printout */
  57 static void
  58 state_struct_out(const char *name, drm_intel_bo *buffer,
  59                  unsigned int offset, unsigned int size)
  60 {
  61    int i;
  62
  63    if (buffer == NULL)
  64       return;
  65
  66    drm_intel_bo_map(buffer, GL_FALSE);
  67    for (i = 0; i < size / 4; i++) {
  68       state_out(name, buffer->virtual + offset, buffer->offset + offset, i,
  69                 "dword %d\n", i);
  70    }
  71    drm_intel_bo_unmap(buffer);
  72 }
  73
  74 static const char *
  75 get_965_surfacetype(unsigned int surfacetype)
  76 {
  77     switch (surfacetype) {
  78     case 0: return "1D";
  79     case 1: return "2D";
  80     case 2: return "3D";
  81     case 3: return "CUBE";
  82     case 4: return "BUFFER";
  83     case 7: return "NULL";
  84     default: return "unknown";
  85     }
  86 }
  87
  88 static const char *
  89 get_965_surface_format(unsigned int surface_format)
  90 {
  91     switch (surface_format) {
  92     case 0x000: return "r32g32b32a32_float";
  93     case 0x0c1: return "b8g8r8a8_unorm";
  94     case 0x100: return "b5g6r5_unorm";
  95     case 0x102: return "b5g5r5a1_unorm";
  96     case 0x104: return "b4g4r4a4_unorm";
  97     default: return "unknown";
  98     }
  99 }
 100
 101 static void dump_wm_surface_state(struct brw_context *brw)
 102 {
 103    dri_bo *bo;
 104    GLubyte *base;
 105    int i;
 106
 107    bo = brw->intel.batch.bo;
 108    drm_intel_bo_map(bo, GL_FALSE);
 109    base = bo->virtual;
 110
 111    for (i = 0; i < brw->wm.nr_surfaces; i++) {
 112       unsigned int surfoff;
 113       struct brw_surface_state *surf;
 114       char name[20];
 115
 116       if (brw->wm.surf_offset[i] == 0) {
 117          fprintf(stderr, "WM SURF%d: NULL\n", i);
 118          continue;
 119       }
 120       surfoff = bo->offset + brw->wm.surf_offset[i];
 121       surf = (struct brw_surface_state *)(base + brw->wm.surf_offset[i]);
 122
 123       sprintf(name, "WM SURF%d", i);
 124       state_out(name, surf, surfoff, 0, "%s %s\n",
 125                 get_965_surfacetype(surf->ss0.surface_type),
 126                 get_965_surface_format(surf->ss0.surface_format));
 127       state_out(name, surf, surfoff, 1, "offset\n");
 128       state_out(name, surf, surfoff, 2, "%dx%d size, %d mips\n",
 129                 surf->ss2.width + 1, surf->ss2.height + 1, surf->ss2.mip_count);
 130       state_out(name, surf, surfoff, 3, "pitch %d, %stiled\n",
 131                 surf->ss3.pitch + 1, surf->ss3.tiled_surface ? "" : "not ");
 132       state_out(name, surf, surfoff, 4, "mip base %d\n",
 133                 surf->ss4.min_lod);
 134       state_out(name, surf, surfoff, 5, "x,y offset: %d,%d\n",
 135                 surf->ss5.x_offset, surf->ss5.y_offset);
 136    }
 137    drm_intel_bo_unmap(bo);
 138 }
 139
 140
 141 static void dump_wm_sampler_state(struct brw_context *brw)
 142 {
 143    struct gl_context *ctx = &brw->intel.ctx;
 144    int i;
 145
 146    if (!brw->wm.sampler_bo) {
 147       fprintf(stderr, "WM_SAMPLER: NULL\n");
 148       return;
 149    }
 150
 151    drm_intel_bo_map(brw->wm.sampler_bo, GL_FALSE);
 152    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 153       unsigned int offset;
 154       struct brw_sampler_state *samp;
 155       struct brw_sampler_default_color *sdc;
 156       char name[20];
 157
 158       if (!ctx->Texture.Unit[i]._ReallyEnabled) {
 159          fprintf(stderr, "WM SAMP%d: disabled\n", i);
 160          continue;
 161       }
 162
 163       offset = brw->wm.sampler_bo->offset +
 164          i * sizeof(struct brw_sampler_state);
 165       samp = (struct brw_sampler_state *)(brw->wm.sampler_bo->virtual +
 166                                           i * sizeof(struct brw_sampler_state));
 167
 168       sprintf(name, "WM SAMP%d", i);
 169       state_out(name, samp, offset, 0, "filtering\n");
 170       state_out(name, samp, offset, 1, "wrapping, lod\n");
 171       state_out(name, samp, offset, 2, "default color pointer\n");
 172       state_out(name, samp, offset, 3, "chroma key, aniso\n");
 173
 174       sprintf(name, " WM SDC%d", i);
 175
 176       drm_intel_bo_map(brw->wm.sdc_bo[i], GL_FALSE);
 177       sdc = (struct brw_sampler_default_color *)(brw->wm.sdc_bo[i]->virtual);
 178       state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 0, "r\n");
 179       state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 1, "g\n");
 180       state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 2, "b\n");
 181       state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 3, "a\n");
 182       drm_intel_bo_unmap(brw->wm.sdc_bo[i]);
 183    }
 184    drm_intel_bo_unmap(brw->wm.sampler_bo);
 185 }
 186
 187 static void dump_sf_viewport_state(struct brw_context *brw)
 188 {
 189    const char *name = "SF VP";
 190    struct brw_sf_viewport *vp;
 191    uint32_t vp_off;
 192
 193    if (brw->sf.vp_bo == NULL)
 194       return;
 195
 196    drm_intel_bo_map(brw->sf.vp_bo, GL_FALSE);
 197
 198    vp = brw->sf.vp_bo->virtual;
 199    vp_off = brw->sf.vp_bo->offset;
 200
 201    state_out(name, vp, vp_off, 0, "m00 = %f\n", vp->viewport.m00);
 202    state_out(name, vp, vp_off, 1, "m11 = %f\n", vp->viewport.m11);
 203    state_out(name, vp, vp_off, 2, "m22 = %f\n", vp->viewport.m22);
 204    state_out(name, vp, vp_off, 3, "m30 = %f\n", vp->viewport.m30);
 205    state_out(name, vp, vp_off, 4, "m31 = %f\n", vp->viewport.m31);
 206    state_out(name, vp, vp_off, 5, "m32 = %f\n", vp->viewport.m32);
 207
 208    state_out(name, vp, vp_off, 6, "top left = %d,%d\n",
 209              vp->scissor.xmin, vp->scissor.ymin);
 210    state_out(name, vp, vp_off, 7, "bottom right = %d,%d\n",
 211              vp->scissor.xmax, vp->scissor.ymax);
 212
 213    drm_intel_bo_unmap(brw->sf.vp_bo);
 214 }
 215
 216 static void dump_clip_viewport_state(struct brw_context *brw)
 217 {
 218    const char *name = "CLIP VP";
 219    struct brw_clipper_viewport *vp;
 220    uint32_t vp_off;
 221
 222    if (brw->clip.vp_bo == NULL)
 223       return;
 224
 225    drm_intel_bo_map(brw->clip.vp_bo, GL_FALSE);
 226
 227    vp = brw->clip.vp_bo->virtual;
 228    vp_off = brw->clip.vp_bo->offset;
 229
 230    state_out(name, vp, vp_off, 0, "xmin = %f\n", vp->xmin);
 231    state_out(name, vp, vp_off, 1, "xmax = %f\n", vp->xmax);
 232    state_out(name, vp, vp_off, 2, "ymin = %f\n", vp->ymin);
 233    state_out(name, vp, vp_off, 3, "ymax = %f\n", vp->ymax);
 234    drm_intel_bo_unmap(brw->clip.vp_bo);
 235 }
 236
 237 static void dump_cc_viewport_state(struct brw_context *brw)
 238 {
 239    const char *name = "CC VP";
 240    struct brw_cc_viewport *vp;
 241    uint32_t vp_off;
 242
 243    if (brw->cc.vp_bo == NULL)
 244       return;
 245
 246    drm_intel_bo_map(brw->cc.vp_bo, GL_FALSE);
 247
 248    vp = brw->cc.vp_bo->virtual;
 249    vp_off = brw->cc.vp_bo->offset;
 250
 251    state_out(name, vp, vp_off, 0, "min_depth = %f\n", vp->min_depth);
 252    state_out(name, vp, vp_off, 1, "max_depth = %f\n", vp->max_depth);
 253    drm_intel_bo_unmap(brw->cc.vp_bo);
 254 }
 255
 256 static void dump_depth_stencil_state(struct brw_context *brw)
 257 {
 258    const char *name = "DEPTH STENCIL";
 259    struct gen6_depth_stencil_state *ds;
 260    uint32_t ds_off;
 261
 262    if (brw->cc.depth_stencil_state_bo == NULL)
 263         return;
 264
 265    drm_intel_bo_map(brw->cc.depth_stencil_state_bo, GL_FALSE);
 266
 267    ds = brw->cc.depth_stencil_state_bo->virtual;
 268    ds_off = brw->cc.depth_stencil_state_bo->offset;
 269
 270    state_out(name, ds, ds_off, 0, "stencil %sable, func %d, write %sable\n",
 271                 ds->ds0.stencil_enable ? "en" : "dis",
 272                 ds->ds0.stencil_func,
 273                 ds->ds0.stencil_write_enable ? "en" : "dis");
 274    state_out(name, ds, ds_off, 1, "stencil test mask 0x%x, write mask 0x%x\n",
 275                 ds->ds1.stencil_test_mask, ds->ds1.stencil_write_mask);
 276    state_out(name, ds, ds_off, 2, "depth test %sable, func %d, write %sable\n",
 277                 ds->ds2.depth_test_enable ? "en" : "dis",
 278                 ds->ds2.depth_test_func,
 279                 ds->ds2.depth_write_enable ? "en" : "dis");
 280    drm_intel_bo_unmap(brw->cc.depth_stencil_state_bo);
 281 }
 282
 283 static void dump_cc_state(struct brw_context *brw)
 284 {
 285    const char *name = "CC";
 286    struct gen6_color_calc_state *cc;
 287    uint32_t cc_off;
 288    dri_bo *bo = brw->intel.batch.bo;
 289
 290    if (brw->cc.state_offset == 0)
 291         return;
 292
 293    drm_intel_bo_map(bo, GL_FALSE);
 294    cc = bo->virtual;
 295    cc_off = bo->offset;
 296
 297    state_out(name, cc, cc_off, 0, "alpha test format %s, round disable %d, stencil ref %d,"
 298                 "bf stencil ref %d\n",
 299                 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
 300                 cc->cc0.round_disable,
 301                 cc->cc0.stencil_ref,
 302                 cc->cc0.bf_stencil_ref);
 303    state_out(name, cc, cc_off, 1, "\n");
 304    state_out(name, cc, cc_off, 2, "constant red %f\n", cc->constant_r);
 305    state_out(name, cc, cc_off, 3, "constant green %f\n", cc->constant_g);
 306    state_out(name, cc, cc_off, 4, "constant blue %f\n", cc->constant_b);
 307    state_out(name, cc, cc_off, 5, "constant alpha %f\n", cc->constant_a);
 308
 309    drm_intel_bo_unmap(bo);
 310
 311 }
 312
 313 static void dump_blend_state(struct brw_context *brw)
 314 {
 315    const char *name = "BLEND";
 316    struct gen6_blend_state *blend;
 317    uint32_t blend_off;
 318
 319    if (brw->cc.blend_state_bo == NULL)
 320         return;
 321
 322    drm_intel_bo_map(brw->cc.blend_state_bo, GL_FALSE);
 323
 324    blend = brw->cc.blend_state_bo->virtual;
 325    blend_off = brw->cc.blend_state_bo->offset;
 326
 327    state_out(name, blend, blend_off, 0, "\n");
 328    state_out(name, blend, blend_off, 1, "\n");
 329
 330    drm_intel_bo_unmap(brw->cc.blend_state_bo);
 331
 332 }
 333
 334 static void brw_debug_prog(const char *name, drm_intel_bo *prog)
 335 {
 336    unsigned int i;
 337    uint32_t *data;
 338
 339    if (prog == NULL)
 340       return;
 341
 342    drm_intel_bo_map(prog, GL_FALSE);
 343
 344    data = prog->virtual;
 345
 346    for (i = 0; i < prog->size / 4 / 4; i++) {
 347       fprintf(stderr, "%8s: 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 348               name, (unsigned int)prog->offset + i * 4 * 4,
 349               data[i * 4], data[i * 4 + 1], data[i * 4 + 2], data[i * 4 + 3]);
 350       /* Stop at the end of the program.  It'd be nice to keep track of the actual
 351        * intended program size instead of guessing like this.
 352        */
 353       if (data[i * 4 + 0] == 0 &&
 354           data[i * 4 + 1] == 0 &&
 355           data[i * 4 + 2] == 0 &&
 356           data[i * 4 + 3] == 0)
 357          break;
 358    }
 359
 360    drm_intel_bo_unmap(prog);
 361 }
 362
 363
 364 /**
 365  * Print additional debug information associated with the batchbuffer
 366  * when DEBUG_BATCH is set.
 367  *
 368  * For 965, this means mapping the state buffers that would have been referenced
 369  * by the batchbuffer and dumping them.
 370  *
 371  * The buffer offsets printed rely on the buffer containing the last offset
 372  * it was validated at.
 373  */
 374 void brw_debug_batch(struct intel_context *intel)
 375 {
 376    struct brw_context *brw = brw_context(&intel->ctx);
 377
 378    state_struct_out("WM bind",
 379                     brw->intel.batch.bo,
 380                     brw->wm.bind_bo_offset,
 381                     4 * brw->wm.nr_surfaces);
 382    dump_wm_surface_state(brw);
 383    dump_wm_sampler_state(brw);
 384
 385    if (intel->gen < 6)
 386        state_struct_out("VS", brw->vs.state_bo, 0, sizeof(struct brw_vs_unit_state));
 387    brw_debug_prog("VS prog", brw->vs.prog_bo);
 388
 389    if (intel->gen < 6)
 390        state_struct_out("GS", brw->gs.state_bo, 0, sizeof(struct brw_gs_unit_state));
 391    brw_debug_prog("GS prog", brw->gs.prog_bo);
 392
 393    if (intel->gen < 6) {
 394        state_struct_out("SF", brw->sf.state_bo, 0, sizeof(struct brw_sf_unit_state));
 395        brw_debug_prog("SF prog", brw->sf.prog_bo);
 396    }
 397    dump_sf_viewport_state(brw);
 398
 399    if (intel->gen < 6)
 400        state_struct_out("WM", brw->wm.state_bo, 0, sizeof(struct brw_wm_unit_state));
 401    brw_debug_prog("WM prog", brw->wm.prog_bo);
 402
 403    if (intel->gen >= 6) {
 404         dump_cc_viewport_state(brw);
 405         dump_clip_viewport_state(brw);
 406         dump_depth_stencil_state(brw);
 407         dump_cc_state(brw);
 408         dump_blend_state(brw);
 409    }
 410 }