src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices, /* must come before brw_vertices */
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_gs_push_constants, /* Before gs_state */
 132    &gen6_wm_push_constants, /* Before wm_state */
 133
 134    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 135     * table upload must be last.
 136     */
 137    &brw_vs_pull_constants,
 138    &brw_vs_ubo_surfaces,
 139    &brw_gs_pull_constants,
 140    &brw_gs_ubo_surfaces,
 141    &brw_wm_pull_constants,
 142    &brw_wm_ubo_surfaces,
 143    &gen6_renderbuffer_surfaces,
 144    &brw_texture_surfaces,
 145    &gen6_sol_surface,
 146    &brw_vs_binding_table,
 147    &gen6_gs_binding_table,
 148    &brw_wm_binding_table,
 149
 150    &brw_fs_samplers,
 151    &brw_vs_samplers,
 152    &brw_gs_samplers,
 153    &gen6_sampler_state,
 154    &gen6_multisample_state,
 155
 156    &gen6_vs_state,
 157    &gen6_gs_state,
 158    &gen6_clip_state,
 159    &gen6_sf_state,
 160    &gen6_wm_state,
 161
 162    &gen6_scissor_state,
 163
 164    &gen6_binding_table_pointers,
 165
 166    &brw_depthbuffer,
 167
 168    &brw_polygon_stipple,
 169    &brw_polygon_stipple_offset,
 170
 171    &brw_line_stipple,
 172    &brw_aa_line_parameters,
 173
 174    &brw_drawing_rect,
 175
 176    &brw_indices, /* must come before brw_vertices */
 177    &brw_index_buffer,
 178    &brw_vertices,
 179 };
 180
 181 static const struct brw_tracked_state *gen7_atoms[] =
 182 {
 183    &brw_vs_prog,
 184    &brw_gs_prog,
 185    &brw_wm_prog,
 186
 187    /* Command packets: */
 188
 189    /* must do before binding table pointers, cc state ptrs */
 190    &brw_state_base_address,
 191
 192    &brw_cc_vp,
 193    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 194    &gen7_sf_clip_viewport,
 195
 196    &gen7_push_constant_space,
 197    &gen7_urb,
 198    &gen6_blend_state,           /* must do before cc unit */
 199    &gen6_color_calc_state,      /* must do before cc unit */
 200    &gen6_depth_stencil_state,   /* must do before cc unit */
 201
 202    &gen6_vs_push_constants, /* Before vs_state */
 203    &gen6_gs_push_constants, /* Before gs_state */
 204    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 205
 206    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 207     * table upload must be last.
 208     */
 209    &brw_vs_pull_constants,
 210    &brw_vs_ubo_surfaces,
 211    &brw_vs_abo_surfaces,
 212    &brw_gs_pull_constants,
 213    &brw_gs_ubo_surfaces,
 214    &brw_gs_abo_surfaces,
 215    &brw_wm_pull_constants,
 216    &brw_wm_ubo_surfaces,
 217    &brw_wm_abo_surfaces,
 218    &gen6_renderbuffer_surfaces,
 219    &brw_texture_surfaces,
 220    &brw_vs_binding_table,
 221    &brw_gs_binding_table,
 222    &brw_wm_binding_table,
 223
 224    &brw_fs_samplers,
 225    &brw_vs_samplers,
 226    &brw_gs_samplers,
 227    &gen6_multisample_state,
 228
 229    &gen7_disable_stages,
 230    &gen7_vs_state,
 231    &gen7_gs_state,
 232    &gen7_sol_state,
 233    &gen7_clip_state,
 234    &gen7_sbe_state,
 235    &gen7_sf_state,
 236    &gen7_wm_state,
 237    &gen7_ps_state,
 238
 239    &gen6_scissor_state,
 240
 241    &gen7_depthbuffer,
 242
 243    &brw_polygon_stipple,
 244    &brw_polygon_stipple_offset,
 245
 246    &brw_line_stipple,
 247    &brw_aa_line_parameters,
 248
 249    &brw_drawing_rect,
 250
 251    &brw_indices, /* must come before brw_vertices */
 252    &brw_index_buffer,
 253    &brw_vertices,
 254
 255    &haswell_cut_index,
 256 };
 257
 258 static const struct brw_tracked_state *gen8_atoms[] =
 259 {
 260    &brw_vs_prog,
 261    &brw_gs_prog,
 262    &brw_wm_prog,
 263
 264    /* Command packets: */
 265    &gen8_state_base_address,
 266
 267    &brw_cc_vp,
 268    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 269    &gen8_sf_clip_viewport,
 270
 271    &gen7_push_constant_space,
 272    &gen7_urb,
 273    &gen8_blend_state,
 274    &gen6_color_calc_state,
 275
 276    &gen6_vs_push_constants, /* Before vs_state */
 277    &gen6_gs_push_constants, /* Before gs_state */
 278    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 279
 280    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 281     * table upload must be last.
 282     */
 283    &brw_vs_pull_constants,
 284    &brw_vs_ubo_surfaces,
 285    &brw_vs_abo_surfaces,
 286    &brw_gs_pull_constants,
 287    &brw_gs_ubo_surfaces,
 288    &brw_gs_abo_surfaces,
 289    &brw_wm_pull_constants,
 290    &brw_wm_ubo_surfaces,
 291    &brw_wm_abo_surfaces,
 292    &gen6_renderbuffer_surfaces,
 293    &brw_texture_surfaces,
 294    &brw_vs_binding_table,
 295    &brw_gs_binding_table,
 296    &brw_wm_binding_table,
 297
 298    &brw_fs_samplers,
 299    &brw_vs_samplers,
 300    &brw_gs_samplers,
 301    &gen8_multisample_state,
 302
 303    &gen8_disable_stages,
 304    &gen8_vs_state,
 305    &gen8_gs_state,
 306    &gen8_sol_state,
 307    &gen6_clip_state,
 308    &gen8_raster_state,
 309    &gen8_sbe_state,
 310    &gen8_sf_state,
 311    &gen8_ps_blend,
 312    &gen8_ps_extra,
 313    &gen8_ps_state,
 314    &gen8_wm_depth_stencil,
 315    &gen8_wm_state,
 316
 317    &gen6_scissor_state,
 318
 319    &gen7_depthbuffer,
 320
 321    &brw_polygon_stipple,
 322    &brw_polygon_stipple_offset,
 323
 324    &brw_line_stipple,
 325    &brw_aa_line_parameters,
 326
 327    &brw_drawing_rect,
 328
 329    &gen8_vf_topology,
 330
 331    &brw_indices,
 332    &gen8_index_buffer,
 333    &gen8_vertices,
 334
 335    &haswell_cut_index,
 336    &gen8_pma_fix,
 337 };
 338
 339 static void
 340 brw_upload_initial_gpu_state(struct brw_context *brw)
 341 {
 342    /* On platforms with hardware contexts, we can set our initial GPU state
 343     * right away rather than doing it via state atoms.  This saves a small
 344     * amount of overhead on every draw call.
 345     */
 346    if (!brw->hw_ctx)
 347       return;
 348
 349    brw_upload_invariant_state(brw);
 350
 351    if (brw->gen >= 8) {
 352       gen8_emit_3dstate_sample_pattern(brw);
 353    }
 354 }
 355
 356 void brw_init_state( struct brw_context *brw )
 357 {
 358    struct gl_context *ctx = &brw->ctx;
 359    const struct brw_tracked_state **atoms;
 360    int num_atoms;
 361
 362    brw_init_caches(brw);
 363
 364    if (brw->gen >= 8) {
 365       atoms = gen8_atoms;
 366       num_atoms = ARRAY_SIZE(gen8_atoms);
 367    } else if (brw->gen == 7) {
 368       atoms = gen7_atoms;
 369       num_atoms = ARRAY_SIZE(gen7_atoms);
 370    } else if (brw->gen == 6) {
 371       atoms = gen6_atoms;
 372       num_atoms = ARRAY_SIZE(gen6_atoms);
 373    } else {
 374       atoms = gen4_atoms;
 375       num_atoms = ARRAY_SIZE(gen4_atoms);
 376    }
 377
 378    brw->atoms = atoms;
 379    brw->num_atoms = num_atoms;
 380
 381    while (num_atoms--) {
 382       assert((*atoms)->dirty.mesa |
 383              (*atoms)->dirty.brw |
 384              (*atoms)->dirty.cache);
 385       assert((*atoms)->emit);
 386       atoms++;
 387    }
 388
 389    brw_upload_initial_gpu_state(brw);
 390
 391    brw->state.dirty.mesa = ~0;
 392    brw->state.dirty.brw = ~0ull;
 393
 394    /* ~0 is a nonsensical value which won't match anything we program, so
 395     * the programming will take effect on the first time around.
 396     */
 397    brw->pma_stall_bits = ~0;
 398
 399    /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
 400     * dirty flags.
 401     */
 402    STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->state.dirty.brw));
 403
 404    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 405    ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
 406    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 407    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 408    ctx->DriverFlags.NewTextureBuffer = BRW_NEW_TEXTURE_BUFFER;
 409    ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 410 }
 411
 412
 413 void brw_destroy_state( struct brw_context *brw )
 414 {
 415    brw_destroy_caches(brw);
 416 }
 417
 418 /***********************************************************************
 419  */
 420
 421 static bool
 422 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 423 {
 424    return ((a->mesa & b->mesa) |
 425            (a->brw & b->brw) |
 426            (a->cache & b->cache)) != 0;
 427 }
 428
 429 static void accumulate_state( struct brw_state_flags *a,
 430                               const struct brw_state_flags *b )
 431 {
 432    a->mesa |= b->mesa;
 433    a->brw |= b->brw;
 434    a->cache |= b->cache;
 435 }
 436
 437
 438 static void xor_states( struct brw_state_flags *result,
 439                              const struct brw_state_flags *a,
 440                               const struct brw_state_flags *b )
 441 {
 442    result->mesa = a->mesa ^ b->mesa;
 443    result->brw = a->brw ^ b->brw;
 444    result->cache = a->cache ^ b->cache;
 445 }
 446
 447 struct dirty_bit_map {
 448    uint64_t bit;
 449    char *name;
 450    uint32_t count;
 451 };
 452
 453 #define DEFINE_BIT(name) {name, #name, 0}
 454
 455 static struct dirty_bit_map mesa_bits[] = {
 456    DEFINE_BIT(_NEW_MODELVIEW),
 457    DEFINE_BIT(_NEW_PROJECTION),
 458    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 459    DEFINE_BIT(_NEW_COLOR),
 460    DEFINE_BIT(_NEW_DEPTH),
 461    DEFINE_BIT(_NEW_EVAL),
 462    DEFINE_BIT(_NEW_FOG),
 463    DEFINE_BIT(_NEW_HINT),
 464    DEFINE_BIT(_NEW_LIGHT),
 465    DEFINE_BIT(_NEW_LINE),
 466    DEFINE_BIT(_NEW_PIXEL),
 467    DEFINE_BIT(_NEW_POINT),
 468    DEFINE_BIT(_NEW_POLYGON),
 469    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 470    DEFINE_BIT(_NEW_SCISSOR),
 471    DEFINE_BIT(_NEW_STENCIL),
 472    DEFINE_BIT(_NEW_TEXTURE),
 473    DEFINE_BIT(_NEW_TRANSFORM),
 474    DEFINE_BIT(_NEW_VIEWPORT),
 475    DEFINE_BIT(_NEW_ARRAY),
 476    DEFINE_BIT(_NEW_RENDERMODE),
 477    DEFINE_BIT(_NEW_BUFFERS),
 478    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 479    DEFINE_BIT(_NEW_MULTISAMPLE),
 480    DEFINE_BIT(_NEW_TRACK_MATRIX),
 481    DEFINE_BIT(_NEW_PROGRAM),
 482    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 483    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 484    DEFINE_BIT(_NEW_FRAG_CLAMP),
 485    /* Avoid sign extension problems. */
 486    {(unsigned) _NEW_VARYING_VP_INPUTS, "_NEW_VARYING_VP_INPUTS", 0},
 487    {0, 0, 0}
 488 };
 489
 490 static struct dirty_bit_map brw_bits[] = {
 491    DEFINE_BIT(BRW_NEW_URB_FENCE),
 492    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 493    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 494    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 495    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 496    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 497    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 498    DEFINE_BIT(BRW_NEW_CONTEXT),
 499    DEFINE_BIT(BRW_NEW_PSP),
 500    DEFINE_BIT(BRW_NEW_SURFACES),
 501    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 502    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 503    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 504    DEFINE_BIT(BRW_NEW_INDICES),
 505    DEFINE_BIT(BRW_NEW_VERTICES),
 506    DEFINE_BIT(BRW_NEW_BATCH),
 507    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 508    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 509    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 510    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 511    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 512    DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
 513    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 514    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 515    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 516    DEFINE_BIT(BRW_NEW_STATS_WM),
 517    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 518    DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
 519    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 520    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 521    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 522    DEFINE_BIT(BRW_NEW_NUM_SAMPLES),
 523    DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER),
 524    DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE),
 525    {0, 0, 0}
 526 };
 527
 528 static struct dirty_bit_map cache_bits[] = {
 529    DEFINE_BIT(CACHE_NEW_CC_VP),
 530    DEFINE_BIT(CACHE_NEW_WM_PROG),
 531    DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG),
 532    DEFINE_BIT(CACHE_NEW_SAMPLER),
 533    DEFINE_BIT(CACHE_NEW_SF_PROG),
 534    DEFINE_BIT(CACHE_NEW_SF_VP),
 535    DEFINE_BIT(CACHE_NEW_VS_PROG),
 536    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 537    DEFINE_BIT(CACHE_NEW_GS_PROG),
 538    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 539    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 540    {0, 0, 0}
 541 };
 542
 543
 544 static void
 545 brw_update_dirty_count(struct dirty_bit_map *bit_map, uint64_t bits)
 546 {
 547    for (int i = 0; bit_map[i].bit != 0; i++) {
 548       if (bit_map[i].bit & bits)
 549          bit_map[i].count++;
 550    }
 551 }
 552
 553 static void
 554 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 555 {
 556    for (int i = 0; bit_map[i].bit != 0; i++) {
 557       fprintf(stderr, "0x%016lx: %12d (%s)\n",
 558               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 559    }
 560 }
 561
 562 /***********************************************************************
 563  * Emit all state:
 564  */
 565 void brw_upload_state(struct brw_context *brw)
 566 {
 567    struct gl_context *ctx = &brw->ctx;
 568    struct brw_state_flags *state = &brw->state.dirty;
 569    int i;
 570    static int dirty_count = 0;
 571
 572    state->mesa |= brw->NewGLState;
 573    brw->NewGLState = 0;
 574
 575    state->brw |= ctx->NewDriverState;
 576    ctx->NewDriverState = 0;
 577
 578    if (0) {
 579       /* Always re-emit all state. */
 580       state->mesa |= ~0;
 581       state->brw |= ~0ull;
 582       state->cache |= ~0;
 583    }
 584
 585    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 586       brw->fragment_program = ctx->FragmentProgram._Current;
 587       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 588    }
 589
 590    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 591       brw->geometry_program = ctx->GeometryProgram._Current;
 592       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 593    }
 594
 595    if (brw->vertex_program != ctx->VertexProgram._Current) {
 596       brw->vertex_program = ctx->VertexProgram._Current;
 597       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 598    }
 599
 600    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 601       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 602       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 603    }
 604
 605    if (brw->num_samples != ctx->DrawBuffer->Visual.samples) {
 606       brw->num_samples = ctx->DrawBuffer->Visual.samples;
 607       brw->state.dirty.brw |= BRW_NEW_NUM_SAMPLES;
 608    }
 609
 610    if ((state->mesa | state->cache | state->brw) == 0)
 611       return;
 612
 613    if (unlikely(INTEL_DEBUG)) {
 614       /* Debug version which enforces various sanity checks on the
 615        * state flags which are generated and checked to help ensure
 616        * state atoms are ordered correctly in the list.
 617        */
 618       struct brw_state_flags examined, prev;
 619       memset(&examined, 0, sizeof(examined));
 620       prev = *state;
 621
 622       for (i = 0; i < brw->num_atoms; i++) {
 623          const struct brw_tracked_state *atom = brw->atoms[i];
 624          struct brw_state_flags generated;
 625
 626          if (check_state(state, &atom->dirty)) {
 627             atom->emit(brw);
 628          }
 629
 630          accumulate_state(&examined, &atom->dirty);
 631
 632          /* generated = (prev ^ state)
 633           * if (examined & generated)
 634           *     fail;
 635           */
 636          xor_states(&generated, &prev, state);
 637          assert(!check_state(&examined, &generated));
 638          prev = *state;
 639       }
 640    }
 641    else {
 642       for (i = 0; i < brw->num_atoms; i++) {
 643          const struct brw_tracked_state *atom = brw->atoms[i];
 644
 645          if (check_state(state, &atom->dirty)) {
 646             atom->emit(brw);
 647          }
 648       }
 649    }
 650
 651    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 652       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 653       STATIC_ASSERT(ARRAY_SIZE(cache_bits) == BRW_MAX_CACHE + 1);
 654
 655       brw_update_dirty_count(mesa_bits, state->mesa);
 656       brw_update_dirty_count(brw_bits, state->brw);
 657       brw_update_dirty_count(cache_bits, state->cache);
 658       if (dirty_count++ % 1000 == 0) {
 659          brw_print_dirty_count(mesa_bits);
 660          brw_print_dirty_count(brw_bits);
 661          brw_print_dirty_count(cache_bits);
 662          fprintf(stderr, "\n");
 663       }
 664    }
 665 }
 666
 667
 668 /**
 669  * Clear dirty bits to account for the fact that the state emitted by
 670  * brw_upload_state() has been committed to the hardware.  This is a separate
 671  * call from brw_upload_state() because it's possible that after the call to
 672  * brw_upload_state(), we will discover that we've run out of aperture space,
 673  * and need to rewind the batch buffer to the state it had before the
 674  * brw_upload_state() call.
 675  */
 676 void
 677 brw_clear_dirty_bits(struct brw_context *brw)
 678 {
 679    struct brw_state_flags *state = &brw->state.dirty;
 680    memset(state, 0, sizeof(*state));
 681 }