src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  67     * table upload must be last.
  68     */
  69    &brw_vs_pull_constants,
  70    &brw_wm_pull_constants,
  71    &brw_renderbuffer_surfaces,
  72    &brw_texture_surfaces,
  73    &brw_vs_binding_table,
  74    &brw_wm_binding_table,
  75
  76    &brw_samplers,
  77
  78    /* These set up state for brw_psp_urb_cbs */
  79    &brw_wm_unit,
  80    &brw_sf_vp,
  81    &brw_sf_unit,
  82    &brw_vs_unit,                /* always required, enabled or not */
  83    &brw_clip_unit,
  84    &brw_gs_unit,
  85
  86    /* Command packets:
  87     */
  88    &brw_invariant_state,
  89    &brw_state_base_address,
  90
  91    &brw_binding_table_pointers,
  92    &brw_blend_constant_color,
  93
  94    &brw_depthbuffer,
  95
  96    &brw_polygon_stipple,
  97    &brw_polygon_stipple_offset,
  98
  99    &brw_line_stipple,
 100    &brw_aa_line_parameters,
 101
 102    &brw_psp_urb_cbs,
 103
 104    &brw_drawing_rect,
 105    &brw_indices,
 106    &brw_index_buffer,
 107    &brw_vertices,
 108
 109    &brw_constant_buffer
 110 };
 111
 112 static const struct brw_tracked_state *gen6_atoms[] =
 113 {
 114    &brw_check_fallback,
 115
 116    &brw_wm_input_sizes,
 117    &brw_vs_prog, /* must do before state base address */
 118    &brw_gs_prog, /* must do before state base address */
 119    &brw_wm_prog, /* must do before state base address */
 120
 121    &gen6_clip_vp,
 122    &gen6_sf_vp,
 123
 124    /* Command packets: */
 125    &brw_invariant_state,
 126
 127    /* must do before binding table pointers, cc state ptrs */
 128    &brw_state_base_address,
 129
 130    &brw_cc_vp,
 131    &gen6_viewport_state,        /* must do after *_vp stages */
 132
 133    &gen6_urb,
 134    &gen6_blend_state,           /* must do before cc unit */
 135    &gen6_color_calc_state,      /* must do before cc unit */
 136    &gen6_depth_stencil_state,   /* must do before cc unit */
 137    &gen6_cc_state_pointers,
 138
 139    &gen6_vs_push_constants, /* Before vs_state */
 140    &gen6_wm_push_constants, /* Before wm_state */
 141
 142    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 143     * table upload must be last.
 144     */
 145    &brw_vs_pull_constants,
 146    &brw_wm_pull_constants,
 147    &gen6_renderbuffer_surfaces,
 148    &brw_texture_surfaces,
 149    &gen6_sol_surface,
 150    &brw_vs_binding_table,
 151    &gen6_gs_binding_table,
 152    &brw_wm_binding_table,
 153
 154    &brw_samplers,
 155    &gen6_sampler_state,
 156    &gen6_multisample_state,
 157
 158    &gen6_vs_state,
 159    &gen6_gs_state,
 160    &gen6_clip_state,
 161    &gen6_sf_state,
 162    &gen6_wm_state,
 163
 164    &gen6_scissor_state,
 165
 166    &gen6_binding_table_pointers,
 167
 168    &brw_depthbuffer,
 169
 170    &brw_polygon_stipple,
 171    &brw_polygon_stipple_offset,
 172
 173    &brw_line_stipple,
 174    &brw_aa_line_parameters,
 175
 176    &brw_drawing_rect,
 177
 178    &gen6_sol_indices,
 179    &brw_indices,
 180    &brw_index_buffer,
 181    &brw_vertices,
 182 };
 183
 184 const struct brw_tracked_state *gen7_atoms[] =
 185 {
 186    &brw_check_fallback,
 187
 188    &brw_wm_input_sizes,
 189    &brw_vs_prog,
 190    &brw_wm_prog,
 191
 192    /* Command packets: */
 193    &brw_invariant_state,
 194    &gen7_push_constant_alloc,
 195
 196    /* must do before binding table pointers, cc state ptrs */
 197    &brw_state_base_address,
 198
 199    &brw_cc_vp,
 200    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 201    &gen7_sf_clip_viewport,
 202
 203    &gen7_urb,
 204    &gen6_blend_state,           /* must do before cc unit */
 205    &gen6_color_calc_state,      /* must do before cc unit */
 206    &gen6_depth_stencil_state,   /* must do before cc unit */
 207    &gen7_blend_state_pointer,
 208    &gen7_cc_state_pointer,
 209    &gen7_depth_stencil_state_pointer,
 210
 211    &gen6_vs_push_constants, /* Before vs_state */
 212    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 213
 214    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 215     * table upload must be last.
 216     */
 217    &brw_vs_pull_constants,
 218    &brw_wm_pull_constants,
 219    &gen6_renderbuffer_surfaces,
 220    &brw_texture_surfaces,
 221    &brw_vs_binding_table,
 222    &brw_wm_binding_table,
 223
 224    &gen7_samplers,
 225    &gen6_multisample_state,
 226
 227    &gen7_disable_stages,
 228    &gen7_vs_state,
 229    &gen7_sol_state,
 230    &gen7_clip_state,
 231    &gen7_sbe_state,
 232    &gen7_sf_state,
 233    &gen7_wm_state,
 234    &gen7_ps_state,
 235
 236    &gen6_scissor_state,
 237
 238    &gen7_depthbuffer,
 239
 240    &brw_polygon_stipple,
 241    &brw_polygon_stipple_offset,
 242
 243    &brw_line_stipple,
 244    &brw_aa_line_parameters,
 245
 246    &brw_drawing_rect,
 247
 248    &brw_indices,
 249    &brw_index_buffer,
 250    &brw_vertices,
 251 };
 252
 253
 254 void brw_init_state( struct brw_context *brw )
 255 {
 256    const struct brw_tracked_state **atoms;
 257    int num_atoms;
 258
 259    brw_init_caches(brw);
 260
 261    if (brw->intel.gen >= 7) {
 262       atoms = gen7_atoms;
 263       num_atoms = ARRAY_SIZE(gen7_atoms);
 264    } else if (brw->intel.gen == 6) {
 265       atoms = gen6_atoms;
 266       num_atoms = ARRAY_SIZE(gen6_atoms);
 267    } else {
 268       atoms = gen4_atoms;
 269       num_atoms = ARRAY_SIZE(gen4_atoms);
 270    }
 271
 272    brw->atoms = atoms;
 273    brw->num_atoms = num_atoms;
 274
 275    while (num_atoms--) {
 276       assert((*atoms)->dirty.mesa |
 277              (*atoms)->dirty.brw |
 278              (*atoms)->dirty.cache);
 279       assert((*atoms)->emit);
 280       atoms++;
 281    }
 282 }
 283
 284
 285 void brw_destroy_state( struct brw_context *brw )
 286 {
 287    brw_destroy_caches(brw);
 288 }
 289
 290 /***********************************************************************
 291  */
 292
 293 static GLuint check_state( const struct brw_state_flags *a,
 294                            const struct brw_state_flags *b )
 295 {
 296    return ((a->mesa & b->mesa) |
 297            (a->brw & b->brw) |
 298            (a->cache & b->cache)) != 0;
 299 }
 300
 301 static void accumulate_state( struct brw_state_flags *a,
 302                               const struct brw_state_flags *b )
 303 {
 304    a->mesa |= b->mesa;
 305    a->brw |= b->brw;
 306    a->cache |= b->cache;
 307 }
 308
 309
 310 static void xor_states( struct brw_state_flags *result,
 311                              const struct brw_state_flags *a,
 312                               const struct brw_state_flags *b )
 313 {
 314    result->mesa = a->mesa ^ b->mesa;
 315    result->brw = a->brw ^ b->brw;
 316    result->cache = a->cache ^ b->cache;
 317 }
 318
 319 struct dirty_bit_map {
 320    uint32_t bit;
 321    char *name;
 322    uint32_t count;
 323 };
 324
 325 #define DEFINE_BIT(name) {name, #name, 0}
 326
 327 static struct dirty_bit_map mesa_bits[] = {
 328    DEFINE_BIT(_NEW_MODELVIEW),
 329    DEFINE_BIT(_NEW_PROJECTION),
 330    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 331    DEFINE_BIT(_NEW_COLOR),
 332    DEFINE_BIT(_NEW_DEPTH),
 333    DEFINE_BIT(_NEW_EVAL),
 334    DEFINE_BIT(_NEW_FOG),
 335    DEFINE_BIT(_NEW_HINT),
 336    DEFINE_BIT(_NEW_LIGHT),
 337    DEFINE_BIT(_NEW_LINE),
 338    DEFINE_BIT(_NEW_PIXEL),
 339    DEFINE_BIT(_NEW_POINT),
 340    DEFINE_BIT(_NEW_POLYGON),
 341    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 342    DEFINE_BIT(_NEW_SCISSOR),
 343    DEFINE_BIT(_NEW_STENCIL),
 344    DEFINE_BIT(_NEW_TEXTURE),
 345    DEFINE_BIT(_NEW_TRANSFORM),
 346    DEFINE_BIT(_NEW_VIEWPORT),
 347    DEFINE_BIT(_NEW_PACKUNPACK),
 348    DEFINE_BIT(_NEW_ARRAY),
 349    DEFINE_BIT(_NEW_RENDERMODE),
 350    DEFINE_BIT(_NEW_BUFFERS),
 351    DEFINE_BIT(_NEW_MULTISAMPLE),
 352    DEFINE_BIT(_NEW_TRACK_MATRIX),
 353    DEFINE_BIT(_NEW_PROGRAM),
 354    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 355    {0, 0, 0}
 356 };
 357
 358 static struct dirty_bit_map brw_bits[] = {
 359    DEFINE_BIT(BRW_NEW_URB_FENCE),
 360    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 361    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 362    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 363    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 364    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 365    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 366    DEFINE_BIT(BRW_NEW_CONTEXT),
 367    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 368    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 369    DEFINE_BIT(BRW_NEW_PSP),
 370    DEFINE_BIT(BRW_NEW_SURFACES),
 371    DEFINE_BIT(BRW_NEW_INDICES),
 372    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 373    DEFINE_BIT(BRW_NEW_VERTICES),
 374    DEFINE_BIT(BRW_NEW_BATCH),
 375    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 376    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 377    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 378    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 379    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 380    {0, 0, 0}
 381 };
 382
 383 static struct dirty_bit_map cache_bits[] = {
 384    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 385    DEFINE_BIT(CACHE_NEW_CC_VP),
 386    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 387    DEFINE_BIT(CACHE_NEW_WM_PROG),
 388    DEFINE_BIT(CACHE_NEW_SAMPLER),
 389    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 390    DEFINE_BIT(CACHE_NEW_SF_PROG),
 391    DEFINE_BIT(CACHE_NEW_SF_VP),
 392    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 393    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 394    DEFINE_BIT(CACHE_NEW_VS_PROG),
 395    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 396    DEFINE_BIT(CACHE_NEW_GS_PROG),
 397    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 398    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 399    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 400    {0, 0, 0}
 401 };
 402
 403
 404 static void
 405 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 406 {
 407    int i;
 408
 409    for (i = 0; i < 32; i++) {
 410       if (bit_map[i].bit == 0)
 411          return;
 412
 413       if (bit_map[i].bit & bits)
 414          bit_map[i].count++;
 415    }
 416 }
 417
 418 static void
 419 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 420 {
 421    int i;
 422
 423    for (i = 0; i < 32; i++) {
 424       if (bit_map[i].bit == 0)
 425          return;
 426
 427       fprintf(stderr, "0x%08x: %12d (%s)\n",
 428               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 429    }
 430 }
 431
 432 /***********************************************************************
 433  * Emit all state:
 434  */
 435 void brw_upload_state(struct brw_context *brw)
 436 {
 437    struct gl_context *ctx = &brw->intel.ctx;
 438    struct intel_context *intel = &brw->intel;
 439    struct brw_state_flags *state = &brw->state.dirty;
 440    int i;
 441    static int dirty_count = 0;
 442
 443    state->mesa |= brw->intel.NewGLState;
 444    brw->intel.NewGLState = 0;
 445
 446    if (brw->emit_state_always) {
 447       state->mesa |= ~0;
 448       state->brw |= ~0;
 449       state->cache |= ~0;
 450    }
 451
 452    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 453       brw->fragment_program = ctx->FragmentProgram._Current;
 454       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 455    }
 456
 457    if (brw->vertex_program != ctx->VertexProgram._Current) {
 458       brw->vertex_program = ctx->VertexProgram._Current;
 459       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 460    }
 461
 462    if ((state->mesa | state->cache | state->brw) == 0)
 463       return;
 464
 465    brw->intel.Fallback = false; /* boolean, not bitfield */
 466
 467    intel_check_front_buffer_rendering(intel);
 468
 469    if (unlikely(INTEL_DEBUG)) {
 470       /* Debug version which enforces various sanity checks on the
 471        * state flags which are generated and checked to help ensure
 472        * state atoms are ordered correctly in the list.
 473        */
 474       struct brw_state_flags examined, prev;
 475       memset(&examined, 0, sizeof(examined));
 476       prev = *state;
 477
 478       for (i = 0; i < brw->num_atoms; i++) {
 479          const struct brw_tracked_state *atom = brw->atoms[i];
 480          struct brw_state_flags generated;
 481
 482          if (brw->intel.Fallback)
 483             break;
 484
 485          if (check_state(state, &atom->dirty)) {
 486             atom->emit(brw);
 487          }
 488
 489          accumulate_state(&examined, &atom->dirty);
 490
 491          /* generated = (prev ^ state)
 492           * if (examined & generated)
 493           *     fail;
 494           */
 495          xor_states(&generated, &prev, state);
 496          assert(!check_state(&examined, &generated));
 497          prev = *state;
 498       }
 499    }
 500    else {
 501       for (i = 0; i < brw->num_atoms; i++) {
 502          const struct brw_tracked_state *atom = brw->atoms[i];
 503
 504          if (brw->intel.Fallback)
 505             break;
 506
 507          if (check_state(state, &atom->dirty)) {
 508             atom->emit(brw);
 509          }
 510       }
 511    }
 512
 513    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 514       brw_update_dirty_count(mesa_bits, state->mesa);
 515       brw_update_dirty_count(brw_bits, state->brw);
 516       brw_update_dirty_count(cache_bits, state->cache);
 517       if (dirty_count++ % 1000 == 0) {
 518          brw_print_dirty_count(mesa_bits, state->mesa);
 519          brw_print_dirty_count(brw_bits, state->brw);
 520          brw_print_dirty_count(cache_bits, state->cache);
 521          fprintf(stderr, "\n");
 522       }
 523    }
 524
 525    if (!brw->intel.Fallback)
 526       memset(state, 0, sizeof(*state));
 527 }