src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39 #include "brw_vs.h"
  40 #include "brw_ff_gs.h"
  41 #include "brw_gs.h"
  42 #include "brw_wm.h"
  43 #include "brw_cs.h"
  44 #include "main/framebuffer.h"
  45
  46 static const struct brw_tracked_state *gen4_atoms[] =
  47 {
  48    &brw_interpolation_map,
  49
  50    &brw_clip_prog, /* must do before state base address */
  51    &brw_sf_prog, /* must do before state base address */
  52
  53    /* Once all the programs are done, we know how large urb entry
  54     * sizes need to be and can decide if we need to change the urb
  55     * layout.
  56     */
  57    &brw_curbe_offsets,
  58    &brw_recalculate_urb_fence,
  59
  60    &brw_cc_vp,
  61    &brw_cc_unit,
  62
  63    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  64     * table upload must be last.
  65     */
  66    &brw_vs_pull_constants,
  67    &brw_wm_pull_constants,
  68    &brw_renderbuffer_surfaces,
  69    &brw_texture_surfaces,
  70    &brw_vs_binding_table,
  71    &brw_wm_binding_table,
  72
  73    &brw_fs_samplers,
  74    &brw_vs_samplers,
  75
  76    /* These set up state for brw_psp_urb_cbs */
  77    &brw_wm_unit,
  78    &brw_sf_vp,
  79    &brw_sf_unit,
  80    &brw_vs_unit,                /* always required, enabled or not */
  81    &brw_clip_unit,
  82    &brw_gs_unit,
  83
  84    /* Command packets:
  85     */
  86    &brw_invariant_state,
  87    &brw_state_base_address,
  88
  89    &brw_binding_table_pointers,
  90    &brw_blend_constant_color,
  91
  92    &brw_depthbuffer,
  93
  94    &brw_polygon_stipple,
  95    &brw_polygon_stipple_offset,
  96
  97    &brw_line_stipple,
  98    &brw_aa_line_parameters,
  99
 100    &brw_psp_urb_cbs,
 101
 102    &brw_drawing_rect,
 103    &brw_indices, /* must come before brw_vertices */
 104    &brw_index_buffer,
 105    &brw_vertices,
 106
 107    &brw_constant_buffer
 108 };
 109
 110 static const struct brw_tracked_state *gen6_atoms[] =
 111 {
 112    &gen6_clip_vp,
 113    &gen6_sf_vp,
 114
 115    /* Command packets: */
 116
 117    /* must do before binding table pointers, cc state ptrs */
 118    &brw_state_base_address,
 119
 120    &brw_cc_vp,
 121    &gen6_viewport_state,        /* must do after *_vp stages */
 122
 123    &gen6_urb,
 124    &gen6_blend_state,           /* must do before cc unit */
 125    &gen6_color_calc_state,      /* must do before cc unit */
 126    &gen6_depth_stencil_state,   /* must do before cc unit */
 127
 128    &gen6_vs_push_constants, /* Before vs_state */
 129    &gen6_gs_push_constants, /* Before gs_state */
 130    &gen6_wm_push_constants, /* Before wm_state */
 131
 132    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 133     * table upload must be last.
 134     */
 135    &brw_vs_pull_constants,
 136    &brw_vs_ubo_surfaces,
 137    &brw_gs_pull_constants,
 138    &brw_gs_ubo_surfaces,
 139    &brw_wm_pull_constants,
 140    &brw_wm_ubo_surfaces,
 141    &gen6_renderbuffer_surfaces,
 142    &brw_texture_surfaces,
 143    &gen6_sol_surface,
 144    &brw_vs_binding_table,
 145    &gen6_gs_binding_table,
 146    &brw_wm_binding_table,
 147
 148    &brw_fs_samplers,
 149    &brw_vs_samplers,
 150    &brw_gs_samplers,
 151    &gen6_sampler_state,
 152    &gen6_multisample_state,
 153
 154    &gen6_vs_state,
 155    &gen6_gs_state,
 156    &gen6_clip_state,
 157    &gen6_sf_state,
 158    &gen6_wm_state,
 159
 160    &gen6_scissor_state,
 161
 162    &gen6_binding_table_pointers,
 163
 164    &brw_depthbuffer,
 165
 166    &brw_polygon_stipple,
 167    &brw_polygon_stipple_offset,
 168
 169    &brw_line_stipple,
 170    &brw_aa_line_parameters,
 171
 172    &brw_drawing_rect,
 173
 174    &brw_indices, /* must come before brw_vertices */
 175    &brw_index_buffer,
 176    &brw_vertices,
 177 };
 178
 179 static const struct brw_tracked_state *gen7_render_atoms[] =
 180 {
 181    /* Command packets: */
 182
 183    /* must do before binding table pointers, cc state ptrs */
 184    &brw_state_base_address,
 185
 186    &brw_cc_vp,
 187    &gen7_sf_clip_viewport,
 188
 189    &gen7_push_constant_space,
 190    &gen7_urb,
 191    &gen6_blend_state,           /* must do before cc unit */
 192    &gen6_color_calc_state,      /* must do before cc unit */
 193    &gen6_depth_stencil_state,   /* must do before cc unit */
 194
 195    &gen7_hw_binding_tables, /* Enable hw-generated binding tables for Haswell */
 196
 197    &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
 198    &brw_gs_image_surfaces, /* Before gs push/pull constants and binding table */
 199    &brw_wm_image_surfaces, /* Before wm push/pull constants and binding table */
 200
 201    &gen6_vs_push_constants, /* Before vs_state */
 202    &gen6_gs_push_constants, /* Before gs_state */
 203    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 204
 205    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 206     * table upload must be last.
 207     */
 208    &brw_vs_pull_constants,
 209    &brw_vs_ubo_surfaces,
 210    &brw_vs_abo_surfaces,
 211    &brw_gs_pull_constants,
 212    &brw_gs_ubo_surfaces,
 213    &brw_gs_abo_surfaces,
 214    &brw_wm_pull_constants,
 215    &brw_wm_ubo_surfaces,
 216    &brw_wm_abo_surfaces,
 217    &gen6_renderbuffer_surfaces,
 218    &brw_texture_surfaces,
 219    &brw_vs_binding_table,
 220    &brw_gs_binding_table,
 221    &brw_wm_binding_table,
 222
 223    &brw_fs_samplers,
 224    &brw_vs_samplers,
 225    &brw_gs_samplers,
 226    &gen6_multisample_state,
 227
 228    &gen7_disable_stages,
 229    &gen7_vs_state,
 230    &gen7_gs_state,
 231    &gen7_sol_state,
 232    &gen7_clip_state,
 233    &gen7_sbe_state,
 234    &gen7_sf_state,
 235    &gen7_wm_state,
 236    &gen7_ps_state,
 237
 238    &gen6_scissor_state,
 239
 240    &gen7_depthbuffer,
 241
 242    &brw_polygon_stipple,
 243    &brw_polygon_stipple_offset,
 244
 245    &brw_line_stipple,
 246    &brw_aa_line_parameters,
 247
 248    &brw_drawing_rect,
 249
 250    &brw_indices, /* must come before brw_vertices */
 251    &brw_index_buffer,
 252    &brw_vertices,
 253
 254    &haswell_cut_index,
 255 };
 256
 257 static const struct brw_tracked_state *gen7_compute_atoms[] =
 258 {
 259    &brw_state_base_address,
 260    &brw_cs_image_surfaces,
 261    &gen7_cs_push_constants,
 262    &brw_cs_abo_surfaces,
 263    &brw_texture_surfaces,
 264    &brw_cs_state,
 265 };
 266
 267 static const struct brw_tracked_state *gen8_render_atoms[] =
 268 {
 269    /* Command packets: */
 270    &gen8_state_base_address,
 271
 272    &brw_cc_vp,
 273    &gen8_sf_clip_viewport,
 274
 275    &gen7_push_constant_space,
 276    &gen7_urb,
 277    &gen8_blend_state,
 278    &gen6_color_calc_state,
 279
 280    &gen7_hw_binding_tables, /* Enable hw-generated binding tables for Broadwell */
 281
 282    &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
 283    &brw_gs_image_surfaces, /* Before gs push/pull constants and binding table */
 284    &brw_wm_image_surfaces, /* Before wm push/pull constants and binding table */
 285
 286    &gen6_vs_push_constants, /* Before vs_state */
 287    &gen6_gs_push_constants, /* Before gs_state */
 288    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 289
 290    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 291     * table upload must be last.
 292     */
 293    &brw_vs_pull_constants,
 294    &brw_vs_ubo_surfaces,
 295    &brw_vs_abo_surfaces,
 296    &brw_gs_pull_constants,
 297    &brw_gs_ubo_surfaces,
 298    &brw_gs_abo_surfaces,
 299    &brw_wm_pull_constants,
 300    &brw_wm_ubo_surfaces,
 301    &brw_wm_abo_surfaces,
 302    &gen6_renderbuffer_surfaces,
 303    &brw_texture_surfaces,
 304    &brw_vs_binding_table,
 305    &brw_gs_binding_table,
 306    &brw_wm_binding_table,
 307
 308    &brw_fs_samplers,
 309    &brw_vs_samplers,
 310    &brw_gs_samplers,
 311    &gen8_multisample_state,
 312
 313    &gen8_disable_stages,
 314    &gen8_vs_state,
 315    &gen8_gs_state,
 316    &gen8_sol_state,
 317    &gen6_clip_state,
 318    &gen8_raster_state,
 319    &gen8_sbe_state,
 320    &gen8_sf_state,
 321    &gen8_ps_blend,
 322    &gen8_ps_extra,
 323    &gen8_ps_state,
 324    &gen8_wm_depth_stencil,
 325    &gen8_wm_state,
 326
 327    &gen6_scissor_state,
 328
 329    &gen7_depthbuffer,
 330
 331    &brw_polygon_stipple,
 332    &brw_polygon_stipple_offset,
 333
 334    &brw_line_stipple,
 335    &brw_aa_line_parameters,
 336
 337    &brw_drawing_rect,
 338
 339    &gen8_vf_topology,
 340
 341    &brw_indices,
 342    &gen8_index_buffer,
 343    &gen8_vertices,
 344
 345    &haswell_cut_index,
 346    &gen8_pma_fix,
 347 };
 348
 349 static const struct brw_tracked_state *gen8_compute_atoms[] =
 350 {
 351    &gen8_state_base_address,
 352    &brw_cs_image_surfaces,
 353    &gen7_cs_push_constants,
 354    &brw_cs_abo_surfaces,
 355    &brw_texture_surfaces,
 356    &brw_cs_state,
 357 };
 358
 359 static void
 360 brw_upload_initial_gpu_state(struct brw_context *brw)
 361 {
 362    /* On platforms with hardware contexts, we can set our initial GPU state
 363     * right away rather than doing it via state atoms.  This saves a small
 364     * amount of overhead on every draw call.
 365     */
 366    if (!brw->hw_ctx)
 367       return;
 368
 369    if (brw->gen == 6)
 370       brw_emit_post_sync_nonzero_flush(brw);
 371
 372    brw_upload_invariant_state(brw);
 373
 374    /* Recommended optimization for Victim Cache eviction in pixel backend. */
 375    if (brw->gen >= 9) {
 376       BEGIN_BATCH(3);
 377       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 378       OUT_BATCH(GEN7_CACHE_MODE_1);
 379       OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) |
 380                 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
 381       ADVANCE_BATCH();
 382    }
 383
 384    if (brw->gen >= 8) {
 385       gen8_emit_3dstate_sample_pattern(brw);
 386    }
 387 }
 388
 389 static inline const struct brw_tracked_state *
 390 brw_get_pipeline_atoms(struct brw_context *brw,
 391                        enum brw_pipeline pipeline)
 392 {
 393    switch (pipeline) {
 394    case BRW_RENDER_PIPELINE:
 395       return brw->render_atoms;
 396    case BRW_COMPUTE_PIPELINE:
 397       return brw->compute_atoms;
 398    default:
 399       STATIC_ASSERT(BRW_NUM_PIPELINES == 2);
 400       unreachable("Unsupported pipeline");
 401       return NULL;
 402    }
 403 }
 404
 405 static void
 406 brw_copy_pipeline_atoms(struct brw_context *brw,
 407                         enum brw_pipeline pipeline,
 408                         const struct brw_tracked_state **atoms,
 409                         int num_atoms)
 410 {
 411    /* This is to work around brw_context::atoms being declared const.  We want
 412     * it to be const, but it needs to be initialized somehow!
 413     */
 414    struct brw_tracked_state *context_atoms =
 415       (struct brw_tracked_state *) brw_get_pipeline_atoms(brw, pipeline);
 416
 417    for (int i = 0; i < num_atoms; i++) {
 418       context_atoms[i] = *atoms[i];
 419       assert(context_atoms[i].dirty.mesa | context_atoms[i].dirty.brw);
 420       assert(context_atoms[i].emit);
 421    }
 422
 423    brw->num_atoms[pipeline] = num_atoms;
 424 }
 425
 426 void brw_init_state( struct brw_context *brw )
 427 {
 428    struct gl_context *ctx = &brw->ctx;
 429
 430    /* Force the first brw_select_pipeline to emit pipeline select */
 431    brw->last_pipeline = BRW_NUM_PIPELINES;
 432
 433    STATIC_ASSERT(ARRAY_SIZE(gen4_atoms) <= ARRAY_SIZE(brw->render_atoms));
 434    STATIC_ASSERT(ARRAY_SIZE(gen6_atoms) <= ARRAY_SIZE(brw->render_atoms));
 435    STATIC_ASSERT(ARRAY_SIZE(gen7_render_atoms) <=
 436                  ARRAY_SIZE(brw->render_atoms));
 437    STATIC_ASSERT(ARRAY_SIZE(gen8_render_atoms) <=
 438                  ARRAY_SIZE(brw->render_atoms));
 439    STATIC_ASSERT(ARRAY_SIZE(gen7_compute_atoms) <=
 440                  ARRAY_SIZE(brw->compute_atoms));
 441    STATIC_ASSERT(ARRAY_SIZE(gen8_compute_atoms) <=
 442                  ARRAY_SIZE(brw->compute_atoms));
 443
 444    brw_init_caches(brw);
 445
 446    if (brw->gen >= 8) {
 447       brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
 448                               gen8_render_atoms,
 449                               ARRAY_SIZE(gen8_render_atoms));
 450       brw_copy_pipeline_atoms(brw, BRW_COMPUTE_PIPELINE,
 451                               gen8_compute_atoms,
 452                               ARRAY_SIZE(gen8_compute_atoms));
 453    } else if (brw->gen == 7) {
 454       brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
 455                               gen7_render_atoms,
 456                               ARRAY_SIZE(gen7_render_atoms));
 457       brw_copy_pipeline_atoms(brw, BRW_COMPUTE_PIPELINE,
 458                               gen7_compute_atoms,
 459                               ARRAY_SIZE(gen7_compute_atoms));
 460    } else if (brw->gen == 6) {
 461       brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
 462                               gen6_atoms, ARRAY_SIZE(gen6_atoms));
 463    } else {
 464       brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
 465                               gen4_atoms, ARRAY_SIZE(gen4_atoms));
 466    }
 467
 468    brw_upload_initial_gpu_state(brw);
 469
 470    brw->NewGLState = ~0;
 471    brw->ctx.NewDriverState = ~0ull;
 472
 473    /* ~0 is a nonsensical value which won't match anything we program, so
 474     * the programming will take effect on the first time around.
 475     */
 476    brw->pma_stall_bits = ~0;
 477
 478    /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
 479     * dirty flags.
 480     */
 481    STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->ctx.NewDriverState));
 482
 483    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 484    ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
 485    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 486    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 487    ctx->DriverFlags.NewTextureBuffer = BRW_NEW_TEXTURE_BUFFER;
 488    ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 489    ctx->DriverFlags.NewImageUnits = BRW_NEW_IMAGE_UNITS;
 490 }
 491
 492
 493 void brw_destroy_state( struct brw_context *brw )
 494 {
 495    brw_destroy_caches(brw);
 496 }
 497
 498 /***********************************************************************
 499  */
 500
 501 static bool
 502 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 503 {
 504    return ((a->mesa & b->mesa) | (a->brw & b->brw)) != 0;
 505 }
 506
 507 static void accumulate_state( struct brw_state_flags *a,
 508                               const struct brw_state_flags *b )
 509 {
 510    a->mesa |= b->mesa;
 511    a->brw |= b->brw;
 512 }
 513
 514
 515 static void xor_states( struct brw_state_flags *result,
 516                              const struct brw_state_flags *a,
 517                               const struct brw_state_flags *b )
 518 {
 519    result->mesa = a->mesa ^ b->mesa;
 520    result->brw = a->brw ^ b->brw;
 521 }
 522
 523 struct dirty_bit_map {
 524    uint64_t bit;
 525    char *name;
 526    uint32_t count;
 527 };
 528
 529 #define DEFINE_BIT(name) {name, #name, 0}
 530
 531 static struct dirty_bit_map mesa_bits[] = {
 532    DEFINE_BIT(_NEW_MODELVIEW),
 533    DEFINE_BIT(_NEW_PROJECTION),
 534    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 535    DEFINE_BIT(_NEW_COLOR),
 536    DEFINE_BIT(_NEW_DEPTH),
 537    DEFINE_BIT(_NEW_EVAL),
 538    DEFINE_BIT(_NEW_FOG),
 539    DEFINE_BIT(_NEW_HINT),
 540    DEFINE_BIT(_NEW_LIGHT),
 541    DEFINE_BIT(_NEW_LINE),
 542    DEFINE_BIT(_NEW_PIXEL),
 543    DEFINE_BIT(_NEW_POINT),
 544    DEFINE_BIT(_NEW_POLYGON),
 545    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 546    DEFINE_BIT(_NEW_SCISSOR),
 547    DEFINE_BIT(_NEW_STENCIL),
 548    DEFINE_BIT(_NEW_TEXTURE),
 549    DEFINE_BIT(_NEW_TRANSFORM),
 550    DEFINE_BIT(_NEW_VIEWPORT),
 551    DEFINE_BIT(_NEW_ARRAY),
 552    DEFINE_BIT(_NEW_RENDERMODE),
 553    DEFINE_BIT(_NEW_BUFFERS),
 554    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 555    DEFINE_BIT(_NEW_MULTISAMPLE),
 556    DEFINE_BIT(_NEW_TRACK_MATRIX),
 557    DEFINE_BIT(_NEW_PROGRAM),
 558    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 559    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 560    DEFINE_BIT(_NEW_FRAG_CLAMP),
 561    /* Avoid sign extension problems. */
 562    {(unsigned) _NEW_VARYING_VP_INPUTS, "_NEW_VARYING_VP_INPUTS", 0},
 563    {0, 0, 0}
 564 };
 565
 566 static struct dirty_bit_map brw_bits[] = {
 567    DEFINE_BIT(BRW_NEW_FS_PROG_DATA),
 568    DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA),
 569    DEFINE_BIT(BRW_NEW_SF_PROG_DATA),
 570    DEFINE_BIT(BRW_NEW_VS_PROG_DATA),
 571    DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA),
 572    DEFINE_BIT(BRW_NEW_GS_PROG_DATA),
 573    DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA),
 574    DEFINE_BIT(BRW_NEW_CS_PROG_DATA),
 575    DEFINE_BIT(BRW_NEW_URB_FENCE),
 576    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 577    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 578    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 579    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 580    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 581    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 582    DEFINE_BIT(BRW_NEW_CONTEXT),
 583    DEFINE_BIT(BRW_NEW_PSP),
 584    DEFINE_BIT(BRW_NEW_SURFACES),
 585    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 586    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 587    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 588    DEFINE_BIT(BRW_NEW_INDICES),
 589    DEFINE_BIT(BRW_NEW_VERTICES),
 590    DEFINE_BIT(BRW_NEW_BATCH),
 591    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 592    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 593    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 594    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 595    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 596    DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
 597    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 598    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 599    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 600    DEFINE_BIT(BRW_NEW_STATS_WM),
 601    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 602    DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
 603    DEFINE_BIT(BRW_NEW_IMAGE_UNITS),
 604    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 605    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 606    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 607    DEFINE_BIT(BRW_NEW_NUM_SAMPLES),
 608    DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER),
 609    DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE),
 610    DEFINE_BIT(BRW_NEW_CC_VP),
 611    DEFINE_BIT(BRW_NEW_SF_VP),
 612    DEFINE_BIT(BRW_NEW_CLIP_VP),
 613    DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE),
 614    DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS),
 615    DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM),
 616    {0, 0, 0}
 617 };
 618
 619 static void
 620 brw_update_dirty_count(struct dirty_bit_map *bit_map, uint64_t bits)
 621 {
 622    for (int i = 0; bit_map[i].bit != 0; i++) {
 623       if (bit_map[i].bit & bits)
 624          bit_map[i].count++;
 625    }
 626 }
 627
 628 static void
 629 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 630 {
 631    for (int i = 0; bit_map[i].bit != 0; i++) {
 632       if (bit_map[i].count > 1) {
 633          fprintf(stderr, "0x%016lx: %12d (%s)\n",
 634                  bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 635       }
 636    }
 637 }
 638
 639 static inline void
 640 brw_upload_programs(struct brw_context *brw,
 641                     enum brw_pipeline pipeline)
 642 {
 643    if (pipeline == BRW_RENDER_PIPELINE) {
 644       brw_upload_vs_prog(brw);
 645
 646       if (brw->gen < 6)
 647          brw_upload_ff_gs_prog(brw);
 648       else
 649          brw_upload_gs_prog(brw);
 650
 651       brw_upload_wm_prog(brw);
 652    } else if (pipeline == BRW_COMPUTE_PIPELINE) {
 653       brw_upload_cs_prog(brw);
 654    }
 655 }
 656
 657 static inline void
 658 merge_ctx_state(struct brw_context *brw,
 659                 struct brw_state_flags *state)
 660 {
 661    state->mesa |= brw->NewGLState;
 662    state->brw |= brw->ctx.NewDriverState;
 663 }
 664
 665 static inline void
 666 check_and_emit_atom(struct brw_context *brw,
 667                     struct brw_state_flags *state,
 668                     const struct brw_tracked_state *atom)
 669 {
 670    if (check_state(state, &atom->dirty)) {
 671       atom->emit(brw);
 672       merge_ctx_state(brw, state);
 673    }
 674 }
 675
 676 static inline void
 677 brw_upload_pipeline_state(struct brw_context *brw,
 678                           enum brw_pipeline pipeline)
 679 {
 680    struct gl_context *ctx = &brw->ctx;
 681    int i;
 682    static int dirty_count = 0;
 683    struct brw_state_flags state = brw->state.pipelines[pipeline];
 684    unsigned int fb_samples = _mesa_geometric_samples(ctx->DrawBuffer);
 685
 686    brw_select_pipeline(brw, pipeline);
 687
 688    if (0) {
 689       /* Always re-emit all state. */
 690       brw->NewGLState = ~0;
 691       ctx->NewDriverState = ~0ull;
 692    }
 693
 694    if (pipeline == BRW_RENDER_PIPELINE) {
 695       if (brw->fragment_program != ctx->FragmentProgram._Current) {
 696          brw->fragment_program = ctx->FragmentProgram._Current;
 697          brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
 698       }
 699
 700       if (brw->geometry_program != ctx->GeometryProgram._Current) {
 701          brw->geometry_program = ctx->GeometryProgram._Current;
 702          brw->ctx.NewDriverState |= BRW_NEW_GEOMETRY_PROGRAM;
 703       }
 704
 705       if (brw->vertex_program != ctx->VertexProgram._Current) {
 706          brw->vertex_program = ctx->VertexProgram._Current;
 707          brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM;
 708       }
 709    }
 710
 711    if (brw->compute_program != ctx->ComputeProgram._Current) {
 712       brw->compute_program = ctx->ComputeProgram._Current;
 713       brw->ctx.NewDriverState |= BRW_NEW_COMPUTE_PROGRAM;
 714    }
 715
 716    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 717       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 718       brw->ctx.NewDriverState |= BRW_NEW_META_IN_PROGRESS;
 719    }
 720
 721    if (brw->num_samples != fb_samples) {
 722       brw->num_samples = fb_samples;
 723       brw->ctx.NewDriverState |= BRW_NEW_NUM_SAMPLES;
 724    }
 725
 726    /* Exit early if no state is flagged as dirty */
 727    merge_ctx_state(brw, &state);
 728    if ((state.mesa | state.brw) == 0)
 729       return;
 730
 731    /* Emit Sandybridge workaround flushes on every primitive, for safety. */
 732    if (brw->gen == 6)
 733       brw_emit_post_sync_nonzero_flush(brw);
 734
 735    brw_upload_programs(brw, pipeline);
 736    merge_ctx_state(brw, &state);
 737
 738    const struct brw_tracked_state *atoms =
 739       brw_get_pipeline_atoms(brw, pipeline);
 740    const int num_atoms = brw->num_atoms[pipeline];
 741
 742    if (unlikely(INTEL_DEBUG)) {
 743       /* Debug version which enforces various sanity checks on the
 744        * state flags which are generated and checked to help ensure
 745        * state atoms are ordered correctly in the list.
 746        */
 747       struct brw_state_flags examined, prev;
 748       memset(&examined, 0, sizeof(examined));
 749       prev = state;
 750
 751       for (i = 0; i < num_atoms; i++) {
 752          const struct brw_tracked_state *atom = &atoms[i];
 753          struct brw_state_flags generated;
 754
 755          check_and_emit_atom(brw, &state, atom);
 756
 757          accumulate_state(&examined, &atom->dirty);
 758
 759          /* generated = (prev ^ state)
 760           * if (examined & generated)
 761           *     fail;
 762           */
 763          xor_states(&generated, &prev, &state);
 764          assert(!check_state(&examined, &generated));
 765          prev = state;
 766       }
 767    }
 768    else {
 769       for (i = 0; i < num_atoms; i++) {
 770          const struct brw_tracked_state *atom = &atoms[i];
 771
 772          check_and_emit_atom(brw, &state, atom);
 773       }
 774    }
 775
 776    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 777       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 778
 779       brw_update_dirty_count(mesa_bits, state.mesa);
 780       brw_update_dirty_count(brw_bits, state.brw);
 781       if (dirty_count++ % 1000 == 0) {
 782          brw_print_dirty_count(mesa_bits);
 783          brw_print_dirty_count(brw_bits);
 784          fprintf(stderr, "\n");
 785       }
 786    }
 787 }
 788
 789 /***********************************************************************
 790  * Emit all state:
 791  */
 792 void brw_upload_render_state(struct brw_context *brw)
 793 {
 794    brw_upload_pipeline_state(brw, BRW_RENDER_PIPELINE);
 795 }
 796
 797 static inline void
 798 brw_pipeline_state_finished(struct brw_context *brw,
 799                             enum brw_pipeline pipeline)
 800 {
 801    /* Save all dirty state into the other pipelines */
 802    for (unsigned i = 0; i < BRW_NUM_PIPELINES; i++) {
 803       if (i != pipeline) {
 804          brw->state.pipelines[i].mesa |= brw->NewGLState;
 805          brw->state.pipelines[i].brw |= brw->ctx.NewDriverState;
 806       } else {
 807          memset(&brw->state.pipelines[i], 0, sizeof(struct brw_state_flags));
 808       }
 809    }
 810
 811    brw->NewGLState = 0;
 812    brw->ctx.NewDriverState = 0ull;
 813 }
 814
 815 /**
 816  * Clear dirty bits to account for the fact that the state emitted by
 817  * brw_upload_render_state() has been committed to the hardware. This is a
 818  * separate call from brw_upload_render_state() because it's possible that
 819  * after the call to brw_upload_render_state(), we will discover that we've
 820  * run out of aperture space, and need to rewind the batch buffer to the state
 821  * it had before the brw_upload_render_state() call.
 822  */
 823 void
 824 brw_render_state_finished(struct brw_context *brw)
 825 {
 826    brw_pipeline_state_finished(brw, BRW_RENDER_PIPELINE);
 827 }
 828
 829 void
 830 brw_upload_compute_state(struct brw_context *brw)
 831 {
 832    brw_upload_pipeline_state(brw, BRW_COMPUTE_PIPELINE);
 833 }
 834
 835 void
 836 brw_compute_state_finished(struct brw_context *brw)
 837 {
 838    brw_pipeline_state_finished(brw, BRW_COMPUTE_PIPELINE);
 839 }