src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 static const struct brw_tracked_state *gen4_atoms[] =
  40 {
  41    &brw_vs_prog, /* must do before GS prog, state base address. */
  42    &brw_gs_prog, /* must do before state base address */
  43    &brw_clip_prog, /* must do before state base address */
  44    &brw_sf_prog, /* must do before state base address */
  45    &brw_wm_prog, /* must do before state base address */
  46
  47    /* Once all the programs are done, we know how large urb entry
  48     * sizes need to be and can decide if we need to change the urb
  49     * layout.
  50     */
  51    &brw_curbe_offsets,
  52    &brw_recalculate_urb_fence,
  53
  54    &brw_cc_vp,
  55    &brw_cc_unit,
  56
  57    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  58     * table upload must be last.
  59     */
  60    &brw_vs_pull_constants,
  61    &brw_wm_pull_constants,
  62    &brw_renderbuffer_surfaces,
  63    &brw_texture_surfaces,
  64    &brw_vs_binding_table,
  65    &brw_wm_binding_table,
  66
  67    &brw_samplers,
  68
  69    /* These set up state for brw_psp_urb_cbs */
  70    &brw_wm_unit,
  71    &brw_sf_vp,
  72    &brw_sf_unit,
  73    &brw_vs_unit,                /* always required, enabled or not */
  74    &brw_clip_unit,
  75    &brw_gs_unit,
  76
  77    /* Command packets:
  78     */
  79    &brw_invariant_state,
  80    &brw_state_base_address,
  81
  82    &brw_binding_table_pointers,
  83    &brw_blend_constant_color,
  84
  85    &brw_depthbuffer,
  86
  87    &brw_polygon_stipple,
  88    &brw_polygon_stipple_offset,
  89
  90    &brw_line_stipple,
  91    &brw_aa_line_parameters,
  92
  93    &brw_psp_urb_cbs,
  94
  95    &brw_drawing_rect,
  96    &brw_indices,
  97    &brw_index_buffer,
  98    &brw_vertices,
  99
 100    &brw_constant_buffer
 101 };
 102
 103 static const struct brw_tracked_state *gen6_atoms[] =
 104 {
 105    &brw_vs_prog, /* must do before state base address */
 106    &brw_gs_prog, /* must do before state base address */
 107    &brw_wm_prog, /* must do before state base address */
 108
 109    &gen6_clip_vp,
 110    &gen6_sf_vp,
 111
 112    /* Command packets: */
 113    &brw_invariant_state,
 114
 115    /* must do before binding table pointers, cc state ptrs */
 116    &brw_state_base_address,
 117
 118    &brw_cc_vp,
 119    &gen6_viewport_state,        /* must do after *_vp stages */
 120
 121    &gen6_urb,
 122    &gen6_blend_state,           /* must do before cc unit */
 123    &gen6_color_calc_state,      /* must do before cc unit */
 124    &gen6_depth_stencil_state,   /* must do before cc unit */
 125    &gen6_cc_state_pointers,
 126
 127    &gen6_vs_push_constants, /* Before vs_state */
 128    &gen6_wm_push_constants, /* Before wm_state */
 129
 130    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 131     * table upload must be last.
 132     */
 133    &brw_vs_pull_constants,
 134    &brw_vs_ubo_surfaces,
 135    &brw_wm_pull_constants,
 136    &brw_wm_ubo_surfaces,
 137    &gen6_renderbuffer_surfaces,
 138    &brw_texture_surfaces,
 139    &gen6_sol_surface,
 140    &brw_vs_binding_table,
 141    &gen6_gs_binding_table,
 142    &brw_wm_binding_table,
 143
 144    &brw_samplers,
 145    &gen6_sampler_state,
 146    &gen6_multisample_state,
 147
 148    &gen6_vs_state,
 149    &gen6_gs_state,
 150    &gen6_clip_state,
 151    &gen6_sf_state,
 152    &gen6_wm_state,
 153
 154    &gen6_scissor_state,
 155
 156    &gen6_binding_table_pointers,
 157
 158    &brw_depthbuffer,
 159
 160    &brw_polygon_stipple,
 161    &brw_polygon_stipple_offset,
 162
 163    &brw_line_stipple,
 164    &brw_aa_line_parameters,
 165
 166    &brw_drawing_rect,
 167
 168    &gen6_sol_indices,
 169    &brw_indices,
 170    &brw_index_buffer,
 171    &brw_vertices,
 172 };
 173
 174 static const struct brw_tracked_state *gen7_atoms[] =
 175 {
 176    &brw_vs_prog,
 177    &brw_wm_prog,
 178
 179    /* Command packets: */
 180    &brw_invariant_state,
 181    &gen7_push_constant_alloc,
 182
 183    /* must do before binding table pointers, cc state ptrs */
 184    &brw_state_base_address,
 185
 186    &brw_cc_vp,
 187    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 188    &gen7_sf_clip_viewport,
 189
 190    &gen7_urb,
 191    &gen6_blend_state,           /* must do before cc unit */
 192    &gen6_color_calc_state,      /* must do before cc unit */
 193    &gen6_depth_stencil_state,   /* must do before cc unit */
 194    &gen7_blend_state_pointer,
 195    &gen7_cc_state_pointer,
 196    &gen7_depth_stencil_state_pointer,
 197
 198    &gen6_vs_push_constants, /* Before vs_state */
 199    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 200
 201    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 202     * table upload must be last.
 203     */
 204    &brw_vs_pull_constants,
 205    &brw_vs_ubo_surfaces,
 206    &brw_wm_pull_constants,
 207    &brw_wm_ubo_surfaces,
 208    &gen6_renderbuffer_surfaces,
 209    &brw_texture_surfaces,
 210    &brw_vs_binding_table,
 211    &brw_wm_binding_table,
 212
 213    &gen7_samplers,
 214    &gen6_multisample_state,
 215
 216    &gen7_disable_stages,
 217    &gen7_vs_state,
 218    &gen7_sol_state,
 219    &gen7_clip_state,
 220    &gen7_sbe_state,
 221    &gen7_sf_state,
 222    &gen7_wm_state,
 223    &gen7_ps_state,
 224
 225    &gen6_scissor_state,
 226
 227    &gen7_depthbuffer,
 228
 229    &brw_polygon_stipple,
 230    &brw_polygon_stipple_offset,
 231
 232    &brw_line_stipple,
 233    &brw_aa_line_parameters,
 234
 235    &brw_drawing_rect,
 236
 237    &brw_indices,
 238    &brw_index_buffer,
 239    &brw_vertices,
 240
 241    &haswell_cut_index,
 242 };
 243
 244
 245 void brw_init_state( struct brw_context *brw )
 246 {
 247    const struct brw_tracked_state **atoms;
 248    int num_atoms;
 249
 250    brw_init_caches(brw);
 251
 252    if (brw->intel.gen >= 7) {
 253       atoms = gen7_atoms;
 254       num_atoms = ARRAY_SIZE(gen7_atoms);
 255    } else if (brw->intel.gen == 6) {
 256       atoms = gen6_atoms;
 257       num_atoms = ARRAY_SIZE(gen6_atoms);
 258    } else {
 259       atoms = gen4_atoms;
 260       num_atoms = ARRAY_SIZE(gen4_atoms);
 261    }
 262
 263    brw->atoms = atoms;
 264    brw->num_atoms = num_atoms;
 265
 266    while (num_atoms--) {
 267       assert((*atoms)->dirty.mesa |
 268              (*atoms)->dirty.brw |
 269              (*atoms)->dirty.cache);
 270       assert((*atoms)->emit);
 271       atoms++;
 272    }
 273 }
 274
 275
 276 void brw_destroy_state( struct brw_context *brw )
 277 {
 278    brw_destroy_caches(brw);
 279 }
 280
 281 /***********************************************************************
 282  */
 283
 284 static GLuint check_state( const struct brw_state_flags *a,
 285                            const struct brw_state_flags *b )
 286 {
 287    return ((a->mesa & b->mesa) |
 288            (a->brw & b->brw) |
 289            (a->cache & b->cache)) != 0;
 290 }
 291
 292 static void accumulate_state( struct brw_state_flags *a,
 293                               const struct brw_state_flags *b )
 294 {
 295    a->mesa |= b->mesa;
 296    a->brw |= b->brw;
 297    a->cache |= b->cache;
 298 }
 299
 300
 301 static void xor_states( struct brw_state_flags *result,
 302                              const struct brw_state_flags *a,
 303                               const struct brw_state_flags *b )
 304 {
 305    result->mesa = a->mesa ^ b->mesa;
 306    result->brw = a->brw ^ b->brw;
 307    result->cache = a->cache ^ b->cache;
 308 }
 309
 310 struct dirty_bit_map {
 311    uint32_t bit;
 312    char *name;
 313    uint32_t count;
 314 };
 315
 316 #define DEFINE_BIT(name) {name, #name, 0}
 317
 318 static struct dirty_bit_map mesa_bits[] = {
 319    DEFINE_BIT(_NEW_MODELVIEW),
 320    DEFINE_BIT(_NEW_PROJECTION),
 321    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 322    DEFINE_BIT(_NEW_COLOR),
 323    DEFINE_BIT(_NEW_DEPTH),
 324    DEFINE_BIT(_NEW_EVAL),
 325    DEFINE_BIT(_NEW_FOG),
 326    DEFINE_BIT(_NEW_HINT),
 327    DEFINE_BIT(_NEW_LIGHT),
 328    DEFINE_BIT(_NEW_LINE),
 329    DEFINE_BIT(_NEW_PIXEL),
 330    DEFINE_BIT(_NEW_POINT),
 331    DEFINE_BIT(_NEW_POLYGON),
 332    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 333    DEFINE_BIT(_NEW_SCISSOR),
 334    DEFINE_BIT(_NEW_STENCIL),
 335    DEFINE_BIT(_NEW_TEXTURE),
 336    DEFINE_BIT(_NEW_TRANSFORM),
 337    DEFINE_BIT(_NEW_VIEWPORT),
 338    DEFINE_BIT(_NEW_ARRAY),
 339    DEFINE_BIT(_NEW_RENDERMODE),
 340    DEFINE_BIT(_NEW_BUFFERS),
 341    DEFINE_BIT(_NEW_MULTISAMPLE),
 342    DEFINE_BIT(_NEW_TRACK_MATRIX),
 343    DEFINE_BIT(_NEW_PROGRAM),
 344    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 345    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 346    DEFINE_BIT(_NEW_FRAG_CLAMP),
 347    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 348    {0, 0, 0}
 349 };
 350
 351 static struct dirty_bit_map brw_bits[] = {
 352    DEFINE_BIT(BRW_NEW_URB_FENCE),
 353    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 354    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 355    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 356    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 357    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 358    DEFINE_BIT(BRW_NEW_CONTEXT),
 359    DEFINE_BIT(BRW_NEW_PSP),
 360    DEFINE_BIT(BRW_NEW_SURFACES),
 361    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 362    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 363    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 364    DEFINE_BIT(BRW_NEW_INDICES),
 365    DEFINE_BIT(BRW_NEW_VERTICES),
 366    DEFINE_BIT(BRW_NEW_BATCH),
 367    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 368    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 369    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 370    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 371    DEFINE_BIT(BRW_NEW_SOL_INDICES),
 372    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 373    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 374    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 375    {0, 0, 0}
 376 };
 377
 378 static struct dirty_bit_map cache_bits[] = {
 379    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 380    DEFINE_BIT(CACHE_NEW_DEPTH_STENCIL_STATE),
 381    DEFINE_BIT(CACHE_NEW_COLOR_CALC_STATE),
 382    DEFINE_BIT(CACHE_NEW_CC_VP),
 383    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 384    DEFINE_BIT(CACHE_NEW_WM_PROG),
 385    DEFINE_BIT(CACHE_NEW_SAMPLER),
 386    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 387    DEFINE_BIT(CACHE_NEW_SF_PROG),
 388    DEFINE_BIT(CACHE_NEW_SF_VP),
 389    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 390    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 391    DEFINE_BIT(CACHE_NEW_VS_PROG),
 392    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 393    DEFINE_BIT(CACHE_NEW_GS_PROG),
 394    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 395    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 396    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 397    {0, 0, 0}
 398 };
 399
 400
 401 static void
 402 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 403 {
 404    int i;
 405
 406    for (i = 0; i < 32; i++) {
 407       if (bit_map[i].bit == 0)
 408          return;
 409
 410       if (bit_map[i].bit & bits)
 411          bit_map[i].count++;
 412    }
 413 }
 414
 415 static void
 416 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 417 {
 418    int i;
 419
 420    for (i = 0; i < 32; i++) {
 421       if (bit_map[i].bit == 0)
 422          return;
 423
 424       fprintf(stderr, "0x%08x: %12d (%s)\n",
 425               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 426    }
 427 }
 428
 429 /***********************************************************************
 430  * Emit all state:
 431  */
 432 void brw_upload_state(struct brw_context *brw)
 433 {
 434    struct gl_context *ctx = &brw->intel.ctx;
 435    struct intel_context *intel = &brw->intel;
 436    struct brw_state_flags *state = &brw->state.dirty;
 437    int i;
 438    static int dirty_count = 0;
 439
 440    state->mesa |= brw->intel.NewGLState;
 441    brw->intel.NewGLState = 0;
 442
 443    state->brw |= ctx->NewDriverState;
 444    ctx->NewDriverState = 0;
 445
 446    if (brw->emit_state_always) {
 447       state->mesa |= ~0;
 448       state->brw |= ~0;
 449       state->cache |= ~0;
 450    }
 451
 452    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 453       brw->fragment_program = ctx->FragmentProgram._Current;
 454       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 455    }
 456
 457    if (brw->vertex_program != ctx->VertexProgram._Current) {
 458       brw->vertex_program = ctx->VertexProgram._Current;
 459       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 460    }
 461
 462    if ((state->mesa | state->cache | state->brw) == 0)
 463       return;
 464
 465    intel_check_front_buffer_rendering(intel);
 466
 467    if (unlikely(INTEL_DEBUG)) {
 468       /* Debug version which enforces various sanity checks on the
 469        * state flags which are generated and checked to help ensure
 470        * state atoms are ordered correctly in the list.
 471        */
 472       struct brw_state_flags examined, prev;
 473       memset(&examined, 0, sizeof(examined));
 474       prev = *state;
 475
 476       for (i = 0; i < brw->num_atoms; i++) {
 477          const struct brw_tracked_state *atom = brw->atoms[i];
 478          struct brw_state_flags generated;
 479
 480          if (check_state(state, &atom->dirty)) {
 481             atom->emit(brw);
 482          }
 483
 484          accumulate_state(&examined, &atom->dirty);
 485
 486          /* generated = (prev ^ state)
 487           * if (examined & generated)
 488           *     fail;
 489           */
 490          xor_states(&generated, &prev, state);
 491          assert(!check_state(&examined, &generated));
 492          prev = *state;
 493       }
 494    }
 495    else {
 496       for (i = 0; i < brw->num_atoms; i++) {
 497          const struct brw_tracked_state *atom = brw->atoms[i];
 498
 499          if (check_state(state, &atom->dirty)) {
 500             atom->emit(brw);
 501          }
 502       }
 503    }
 504
 505    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 506       brw_update_dirty_count(mesa_bits, state->mesa);
 507       brw_update_dirty_count(brw_bits, state->brw);
 508       brw_update_dirty_count(cache_bits, state->cache);
 509       if (dirty_count++ % 1000 == 0) {
 510          brw_print_dirty_count(mesa_bits, state->mesa);
 511          brw_print_dirty_count(brw_bits, state->brw);
 512          brw_print_dirty_count(cache_bits, state->cache);
 513          fprintf(stderr, "\n");
 514       }
 515    }
 516
 517    memset(state, 0, sizeof(*state));
 518 }