2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "intel_batchbuffer.h"
37 #include "intel_buffers.h"
38 #include "intel_chipset.h"
40 /* This is used to initialize brw->state.atoms[]. We could use this
41 * list directly except for a single atom, brw_constant_buffer, which
42 * has a .dirty value which changes according to the parameters of the
43 * current fragment and vertex programs, and so cannot be a static
46 static const struct brw_tracked_state
*gen4_atoms
[] =
57 /* Once all the programs are done, we know how large urb entry
58 * sizes need to be and can decide if we need to change the urb
62 &brw_recalculate_urb_fence
,
67 &brw_vs_surfaces
, /* must do before unit */
68 &brw_wm_constant_surface
, /* must do before wm surfaces/bind bo */
69 &brw_wm_surfaces
, /* must do before samplers and unit */
75 &brw_vs_unit
, /* always required, enabled or not */
82 &brw_state_base_address
,
84 &brw_binding_table_pointers
,
85 &brw_blend_constant_color
,
90 &brw_polygon_stipple_offset
,
93 &brw_aa_line_parameters
,
105 const struct brw_tracked_state
*gen6_atoms
[] =
116 /* Once all the programs are done, we know how large urb entry
117 * sizes need to be and can decide if we need to change the urb
127 &gen6_viewport_state
, /* must do after *_vp stages */
130 &gen6_blend_state
, /* must do before cc unit */
131 &gen6_color_calc_state
, /* must do before cc unit */
132 &gen6_depth_stencil_state
, /* must do before cc unit */
133 &gen6_cc_state_pointers
,
135 &brw_vs_surfaces
, /* must do before unit */
136 &brw_wm_constant_surface
, /* must do before wm surfaces/bind bo */
137 &brw_wm_surfaces
, /* must do before samplers and unit */
154 &brw_invarient_state
,
157 &brw_state_base_address
,
160 &brw_binding_table_pointers
,
161 &brw_blend_constant_color
,
167 &brw_polygon_stipple
,
168 &brw_polygon_stipple_offset
,
171 &brw_aa_line_parameters
,
183 void brw_init_state( struct brw_context
*brw
)
185 brw_init_caches(brw
);
189 void brw_destroy_state( struct brw_context
*brw
)
191 brw_destroy_caches(brw
);
192 brw_destroy_batch_cache(brw
);
195 /***********************************************************************
198 static GLboolean
check_state( const struct brw_state_flags
*a
,
199 const struct brw_state_flags
*b
)
201 return ((a
->mesa
& b
->mesa
) ||
203 (a
->cache
& b
->cache
));
206 static void accumulate_state( struct brw_state_flags
*a
,
207 const struct brw_state_flags
*b
)
211 a
->cache
|= b
->cache
;
215 static void xor_states( struct brw_state_flags
*result
,
216 const struct brw_state_flags
*a
,
217 const struct brw_state_flags
*b
)
219 result
->mesa
= a
->mesa
^ b
->mesa
;
220 result
->brw
= a
->brw
^ b
->brw
;
221 result
->cache
= a
->cache
^ b
->cache
;
225 brw_clear_validated_bos(struct brw_context
*brw
)
229 /* Clear the last round of validated bos */
230 for (i
= 0; i
< brw
->state
.validated_bo_count
; i
++) {
231 dri_bo_unreference(brw
->state
.validated_bos
[i
]);
232 brw
->state
.validated_bos
[i
] = NULL
;
234 brw
->state
.validated_bo_count
= 0;
237 struct dirty_bit_map
{
243 #define DEFINE_BIT(name) {name, #name, 0}
245 static struct dirty_bit_map mesa_bits
[] = {
246 DEFINE_BIT(_NEW_MODELVIEW
),
247 DEFINE_BIT(_NEW_PROJECTION
),
248 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
249 DEFINE_BIT(_NEW_COLOR_MATRIX
),
250 DEFINE_BIT(_NEW_ACCUM
),
251 DEFINE_BIT(_NEW_COLOR
),
252 DEFINE_BIT(_NEW_DEPTH
),
253 DEFINE_BIT(_NEW_EVAL
),
254 DEFINE_BIT(_NEW_FOG
),
255 DEFINE_BIT(_NEW_HINT
),
256 DEFINE_BIT(_NEW_LIGHT
),
257 DEFINE_BIT(_NEW_LINE
),
258 DEFINE_BIT(_NEW_PIXEL
),
259 DEFINE_BIT(_NEW_POINT
),
260 DEFINE_BIT(_NEW_POLYGON
),
261 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
262 DEFINE_BIT(_NEW_SCISSOR
),
263 DEFINE_BIT(_NEW_STENCIL
),
264 DEFINE_BIT(_NEW_TEXTURE
),
265 DEFINE_BIT(_NEW_TRANSFORM
),
266 DEFINE_BIT(_NEW_VIEWPORT
),
267 DEFINE_BIT(_NEW_PACKUNPACK
),
268 DEFINE_BIT(_NEW_ARRAY
),
269 DEFINE_BIT(_NEW_RENDERMODE
),
270 DEFINE_BIT(_NEW_BUFFERS
),
271 DEFINE_BIT(_NEW_MULTISAMPLE
),
272 DEFINE_BIT(_NEW_TRACK_MATRIX
),
273 DEFINE_BIT(_NEW_PROGRAM
),
274 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
278 static struct dirty_bit_map brw_bits
[] = {
279 DEFINE_BIT(BRW_NEW_URB_FENCE
),
280 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
281 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
282 DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS
),
283 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS
),
284 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
285 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
286 DEFINE_BIT(BRW_NEW_CONTEXT
),
287 DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS
),
288 DEFINE_BIT(BRW_NEW_PSP
),
289 DEFINE_BIT(BRW_NEW_INDICES
),
290 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
291 DEFINE_BIT(BRW_NEW_VERTICES
),
292 DEFINE_BIT(BRW_NEW_BATCH
),
293 DEFINE_BIT(BRW_NEW_DEPTH_BUFFER
),
297 static struct dirty_bit_map cache_bits
[] = {
298 DEFINE_BIT(CACHE_NEW_BLEND_STATE
),
299 DEFINE_BIT(CACHE_NEW_CC_VP
),
300 DEFINE_BIT(CACHE_NEW_CC_UNIT
),
301 DEFINE_BIT(CACHE_NEW_WM_PROG
),
302 DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR
),
303 DEFINE_BIT(CACHE_NEW_SAMPLER
),
304 DEFINE_BIT(CACHE_NEW_WM_UNIT
),
305 DEFINE_BIT(CACHE_NEW_SF_PROG
),
306 DEFINE_BIT(CACHE_NEW_SF_VP
),
307 DEFINE_BIT(CACHE_NEW_SF_UNIT
),
308 DEFINE_BIT(CACHE_NEW_VS_UNIT
),
309 DEFINE_BIT(CACHE_NEW_VS_PROG
),
310 DEFINE_BIT(CACHE_NEW_GS_UNIT
),
311 DEFINE_BIT(CACHE_NEW_GS_PROG
),
312 DEFINE_BIT(CACHE_NEW_CLIP_VP
),
313 DEFINE_BIT(CACHE_NEW_CLIP_UNIT
),
314 DEFINE_BIT(CACHE_NEW_CLIP_PROG
),
315 DEFINE_BIT(CACHE_NEW_SURFACE
),
316 DEFINE_BIT(CACHE_NEW_SURF_BIND
),
322 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, int32_t bits
)
326 for (i
= 0; i
< 32; i
++) {
327 if (bit_map
[i
].bit
== 0)
330 if (bit_map
[i
].bit
& bits
)
336 brw_print_dirty_count(struct dirty_bit_map
*bit_map
, int32_t bits
)
340 for (i
= 0; i
< 32; i
++) {
341 if (bit_map
[i
].bit
== 0)
344 fprintf(stderr
, "0x%08x: %12d (%s)\n",
345 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
349 /***********************************************************************
352 void brw_validate_state( struct brw_context
*brw
)
354 GLcontext
*ctx
= &brw
->intel
.ctx
;
355 struct intel_context
*intel
= &brw
->intel
;
356 struct brw_state_flags
*state
= &brw
->state
.dirty
;
358 const struct brw_tracked_state
**atoms
;
361 brw_clear_validated_bos(brw
);
363 state
->mesa
|= brw
->intel
.NewGLState
;
364 brw
->intel
.NewGLState
= 0;
366 brw_add_validated_bo(brw
, intel
->batch
->buf
);
368 if (IS_GEN6(intel
->intelScreen
->deviceID
)) {
370 num_atoms
= ARRAY_SIZE(gen6_atoms
);
373 num_atoms
= ARRAY_SIZE(gen4_atoms
);
376 if (brw
->emit_state_always
) {
382 if (brw
->fragment_program
!= ctx
->FragmentProgram
._Current
) {
383 brw
->fragment_program
= ctx
->FragmentProgram
._Current
;
384 brw
->state
.dirty
.brw
|= BRW_NEW_FRAGMENT_PROGRAM
;
387 if (brw
->vertex_program
!= ctx
->VertexProgram
._Current
) {
388 brw
->vertex_program
= ctx
->VertexProgram
._Current
;
389 brw
->state
.dirty
.brw
|= BRW_NEW_VERTEX_PROGRAM
;
392 if (state
->mesa
== 0 &&
397 if (brw
->state
.dirty
.brw
& BRW_NEW_CONTEXT
)
398 brw_clear_batch_cache(brw
);
400 brw
->intel
.Fallback
= GL_FALSE
; /* boolean, not bitfield */
402 /* do prepare stage for all atoms */
403 for (i
= 0; i
< num_atoms
; i
++) {
404 const struct brw_tracked_state
*atom
= atoms
[i
];
406 if (brw
->intel
.Fallback
)
409 if (check_state(state
, &atom
->dirty
)) {
416 intel_check_front_buffer_rendering(intel
);
418 /* Make sure that the textures which are referenced by the current
419 * brw fragment program are actually present/valid.
420 * If this fails, we can experience GPU lock-ups.
423 const struct brw_fragment_program
*fp
;
424 fp
= brw_fragment_program_const(brw
->fragment_program
);
426 assert((fp
->tex_units_used
& ctx
->Texture
._EnabledUnits
)
427 == fp
->tex_units_used
);
433 void brw_upload_state(struct brw_context
*brw
)
435 struct intel_context
*intel
= &brw
->intel
;
436 struct brw_state_flags
*state
= &brw
->state
.dirty
;
438 static int dirty_count
= 0;
439 const struct brw_tracked_state
**atoms
;
442 if (IS_GEN6(intel
->intelScreen
->deviceID
)) {
444 num_atoms
= ARRAY_SIZE(gen6_atoms
);
447 num_atoms
= ARRAY_SIZE(gen4_atoms
);
450 brw_clear_validated_bos(brw
);
453 /* Debug version which enforces various sanity checks on the
454 * state flags which are generated and checked to help ensure
455 * state atoms are ordered correctly in the list.
457 struct brw_state_flags examined
, prev
;
458 memset(&examined
, 0, sizeof(examined
));
461 for (i
= 0; i
< num_atoms
; i
++) {
462 const struct brw_tracked_state
*atom
= atoms
[i
];
463 struct brw_state_flags generated
;
465 assert(atom
->dirty
.mesa
||
469 if (brw
->intel
.Fallback
)
472 if (check_state(state
, &atom
->dirty
)) {
478 accumulate_state(&examined
, &atom
->dirty
);
480 /* generated = (prev ^ state)
481 * if (examined & generated)
484 xor_states(&generated
, &prev
, state
);
485 assert(!check_state(&examined
, &generated
));
490 for (i
= 0; i
< num_atoms
; i
++) {
491 const struct brw_tracked_state
*atom
= atoms
[i
];
493 if (brw
->intel
.Fallback
)
496 if (check_state(state
, &atom
->dirty
)) {
504 if (INTEL_DEBUG
& DEBUG_STATE
) {
505 brw_update_dirty_count(mesa_bits
, state
->mesa
);
506 brw_update_dirty_count(brw_bits
, state
->brw
);
507 brw_update_dirty_count(cache_bits
, state
->cache
);
508 if (dirty_count
++ % 1000 == 0) {
509 brw_print_dirty_count(mesa_bits
, state
->mesa
);
510 brw_print_dirty_count(brw_bits
, state
->brw
);
511 brw_print_dirty_count(cache_bits
, state
->cache
);
512 fprintf(stderr
, "\n");
516 if (!brw
->intel
.Fallback
)
517 memset(state
, 0, sizeof(*state
));