src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_wm_push_constants, /* Before wm_state */
 132
 133    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 134     * table upload must be last.
 135     */
 136    &brw_vs_pull_constants,
 137    &brw_vs_ubo_surfaces,
 138    &brw_wm_pull_constants,
 139    &brw_wm_ubo_surfaces,
 140    &gen6_renderbuffer_surfaces,
 141    &brw_texture_surfaces,
 142    &gen6_sol_surface,
 143    &brw_vs_binding_table,
 144    &gen6_gs_binding_table,
 145    &brw_wm_binding_table,
 146
 147    &brw_fs_samplers,
 148    &brw_vs_samplers,
 149    &gen6_sampler_state,
 150    &gen6_multisample_state,
 151
 152    &gen6_vs_state,
 153    &gen6_gs_state,
 154    &gen6_clip_state,
 155    &gen6_sf_state,
 156    &gen6_wm_state,
 157
 158    &gen6_scissor_state,
 159
 160    &gen6_binding_table_pointers,
 161
 162    &brw_depthbuffer,
 163
 164    &brw_polygon_stipple,
 165    &brw_polygon_stipple_offset,
 166
 167    &brw_line_stipple,
 168    &brw_aa_line_parameters,
 169
 170    &brw_drawing_rect,
 171
 172    &brw_indices,
 173    &brw_index_buffer,
 174    &brw_vertices,
 175 };
 176
 177 static const struct brw_tracked_state *gen7_atoms[] =
 178 {
 179    &brw_vs_prog,
 180    &brw_wm_prog,
 181
 182    /* Command packets: */
 183
 184    /* must do before binding table pointers, cc state ptrs */
 185    &brw_state_base_address,
 186
 187    &brw_cc_vp,
 188    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 189    &gen7_sf_clip_viewport,
 190
 191    &gen7_urb,
 192    &gen6_blend_state,           /* must do before cc unit */
 193    &gen6_color_calc_state,      /* must do before cc unit */
 194    &gen6_depth_stencil_state,   /* must do before cc unit */
 195
 196    &gen6_vs_push_constants, /* Before vs_state */
 197    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 198
 199    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 200     * table upload must be last.
 201     */
 202    &brw_vs_pull_constants,
 203    &brw_vs_ubo_surfaces,
 204    &brw_wm_pull_constants,
 205    &brw_wm_ubo_surfaces,
 206    &gen6_renderbuffer_surfaces,
 207    &brw_texture_surfaces,
 208    &brw_vs_binding_table,
 209    &brw_wm_binding_table,
 210
 211    &brw_fs_samplers,
 212    &brw_vs_samplers,
 213    &gen6_multisample_state,
 214
 215    &gen7_disable_stages,
 216    &gen7_vs_state,
 217    &gen7_sol_state,
 218    &gen7_clip_state,
 219    &gen7_sbe_state,
 220    &gen7_sf_state,
 221    &gen7_wm_state,
 222    &gen7_ps_state,
 223
 224    &gen6_scissor_state,
 225
 226    &gen7_depthbuffer,
 227
 228    &brw_polygon_stipple,
 229    &brw_polygon_stipple_offset,
 230
 231    &brw_line_stipple,
 232    &brw_aa_line_parameters,
 233
 234    &brw_drawing_rect,
 235
 236    &brw_indices,
 237    &brw_index_buffer,
 238    &brw_vertices,
 239
 240    &haswell_cut_index,
 241 };
 242
 243 static void
 244 brw_upload_initial_gpu_state(struct brw_context *brw)
 245 {
 246    /* On platforms with hardware contexts, we can set our initial GPU state
 247     * right away rather than doing it via state atoms.  This saves a small
 248     * amount of overhead on every draw call.
 249     */
 250    if (!brw->hw_ctx)
 251       return;
 252
 253    brw_upload_invariant_state(brw);
 254
 255    if (brw->gen >= 7) {
 256       gen7_allocate_push_constants(brw);
 257    }
 258 }
 259
 260 void brw_init_state( struct brw_context *brw )
 261 {
 262    const struct brw_tracked_state **atoms;
 263    int num_atoms;
 264
 265    brw_init_caches(brw);
 266
 267    if (brw->gen >= 7) {
 268       atoms = gen7_atoms;
 269       num_atoms = ARRAY_SIZE(gen7_atoms);
 270    } else if (brw->gen == 6) {
 271       atoms = gen6_atoms;
 272       num_atoms = ARRAY_SIZE(gen6_atoms);
 273    } else {
 274       atoms = gen4_atoms;
 275       num_atoms = ARRAY_SIZE(gen4_atoms);
 276    }
 277
 278    brw->atoms = atoms;
 279    brw->num_atoms = num_atoms;
 280
 281    while (num_atoms--) {
 282       assert((*atoms)->dirty.mesa |
 283              (*atoms)->dirty.brw |
 284              (*atoms)->dirty.cache);
 285       assert((*atoms)->emit);
 286       atoms++;
 287    }
 288
 289    brw_upload_initial_gpu_state(brw);
 290 }
 291
 292
 293 void brw_destroy_state( struct brw_context *brw )
 294 {
 295    brw_destroy_caches(brw);
 296 }
 297
 298 /***********************************************************************
 299  */
 300
 301 static bool
 302 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 303 {
 304    return ((a->mesa & b->mesa) |
 305            (a->brw & b->brw) |
 306            (a->cache & b->cache)) != 0;
 307 }
 308
 309 static void accumulate_state( struct brw_state_flags *a,
 310                               const struct brw_state_flags *b )
 311 {
 312    a->mesa |= b->mesa;
 313    a->brw |= b->brw;
 314    a->cache |= b->cache;
 315 }
 316
 317
 318 static void xor_states( struct brw_state_flags *result,
 319                              const struct brw_state_flags *a,
 320                               const struct brw_state_flags *b )
 321 {
 322    result->mesa = a->mesa ^ b->mesa;
 323    result->brw = a->brw ^ b->brw;
 324    result->cache = a->cache ^ b->cache;
 325 }
 326
 327 struct dirty_bit_map {
 328    uint32_t bit;
 329    char *name;
 330    uint32_t count;
 331 };
 332
 333 #define DEFINE_BIT(name) {name, #name, 0}
 334
 335 static struct dirty_bit_map mesa_bits[] = {
 336    DEFINE_BIT(_NEW_MODELVIEW),
 337    DEFINE_BIT(_NEW_PROJECTION),
 338    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 339    DEFINE_BIT(_NEW_COLOR),
 340    DEFINE_BIT(_NEW_DEPTH),
 341    DEFINE_BIT(_NEW_EVAL),
 342    DEFINE_BIT(_NEW_FOG),
 343    DEFINE_BIT(_NEW_HINT),
 344    DEFINE_BIT(_NEW_LIGHT),
 345    DEFINE_BIT(_NEW_LINE),
 346    DEFINE_BIT(_NEW_PIXEL),
 347    DEFINE_BIT(_NEW_POINT),
 348    DEFINE_BIT(_NEW_POLYGON),
 349    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 350    DEFINE_BIT(_NEW_SCISSOR),
 351    DEFINE_BIT(_NEW_STENCIL),
 352    DEFINE_BIT(_NEW_TEXTURE),
 353    DEFINE_BIT(_NEW_TRANSFORM),
 354    DEFINE_BIT(_NEW_VIEWPORT),
 355    DEFINE_BIT(_NEW_ARRAY),
 356    DEFINE_BIT(_NEW_RENDERMODE),
 357    DEFINE_BIT(_NEW_BUFFERS),
 358    DEFINE_BIT(_NEW_MULTISAMPLE),
 359    DEFINE_BIT(_NEW_TRACK_MATRIX),
 360    DEFINE_BIT(_NEW_PROGRAM),
 361    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 362    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 363    DEFINE_BIT(_NEW_FRAG_CLAMP),
 364    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 365    {0, 0, 0}
 366 };
 367
 368 static struct dirty_bit_map brw_bits[] = {
 369    DEFINE_BIT(BRW_NEW_URB_FENCE),
 370    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 371    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 372    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 373    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 374    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 375    DEFINE_BIT(BRW_NEW_CONTEXT),
 376    DEFINE_BIT(BRW_NEW_PSP),
 377    DEFINE_BIT(BRW_NEW_SURFACES),
 378    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 379    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 380    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 381    DEFINE_BIT(BRW_NEW_INDICES),
 382    DEFINE_BIT(BRW_NEW_VERTICES),
 383    DEFINE_BIT(BRW_NEW_BATCH),
 384    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 385    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 386    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 387    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 388    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 389    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 390    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 391    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 392    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 393    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 394    {0, 0, 0}
 395 };
 396
 397 static struct dirty_bit_map cache_bits[] = {
 398    DEFINE_BIT(CACHE_NEW_CC_VP),
 399    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 400    DEFINE_BIT(CACHE_NEW_WM_PROG),
 401    DEFINE_BIT(CACHE_NEW_SAMPLER),
 402    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 403    DEFINE_BIT(CACHE_NEW_SF_PROG),
 404    DEFINE_BIT(CACHE_NEW_SF_VP),
 405    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 406    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 407    DEFINE_BIT(CACHE_NEW_VS_PROG),
 408    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 409    DEFINE_BIT(CACHE_NEW_GS_PROG),
 410    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 411    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 412    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 413    {0, 0, 0}
 414 };
 415
 416
 417 static void
 418 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 419 {
 420    int i;
 421
 422    for (i = 0; i < 32; i++) {
 423       if (bit_map[i].bit == 0)
 424          return;
 425
 426       if (bit_map[i].bit & bits)
 427          bit_map[i].count++;
 428    }
 429 }
 430
 431 static void
 432 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 433 {
 434    int i;
 435
 436    for (i = 0; i < 32; i++) {
 437       if (bit_map[i].bit == 0)
 438          return;
 439
 440       fprintf(stderr, "0x%08x: %12d (%s)\n",
 441               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 442    }
 443 }
 444
 445 /***********************************************************************
 446  * Emit all state:
 447  */
 448 void brw_upload_state(struct brw_context *brw)
 449 {
 450    struct gl_context *ctx = &brw->ctx;
 451    struct brw_state_flags *state = &brw->state.dirty;
 452    int i;
 453    static int dirty_count = 0;
 454
 455    state->mesa |= brw->NewGLState;
 456    brw->NewGLState = 0;
 457
 458    state->brw |= ctx->NewDriverState;
 459    ctx->NewDriverState = 0;
 460
 461    if (brw->emit_state_always) {
 462       state->mesa |= ~0;
 463       state->brw |= ~0;
 464       state->cache |= ~0;
 465    }
 466
 467    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 468       brw->fragment_program = ctx->FragmentProgram._Current;
 469       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 470    }
 471
 472    if (brw->vertex_program != ctx->VertexProgram._Current) {
 473       brw->vertex_program = ctx->VertexProgram._Current;
 474       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 475    }
 476
 477    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 478       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 479       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 480    }
 481
 482    if ((state->mesa | state->cache | state->brw) == 0)
 483       return;
 484
 485    intel_check_front_buffer_rendering(brw);
 486
 487    if (unlikely(INTEL_DEBUG)) {
 488       /* Debug version which enforces various sanity checks on the
 489        * state flags which are generated and checked to help ensure
 490        * state atoms are ordered correctly in the list.
 491        */
 492       struct brw_state_flags examined, prev;
 493       memset(&examined, 0, sizeof(examined));
 494       prev = *state;
 495
 496       for (i = 0; i < brw->num_atoms; i++) {
 497          const struct brw_tracked_state *atom = brw->atoms[i];
 498          struct brw_state_flags generated;
 499
 500          if (check_state(state, &atom->dirty)) {
 501             atom->emit(brw);
 502          }
 503
 504          accumulate_state(&examined, &atom->dirty);
 505
 506          /* generated = (prev ^ state)
 507           * if (examined & generated)
 508           *     fail;
 509           */
 510          xor_states(&generated, &prev, state);
 511          assert(!check_state(&examined, &generated));
 512          prev = *state;
 513       }
 514    }
 515    else {
 516       for (i = 0; i < brw->num_atoms; i++) {
 517          const struct brw_tracked_state *atom = brw->atoms[i];
 518
 519          if (check_state(state, &atom->dirty)) {
 520             atom->emit(brw);
 521          }
 522       }
 523    }
 524
 525    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 526       brw_update_dirty_count(mesa_bits, state->mesa);
 527       brw_update_dirty_count(brw_bits, state->brw);
 528       brw_update_dirty_count(cache_bits, state->cache);
 529       if (dirty_count++ % 1000 == 0) {
 530          brw_print_dirty_count(mesa_bits);
 531          brw_print_dirty_count(brw_bits);
 532          brw_print_dirty_count(cache_bits);
 533          fprintf(stderr, "\n");
 534       }
 535    }
 536
 537    memset(state, 0, sizeof(*state));
 538 }