2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "intel_batchbuffer.h"
37 #include "intel_buffers.h"
39 /* This is used to initialize brw->state.atoms[]. We could use this
40 * list directly except for a single atom, brw_constant_buffer, which
41 * has a .dirty value which changes according to the parameters of the
42 * current fragment and vertex programs, and so cannot be a static
45 static const struct brw_tracked_state
*gen4_atoms
[] =
50 &brw_vs_prog
, /* must do before GS prog, state base address. */
51 &brw_gs_prog
, /* must do before state base address */
52 &brw_clip_prog
, /* must do before state base address */
53 &brw_sf_prog
, /* must do before state base address */
54 &brw_wm_prog
, /* must do before state base address */
56 /* Once all the programs are done, we know how large urb entry
57 * sizes need to be and can decide if we need to change the urb
61 &brw_recalculate_urb_fence
,
66 &brw_vs_constants
, /* Before vs_surfaces and constant_buffer */
67 &brw_wm_constants
, /* Before wm_surfaces and constant_buffer */
69 &brw_vs_surfaces
, /* must do before unit */
70 &brw_wm_constant_surface
, /* must do before wm surfaces/bind bo */
71 &brw_wm_surfaces
, /* must do before samplers and unit */
72 &brw_wm_binding_table
,
75 /* These set up state for brw_psp_urb_cbs */
79 &brw_vs_unit
, /* always required, enabled or not */
86 &brw_state_base_address
,
88 &brw_binding_table_pointers
,
89 &brw_blend_constant_color
,
94 &brw_polygon_stipple_offset
,
97 &brw_aa_line_parameters
,
109 static const struct brw_tracked_state
*gen6_atoms
[] =
114 &brw_vs_prog
, /* must do before state base address */
115 &brw_gs_prog
, /* must do before state base address */
116 &brw_wm_prog
, /* must do before state base address */
121 /* Command packets: */
122 &brw_invarient_state
,
124 /* must do before binding table pointers, cc state ptrs */
125 &brw_state_base_address
,
128 &gen6_viewport_state
, /* must do after *_vp stages */
131 &gen6_blend_state
, /* must do before cc unit */
132 &gen6_color_calc_state
, /* must do before cc unit */
133 &gen6_depth_stencil_state
, /* must do before cc unit */
134 &gen6_cc_state_pointers
,
136 &brw_vs_constants
, /* Before vs_surfaces and constant_buffer */
137 &brw_wm_constants
, /* Before wm_surfaces and constant_buffer */
138 &gen6_vs_constants
, /* Before vs_state */
139 &gen6_wm_constants
, /* Before wm_state */
141 &brw_vs_surfaces
, /* must do before unit */
142 &brw_wm_constant_surface
, /* must do before wm surfaces/bind bo */
143 &brw_wm_surfaces
, /* must do before samplers and unit */
144 &brw_wm_binding_table
,
157 &gen6_binding_table_pointers
,
161 &brw_polygon_stipple
,
162 &brw_polygon_stipple_offset
,
165 &brw_aa_line_parameters
,
174 const struct brw_tracked_state
*gen7_atoms
[] =
183 /* Command packets: */
184 &brw_invarient_state
,
186 /* must do before binding table pointers, cc state ptrs */
187 &brw_state_base_address
,
190 &gen7_cc_viewport_state_pointer
, /* must do after brw_cc_vp */
191 &gen7_sf_clip_viewport
,
194 &gen6_blend_state
, /* must do before cc unit */
195 &gen6_color_calc_state
, /* must do before cc unit */
196 &gen6_depth_stencil_state
, /* must do before cc unit */
197 &gen7_blend_state_pointer
,
198 &gen7_cc_state_pointer
,
199 &gen7_depth_stencil_state_pointer
,
201 &brw_vs_constants
, /* Before vs_surfaces and constant_buffer */
202 &brw_wm_constants
, /* Before wm_surfaces and constant_buffer */
203 &gen6_vs_constants
, /* Before vs_state */
204 &gen6_wm_constants
, /* Before wm_surfaces and constant_buffer */
206 &brw_vs_surfaces
, /* must do before unit */
207 &gen7_wm_constant_surface
, /* must do before wm surfaces/bind bo */
208 &gen7_wm_surfaces
, /* must do before samplers and unit */
209 &brw_wm_binding_table
,
213 &gen7_disable_stages
,
225 &brw_polygon_stipple
,
226 &brw_polygon_stipple_offset
,
229 &brw_aa_line_parameters
,
239 void brw_init_state( struct brw_context
*brw
)
241 const struct brw_tracked_state
**atoms
;
244 brw_init_caches(brw
);
246 if (brw
->intel
.gen
>= 7) {
248 num_atoms
= ARRAY_SIZE(gen7_atoms
);
249 } else if (brw
->intel
.gen
== 6) {
251 num_atoms
= ARRAY_SIZE(gen6_atoms
);
254 num_atoms
= ARRAY_SIZE(gen4_atoms
);
257 while (num_atoms
--) {
258 assert((*atoms
)->dirty
.mesa
|
259 (*atoms
)->dirty
.brw
|
260 (*atoms
)->dirty
.cache
);
262 if ((*atoms
)->prepare
)
263 brw
->prepare_atoms
[brw
->num_prepare_atoms
++] = **atoms
;
265 brw
->emit_atoms
[brw
->num_emit_atoms
++] = **atoms
;
268 assert(brw
->num_emit_atoms
<= ARRAY_SIZE(brw
->emit_atoms
));
269 assert(brw
->num_prepare_atoms
<= ARRAY_SIZE(brw
->prepare_atoms
));
273 void brw_destroy_state( struct brw_context
*brw
)
275 brw_destroy_caches(brw
);
278 /***********************************************************************
281 static GLuint
check_state( const struct brw_state_flags
*a
,
282 const struct brw_state_flags
*b
)
284 return ((a
->mesa
& b
->mesa
) |
286 (a
->cache
& b
->cache
)) != 0;
289 static void accumulate_state( struct brw_state_flags
*a
,
290 const struct brw_state_flags
*b
)
294 a
->cache
|= b
->cache
;
298 static void xor_states( struct brw_state_flags
*result
,
299 const struct brw_state_flags
*a
,
300 const struct brw_state_flags
*b
)
302 result
->mesa
= a
->mesa
^ b
->mesa
;
303 result
->brw
= a
->brw
^ b
->brw
;
304 result
->cache
= a
->cache
^ b
->cache
;
307 struct dirty_bit_map
{
313 #define DEFINE_BIT(name) {name, #name, 0}
315 static struct dirty_bit_map mesa_bits
[] = {
316 DEFINE_BIT(_NEW_MODELVIEW
),
317 DEFINE_BIT(_NEW_PROJECTION
),
318 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
319 DEFINE_BIT(_NEW_COLOR
),
320 DEFINE_BIT(_NEW_DEPTH
),
321 DEFINE_BIT(_NEW_EVAL
),
322 DEFINE_BIT(_NEW_FOG
),
323 DEFINE_BIT(_NEW_HINT
),
324 DEFINE_BIT(_NEW_LIGHT
),
325 DEFINE_BIT(_NEW_LINE
),
326 DEFINE_BIT(_NEW_PIXEL
),
327 DEFINE_BIT(_NEW_POINT
),
328 DEFINE_BIT(_NEW_POLYGON
),
329 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
330 DEFINE_BIT(_NEW_SCISSOR
),
331 DEFINE_BIT(_NEW_STENCIL
),
332 DEFINE_BIT(_NEW_TEXTURE
),
333 DEFINE_BIT(_NEW_TRANSFORM
),
334 DEFINE_BIT(_NEW_VIEWPORT
),
335 DEFINE_BIT(_NEW_PACKUNPACK
),
336 DEFINE_BIT(_NEW_ARRAY
),
337 DEFINE_BIT(_NEW_RENDERMODE
),
338 DEFINE_BIT(_NEW_BUFFERS
),
339 DEFINE_BIT(_NEW_MULTISAMPLE
),
340 DEFINE_BIT(_NEW_TRACK_MATRIX
),
341 DEFINE_BIT(_NEW_PROGRAM
),
342 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
346 static struct dirty_bit_map brw_bits
[] = {
347 DEFINE_BIT(BRW_NEW_URB_FENCE
),
348 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
349 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
350 DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS
),
351 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS
),
352 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
353 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
354 DEFINE_BIT(BRW_NEW_CONTEXT
),
355 DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS
),
356 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
357 DEFINE_BIT(BRW_NEW_PSP
),
358 DEFINE_BIT(BRW_NEW_WM_SURFACES
),
359 DEFINE_BIT(BRW_NEW_INDICES
),
360 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
361 DEFINE_BIT(BRW_NEW_VERTICES
),
362 DEFINE_BIT(BRW_NEW_BATCH
),
363 DEFINE_BIT(BRW_NEW_NR_WM_SURFACES
),
364 DEFINE_BIT(BRW_NEW_NR_VS_SURFACES
),
365 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
366 DEFINE_BIT(BRW_NEW_WM_CONSTBUF
),
367 DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE
),
368 DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE
),
369 DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE
),
370 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
374 static struct dirty_bit_map cache_bits
[] = {
375 DEFINE_BIT(CACHE_NEW_BLEND_STATE
),
376 DEFINE_BIT(CACHE_NEW_CC_VP
),
377 DEFINE_BIT(CACHE_NEW_CC_UNIT
),
378 DEFINE_BIT(CACHE_NEW_WM_PROG
),
379 DEFINE_BIT(CACHE_NEW_SAMPLER
),
380 DEFINE_BIT(CACHE_NEW_WM_UNIT
),
381 DEFINE_BIT(CACHE_NEW_SF_PROG
),
382 DEFINE_BIT(CACHE_NEW_SF_VP
),
383 DEFINE_BIT(CACHE_NEW_SF_UNIT
),
384 DEFINE_BIT(CACHE_NEW_VS_UNIT
),
385 DEFINE_BIT(CACHE_NEW_VS_PROG
),
386 DEFINE_BIT(CACHE_NEW_GS_UNIT
),
387 DEFINE_BIT(CACHE_NEW_GS_PROG
),
388 DEFINE_BIT(CACHE_NEW_CLIP_VP
),
389 DEFINE_BIT(CACHE_NEW_CLIP_UNIT
),
390 DEFINE_BIT(CACHE_NEW_CLIP_PROG
),
396 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, int32_t bits
)
400 for (i
= 0; i
< 32; i
++) {
401 if (bit_map
[i
].bit
== 0)
404 if (bit_map
[i
].bit
& bits
)
410 brw_print_dirty_count(struct dirty_bit_map
*bit_map
, int32_t bits
)
414 for (i
= 0; i
< 32; i
++) {
415 if (bit_map
[i
].bit
== 0)
418 fprintf(stderr
, "0x%08x: %12d (%s)\n",
419 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
423 /***********************************************************************
426 void brw_validate_state( struct brw_context
*brw
)
428 struct gl_context
*ctx
= &brw
->intel
.ctx
;
429 struct intel_context
*intel
= &brw
->intel
;
430 struct brw_state_flags
*state
= &brw
->state
.dirty
;
431 const struct brw_tracked_state
*atoms
= brw
->prepare_atoms
;
432 int num_atoms
= brw
->num_prepare_atoms
;
435 state
->mesa
|= brw
->intel
.NewGLState
;
436 brw
->intel
.NewGLState
= 0;
438 if (brw
->emit_state_always
) {
444 if (brw
->fragment_program
!= ctx
->FragmentProgram
._Current
) {
445 brw
->fragment_program
= ctx
->FragmentProgram
._Current
;
446 brw
->state
.dirty
.brw
|= BRW_NEW_FRAGMENT_PROGRAM
;
449 if (brw
->vertex_program
!= ctx
->VertexProgram
._Current
) {
450 brw
->vertex_program
= ctx
->VertexProgram
._Current
;
451 brw
->state
.dirty
.brw
|= BRW_NEW_VERTEX_PROGRAM
;
454 if ((state
->mesa
| state
->cache
| state
->brw
) == 0)
457 brw
->intel
.Fallback
= false; /* boolean, not bitfield */
459 /* do prepare stage for all atoms */
460 for (i
= 0; i
< num_atoms
; i
++) {
461 const struct brw_tracked_state
*atom
= &atoms
[i
];
463 if (check_state(state
, &atom
->dirty
)) {
466 if (brw
->intel
.Fallback
)
471 intel_check_front_buffer_rendering(intel
);
473 /* Make sure that the textures which are referenced by the current
474 * brw fragment program are actually present/valid.
475 * If this fails, we can experience GPU lock-ups.
478 const struct brw_fragment_program
*fp
;
479 fp
= brw_fragment_program_const(brw
->fragment_program
);
481 assert((fp
->tex_units_used
& ctx
->Texture
._EnabledUnits
)
482 == fp
->tex_units_used
);
488 void brw_upload_state(struct brw_context
*brw
)
490 struct brw_state_flags
*state
= &brw
->state
.dirty
;
491 const struct brw_tracked_state
*atoms
= brw
->emit_atoms
;
492 int num_atoms
= brw
->num_emit_atoms
;
494 static int dirty_count
= 0;
496 if (unlikely(INTEL_DEBUG
)) {
497 /* Debug version which enforces various sanity checks on the
498 * state flags which are generated and checked to help ensure
499 * state atoms are ordered correctly in the list.
501 struct brw_state_flags examined
, prev
;
502 memset(&examined
, 0, sizeof(examined
));
505 for (i
= 0; i
< num_atoms
; i
++) {
506 const struct brw_tracked_state
*atom
= &atoms
[i
];
507 struct brw_state_flags generated
;
509 if (brw
->intel
.Fallback
)
512 if (check_state(state
, &atom
->dirty
)) {
516 accumulate_state(&examined
, &atom
->dirty
);
518 /* generated = (prev ^ state)
519 * if (examined & generated)
522 xor_states(&generated
, &prev
, state
);
523 assert(!check_state(&examined
, &generated
));
528 for (i
= 0; i
< num_atoms
; i
++) {
529 const struct brw_tracked_state
*atom
= &atoms
[i
];
531 if (brw
->intel
.Fallback
)
534 if (check_state(state
, &atom
->dirty
)) {
540 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
541 brw_update_dirty_count(mesa_bits
, state
->mesa
);
542 brw_update_dirty_count(brw_bits
, state
->brw
);
543 brw_update_dirty_count(cache_bits
, state
->cache
);
544 if (dirty_count
++ % 1000 == 0) {
545 brw_print_dirty_count(mesa_bits
, state
->mesa
);
546 brw_print_dirty_count(brw_bits
, state
->brw
);
547 brw_print_dirty_count(cache_bits
, state
->cache
);
548 fprintf(stderr
, "\n");
552 if (!brw
->intel
.Fallback
)
553 memset(state
, 0, sizeof(*state
));