src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
  67    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
  68
  69    &brw_vs_surfaces,            /* must do before unit */
  70    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  71    &brw_wm_surfaces,            /* must do before samplers and unit */
  72    &brw_wm_binding_table,
  73    &brw_wm_samplers,
  74
  75    /* These set up state for brw_psp_urb_cbs */
  76    &brw_wm_unit,
  77    &brw_sf_vp,
  78    &brw_sf_unit,
  79    &brw_vs_unit,                /* always required, enabled or not */
  80    &brw_clip_unit,
  81    &brw_gs_unit,
  82
  83    /* Command packets:
  84     */
  85    &brw_invarient_state,
  86    &brw_state_base_address,
  87
  88    &brw_binding_table_pointers,
  89    &brw_blend_constant_color,
  90
  91    &brw_depthbuffer,
  92
  93    &brw_polygon_stipple,
  94    &brw_polygon_stipple_offset,
  95
  96    &brw_line_stipple,
  97    &brw_aa_line_parameters,
  98
  99    &brw_psp_urb_cbs,
 100
 101    &brw_drawing_rect,
 102    &brw_indices,
 103    &brw_index_buffer,
 104    &brw_vertices,
 105
 106    &brw_constant_buffer
 107 };
 108
 109 static const struct brw_tracked_state *gen6_atoms[] =
 110 {
 111    &brw_check_fallback,
 112
 113    &brw_wm_input_sizes,
 114    &brw_vs_prog, /* must do before state base address */
 115    &brw_gs_prog, /* must do before state base address */
 116    &brw_wm_prog, /* must do before state base address */
 117
 118    &gen6_clip_vp,
 119    &gen6_sf_vp,
 120
 121    /* Command packets: */
 122    &brw_invarient_state,
 123
 124    /* must do before binding table pointers, cc state ptrs */
 125    &brw_state_base_address,
 126
 127    &brw_cc_vp,
 128    &gen6_viewport_state,        /* must do after *_vp stages */
 129
 130    &gen6_urb,
 131    &gen6_blend_state,           /* must do before cc unit */
 132    &gen6_color_calc_state,      /* must do before cc unit */
 133    &gen6_depth_stencil_state,   /* must do before cc unit */
 134    &gen6_cc_state_pointers,
 135
 136    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 137    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 138    &gen6_vs_constants, /* Before vs_state */
 139    &gen6_wm_constants, /* Before wm_state */
 140
 141    &brw_vs_surfaces,            /* must do before unit */
 142    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 143    &brw_wm_surfaces,            /* must do before samplers and unit */
 144    &brw_wm_binding_table,
 145
 146    &brw_wm_samplers,
 147    &gen6_sampler_state,
 148
 149    &gen6_vs_state,
 150    &gen6_gs_state,
 151    &gen6_clip_state,
 152    &gen6_sf_state,
 153    &gen6_wm_state,
 154
 155    &gen6_scissor_state,
 156
 157    &gen6_binding_table_pointers,
 158
 159    &brw_depthbuffer,
 160
 161    &brw_polygon_stipple,
 162    &brw_polygon_stipple_offset,
 163
 164    &brw_line_stipple,
 165    &brw_aa_line_parameters,
 166
 167    &brw_drawing_rect,
 168
 169    &brw_indices,
 170    &brw_index_buffer,
 171    &brw_vertices,
 172 };
 173
 174 const struct brw_tracked_state *gen7_atoms[] =
 175 {
 176    &brw_check_fallback,
 177
 178    &brw_wm_input_sizes,
 179    &brw_vs_prog,
 180    &brw_gs_prog,
 181    &brw_wm_prog,
 182
 183    /* Command packets: */
 184    &brw_invarient_state,
 185
 186    /* must do before binding table pointers, cc state ptrs */
 187    &brw_state_base_address,
 188
 189    &brw_cc_vp,
 190    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 191    &gen7_sf_clip_viewport,
 192
 193    &gen7_urb,
 194    &gen6_blend_state,           /* must do before cc unit */
 195    &gen6_color_calc_state,      /* must do before cc unit */
 196    &gen6_depth_stencil_state,   /* must do before cc unit */
 197    &gen7_blend_state_pointer,
 198    &gen7_cc_state_pointer,
 199    &gen7_depth_stencil_state_pointer,
 200
 201    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 202    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 203    &gen6_vs_constants, /* Before vs_state */
 204    &gen6_wm_constants, /* Before wm_surfaces and constant_buffer */
 205
 206    &brw_vs_surfaces,            /* must do before unit */
 207    &gen7_wm_constant_surface,   /* must do before wm surfaces/bind bo */
 208    &gen7_wm_surfaces,           /* must do before samplers and unit */
 209    &brw_wm_binding_table,
 210
 211    &gen7_samplers,
 212
 213    &gen7_disable_stages,
 214    &gen7_vs_state,
 215    &gen7_clip_state,
 216    &gen7_sbe_state,
 217    &gen7_sf_state,
 218    &gen7_wm_state,
 219    &gen7_ps_state,
 220
 221    &gen6_scissor_state,
 222
 223    &gen7_depthbuffer,
 224
 225    &brw_polygon_stipple,
 226    &brw_polygon_stipple_offset,
 227
 228    &brw_line_stipple,
 229    &brw_aa_line_parameters,
 230
 231    &brw_drawing_rect,
 232
 233    &brw_indices,
 234    &brw_index_buffer,
 235    &brw_vertices,
 236 };
 237
 238
 239 void brw_init_state( struct brw_context *brw )
 240 {
 241    const struct brw_tracked_state **atoms;
 242    int num_atoms;
 243
 244    brw_init_caches(brw);
 245
 246    if (brw->intel.gen >= 7) {
 247       atoms = gen7_atoms;
 248       num_atoms = ARRAY_SIZE(gen7_atoms);
 249    } else if (brw->intel.gen == 6) {
 250       atoms = gen6_atoms;
 251       num_atoms = ARRAY_SIZE(gen6_atoms);
 252    } else {
 253       atoms = gen4_atoms;
 254       num_atoms = ARRAY_SIZE(gen4_atoms);
 255    }
 256
 257    while (num_atoms--) {
 258       assert((*atoms)->dirty.mesa |
 259              (*atoms)->dirty.brw |
 260              (*atoms)->dirty.cache);
 261
 262       if ((*atoms)->prepare)
 263          brw->prepare_atoms[brw->num_prepare_atoms++] = **atoms;
 264       if ((*atoms)->emit)
 265          brw->emit_atoms[brw->num_emit_atoms++] = **atoms;
 266       atoms++;
 267    }
 268    assert(brw->num_emit_atoms <= ARRAY_SIZE(brw->emit_atoms));
 269    assert(brw->num_prepare_atoms <= ARRAY_SIZE(brw->prepare_atoms));
 270 }
 271
 272
 273 void brw_destroy_state( struct brw_context *brw )
 274 {
 275    brw_destroy_caches(brw);
 276 }
 277
 278 /***********************************************************************
 279  */
 280
 281 static GLuint check_state( const struct brw_state_flags *a,
 282                            const struct brw_state_flags *b )
 283 {
 284    return ((a->mesa & b->mesa) |
 285            (a->brw & b->brw) |
 286            (a->cache & b->cache)) != 0;
 287 }
 288
 289 static void accumulate_state( struct brw_state_flags *a,
 290                               const struct brw_state_flags *b )
 291 {
 292    a->mesa |= b->mesa;
 293    a->brw |= b->brw;
 294    a->cache |= b->cache;
 295 }
 296
 297
 298 static void xor_states( struct brw_state_flags *result,
 299                              const struct brw_state_flags *a,
 300                               const struct brw_state_flags *b )
 301 {
 302    result->mesa = a->mesa ^ b->mesa;
 303    result->brw = a->brw ^ b->brw;
 304    result->cache = a->cache ^ b->cache;
 305 }
 306
 307 struct dirty_bit_map {
 308    uint32_t bit;
 309    char *name;
 310    uint32_t count;
 311 };
 312
 313 #define DEFINE_BIT(name) {name, #name, 0}
 314
 315 static struct dirty_bit_map mesa_bits[] = {
 316    DEFINE_BIT(_NEW_MODELVIEW),
 317    DEFINE_BIT(_NEW_PROJECTION),
 318    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 319    DEFINE_BIT(_NEW_COLOR),
 320    DEFINE_BIT(_NEW_DEPTH),
 321    DEFINE_BIT(_NEW_EVAL),
 322    DEFINE_BIT(_NEW_FOG),
 323    DEFINE_BIT(_NEW_HINT),
 324    DEFINE_BIT(_NEW_LIGHT),
 325    DEFINE_BIT(_NEW_LINE),
 326    DEFINE_BIT(_NEW_PIXEL),
 327    DEFINE_BIT(_NEW_POINT),
 328    DEFINE_BIT(_NEW_POLYGON),
 329    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 330    DEFINE_BIT(_NEW_SCISSOR),
 331    DEFINE_BIT(_NEW_STENCIL),
 332    DEFINE_BIT(_NEW_TEXTURE),
 333    DEFINE_BIT(_NEW_TRANSFORM),
 334    DEFINE_BIT(_NEW_VIEWPORT),
 335    DEFINE_BIT(_NEW_PACKUNPACK),
 336    DEFINE_BIT(_NEW_ARRAY),
 337    DEFINE_BIT(_NEW_RENDERMODE),
 338    DEFINE_BIT(_NEW_BUFFERS),
 339    DEFINE_BIT(_NEW_MULTISAMPLE),
 340    DEFINE_BIT(_NEW_TRACK_MATRIX),
 341    DEFINE_BIT(_NEW_PROGRAM),
 342    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 343    {0, 0, 0}
 344 };
 345
 346 static struct dirty_bit_map brw_bits[] = {
 347    DEFINE_BIT(BRW_NEW_URB_FENCE),
 348    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 349    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 350    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 351    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 352    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 353    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 354    DEFINE_BIT(BRW_NEW_CONTEXT),
 355    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 356    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 357    DEFINE_BIT(BRW_NEW_PSP),
 358    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 359    DEFINE_BIT(BRW_NEW_INDICES),
 360    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 361    DEFINE_BIT(BRW_NEW_VERTICES),
 362    DEFINE_BIT(BRW_NEW_BATCH),
 363    DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
 364    DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
 365    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 366    DEFINE_BIT(BRW_NEW_WM_CONSTBUF),
 367    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 368    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 369    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 370    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 371    {0, 0, 0}
 372 };
 373
 374 static struct dirty_bit_map cache_bits[] = {
 375    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 376    DEFINE_BIT(CACHE_NEW_CC_VP),
 377    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 378    DEFINE_BIT(CACHE_NEW_WM_PROG),
 379    DEFINE_BIT(CACHE_NEW_SAMPLER),
 380    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 381    DEFINE_BIT(CACHE_NEW_SF_PROG),
 382    DEFINE_BIT(CACHE_NEW_SF_VP),
 383    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 384    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 385    DEFINE_BIT(CACHE_NEW_VS_PROG),
 386    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 387    DEFINE_BIT(CACHE_NEW_GS_PROG),
 388    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 389    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 390    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 391    {0, 0, 0}
 392 };
 393
 394
 395 static void
 396 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 397 {
 398    int i;
 399
 400    for (i = 0; i < 32; i++) {
 401       if (bit_map[i].bit == 0)
 402          return;
 403
 404       if (bit_map[i].bit & bits)
 405          bit_map[i].count++;
 406    }
 407 }
 408
 409 static void
 410 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 411 {
 412    int i;
 413
 414    for (i = 0; i < 32; i++) {
 415       if (bit_map[i].bit == 0)
 416          return;
 417
 418       fprintf(stderr, "0x%08x: %12d (%s)\n",
 419               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 420    }
 421 }
 422
 423 /***********************************************************************
 424  * Emit all state:
 425  */
 426 void brw_validate_state( struct brw_context *brw )
 427 {
 428    struct gl_context *ctx = &brw->intel.ctx;
 429    struct intel_context *intel = &brw->intel;
 430    struct brw_state_flags *state = &brw->state.dirty;
 431    const struct brw_tracked_state *atoms = brw->prepare_atoms;
 432    int num_atoms = brw->num_prepare_atoms;
 433    GLuint i;
 434
 435    state->mesa |= brw->intel.NewGLState;
 436    brw->intel.NewGLState = 0;
 437
 438    if (brw->emit_state_always) {
 439       state->mesa |= ~0;
 440       state->brw |= ~0;
 441       state->cache |= ~0;
 442    }
 443
 444    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 445       brw->fragment_program = ctx->FragmentProgram._Current;
 446       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 447    }
 448
 449    if (brw->vertex_program != ctx->VertexProgram._Current) {
 450       brw->vertex_program = ctx->VertexProgram._Current;
 451       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 452    }
 453
 454    if ((state->mesa | state->cache | state->brw) == 0)
 455       return;
 456
 457    brw->intel.Fallback = false; /* boolean, not bitfield */
 458
 459    /* do prepare stage for all atoms */
 460    for (i = 0; i < num_atoms; i++) {
 461       const struct brw_tracked_state *atom = &atoms[i];
 462
 463       if (check_state(state, &atom->dirty)) {
 464          atom->prepare(brw);
 465
 466          if (brw->intel.Fallback)
 467             break;
 468       }
 469    }
 470
 471    intel_check_front_buffer_rendering(intel);
 472
 473    /* Make sure that the textures which are referenced by the current
 474     * brw fragment program are actually present/valid.
 475     * If this fails, we can experience GPU lock-ups.
 476     */
 477    {
 478       const struct brw_fragment_program *fp;
 479       fp = brw_fragment_program_const(brw->fragment_program);
 480       if (fp) {
 481          assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
 482                 == fp->tex_units_used);
 483       }
 484    }
 485 }
 486
 487
 488 void brw_upload_state(struct brw_context *brw)
 489 {
 490    struct brw_state_flags *state = &brw->state.dirty;
 491    const struct brw_tracked_state *atoms = brw->emit_atoms;
 492    int num_atoms = brw->num_emit_atoms;
 493    int i;
 494    static int dirty_count = 0;
 495
 496    if (unlikely(INTEL_DEBUG)) {
 497       /* Debug version which enforces various sanity checks on the
 498        * state flags which are generated and checked to help ensure
 499        * state atoms are ordered correctly in the list.
 500        */
 501       struct brw_state_flags examined, prev;
 502       memset(&examined, 0, sizeof(examined));
 503       prev = *state;
 504
 505       for (i = 0; i < num_atoms; i++) {
 506          const struct brw_tracked_state *atom = &atoms[i];
 507          struct brw_state_flags generated;
 508
 509          if (brw->intel.Fallback)
 510             break;
 511
 512          if (check_state(state, &atom->dirty)) {
 513             atom->emit(brw);
 514          }
 515
 516          accumulate_state(&examined, &atom->dirty);
 517
 518          /* generated = (prev ^ state)
 519           * if (examined & generated)
 520           *     fail;
 521           */
 522          xor_states(&generated, &prev, state);
 523          assert(!check_state(&examined, &generated));
 524          prev = *state;
 525       }
 526    }
 527    else {
 528       for (i = 0; i < num_atoms; i++) {
 529          const struct brw_tracked_state *atom = &atoms[i];
 530
 531          if (brw->intel.Fallback)
 532             break;
 533
 534          if (check_state(state, &atom->dirty)) {
 535             atom->emit(brw);
 536          }
 537       }
 538    }
 539
 540    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 541       brw_update_dirty_count(mesa_bits, state->mesa);
 542       brw_update_dirty_count(brw_bits, state->brw);
 543       brw_update_dirty_count(cache_bits, state->cache);
 544       if (dirty_count++ % 1000 == 0) {
 545          brw_print_dirty_count(mesa_bits, state->mesa);
 546          brw_print_dirty_count(brw_bits, state->brw);
 547          brw_print_dirty_count(cache_bits, state->cache);
 548          fprintf(stderr, "\n");
 549       }
 550    }
 551
 552    if (!brw->intel.Fallback)
 553       memset(state, 0, sizeof(*state));
 554 }