src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices, /* must come before brw_vertices */
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_gs_push_constants, /* Before gs_state */
 132    &gen6_wm_push_constants, /* Before wm_state */
 133
 134    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 135     * table upload must be last.
 136     */
 137    &brw_vs_pull_constants,
 138    &brw_vs_ubo_surfaces,
 139    &brw_gs_pull_constants,
 140    &brw_gs_ubo_surfaces,
 141    &brw_wm_pull_constants,
 142    &brw_wm_ubo_surfaces,
 143    &gen6_renderbuffer_surfaces,
 144    &brw_texture_surfaces,
 145    &gen6_sol_surface,
 146    &brw_vs_binding_table,
 147    &gen6_gs_binding_table,
 148    &brw_wm_binding_table,
 149
 150    &brw_fs_samplers,
 151    &brw_vs_samplers,
 152    &brw_gs_samplers,
 153    &gen6_sampler_state,
 154    &gen6_multisample_state,
 155
 156    &gen6_vs_state,
 157    &gen6_gs_state,
 158    &gen6_clip_state,
 159    &gen6_sf_state,
 160    &gen6_wm_state,
 161
 162    &gen6_scissor_state,
 163
 164    &gen6_binding_table_pointers,
 165
 166    &brw_depthbuffer,
 167
 168    &brw_polygon_stipple,
 169    &brw_polygon_stipple_offset,
 170
 171    &brw_line_stipple,
 172    &brw_aa_line_parameters,
 173
 174    &brw_drawing_rect,
 175
 176    &brw_indices, /* must come before brw_vertices */
 177    &brw_index_buffer,
 178    &brw_vertices,
 179 };
 180
 181 static const struct brw_tracked_state *gen7_atoms[] =
 182 {
 183    &brw_vs_prog,
 184    &brw_gs_prog,
 185    &brw_wm_prog,
 186
 187    /* Command packets: */
 188
 189    /* must do before binding table pointers, cc state ptrs */
 190    &brw_state_base_address,
 191
 192    &brw_cc_vp,
 193    &gen7_sf_clip_viewport,
 194
 195    &gen7_push_constant_space,
 196    &gen7_urb,
 197    &gen6_blend_state,           /* must do before cc unit */
 198    &gen6_color_calc_state,      /* must do before cc unit */
 199    &gen6_depth_stencil_state,   /* must do before cc unit */
 200
 201    &gen6_vs_push_constants, /* Before vs_state */
 202    &gen6_gs_push_constants, /* Before gs_state */
 203    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 204
 205    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 206     * table upload must be last.
 207     */
 208    &brw_vs_pull_constants,
 209    &brw_vs_ubo_surfaces,
 210    &brw_vs_abo_surfaces,
 211    &brw_gs_pull_constants,
 212    &brw_gs_ubo_surfaces,
 213    &brw_gs_abo_surfaces,
 214    &brw_wm_pull_constants,
 215    &brw_wm_ubo_surfaces,
 216    &brw_wm_abo_surfaces,
 217    &gen6_renderbuffer_surfaces,
 218    &brw_texture_surfaces,
 219    &brw_vs_binding_table,
 220    &brw_gs_binding_table,
 221    &brw_wm_binding_table,
 222
 223    &brw_fs_samplers,
 224    &brw_vs_samplers,
 225    &brw_gs_samplers,
 226    &gen6_multisample_state,
 227
 228    &gen7_disable_stages,
 229    &gen7_vs_state,
 230    &gen7_gs_state,
 231    &gen7_sol_state,
 232    &gen7_clip_state,
 233    &gen7_sbe_state,
 234    &gen7_sf_state,
 235    &gen7_wm_state,
 236    &gen7_ps_state,
 237
 238    &gen6_scissor_state,
 239
 240    &gen7_depthbuffer,
 241
 242    &brw_polygon_stipple,
 243    &brw_polygon_stipple_offset,
 244
 245    &brw_line_stipple,
 246    &brw_aa_line_parameters,
 247
 248    &brw_drawing_rect,
 249
 250    &brw_indices, /* must come before brw_vertices */
 251    &brw_index_buffer,
 252    &brw_vertices,
 253
 254    &haswell_cut_index,
 255 };
 256
 257 static const struct brw_tracked_state *gen8_atoms[] =
 258 {
 259    &brw_vs_prog,
 260    &brw_gs_prog,
 261    &brw_wm_prog,
 262
 263    /* Command packets: */
 264    &gen8_state_base_address,
 265
 266    &brw_cc_vp,
 267    &gen8_sf_clip_viewport,
 268
 269    &gen7_push_constant_space,
 270    &gen7_urb,
 271    &gen8_blend_state,
 272    &gen6_color_calc_state,
 273
 274    &gen6_vs_push_constants, /* Before vs_state */
 275    &gen6_gs_push_constants, /* Before gs_state */
 276    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 277
 278    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 279     * table upload must be last.
 280     */
 281    &brw_vs_pull_constants,
 282    &brw_vs_ubo_surfaces,
 283    &brw_vs_abo_surfaces,
 284    &brw_gs_pull_constants,
 285    &brw_gs_ubo_surfaces,
 286    &brw_gs_abo_surfaces,
 287    &brw_wm_pull_constants,
 288    &brw_wm_ubo_surfaces,
 289    &brw_wm_abo_surfaces,
 290    &gen6_renderbuffer_surfaces,
 291    &brw_texture_surfaces,
 292    &brw_vs_binding_table,
 293    &brw_gs_binding_table,
 294    &brw_wm_binding_table,
 295
 296    &brw_fs_samplers,
 297    &brw_vs_samplers,
 298    &brw_gs_samplers,
 299    &gen8_multisample_state,
 300
 301    &gen8_disable_stages,
 302    &gen8_vs_state,
 303    &gen8_gs_state,
 304    &gen8_sol_state,
 305    &gen6_clip_state,
 306    &gen8_raster_state,
 307    &gen8_sbe_state,
 308    &gen8_sf_state,
 309    &gen8_ps_blend,
 310    &gen8_ps_extra,
 311    &gen8_ps_state,
 312    &gen8_wm_depth_stencil,
 313    &gen8_wm_state,
 314
 315    &gen6_scissor_state,
 316
 317    &gen7_depthbuffer,
 318
 319    &brw_polygon_stipple,
 320    &brw_polygon_stipple_offset,
 321
 322    &brw_line_stipple,
 323    &brw_aa_line_parameters,
 324
 325    &brw_drawing_rect,
 326
 327    &gen8_vf_topology,
 328
 329    &brw_indices,
 330    &gen8_index_buffer,
 331    &gen8_vertices,
 332
 333    &haswell_cut_index,
 334    &gen8_pma_fix,
 335 };
 336
 337 static void
 338 brw_upload_initial_gpu_state(struct brw_context *brw)
 339 {
 340    /* On platforms with hardware contexts, we can set our initial GPU state
 341     * right away rather than doing it via state atoms.  This saves a small
 342     * amount of overhead on every draw call.
 343     */
 344    if (!brw->hw_ctx)
 345       return;
 346
 347    brw_upload_invariant_state(brw);
 348
 349    if (brw->gen >= 8) {
 350       gen8_emit_3dstate_sample_pattern(brw);
 351    }
 352 }
 353
 354 void brw_init_state( struct brw_context *brw )
 355 {
 356    struct gl_context *ctx = &brw->ctx;
 357    const struct brw_tracked_state **atoms;
 358    int num_atoms;
 359
 360    brw_init_caches(brw);
 361
 362    if (brw->gen >= 8) {
 363       atoms = gen8_atoms;
 364       num_atoms = ARRAY_SIZE(gen8_atoms);
 365    } else if (brw->gen == 7) {
 366       atoms = gen7_atoms;
 367       num_atoms = ARRAY_SIZE(gen7_atoms);
 368    } else if (brw->gen == 6) {
 369       atoms = gen6_atoms;
 370       num_atoms = ARRAY_SIZE(gen6_atoms);
 371    } else {
 372       atoms = gen4_atoms;
 373       num_atoms = ARRAY_SIZE(gen4_atoms);
 374    }
 375
 376    brw->atoms = atoms;
 377    brw->num_atoms = num_atoms;
 378
 379    while (num_atoms--) {
 380       assert((*atoms)->dirty.mesa |
 381              (*atoms)->dirty.brw |
 382              (*atoms)->dirty.cache);
 383       assert((*atoms)->emit);
 384       atoms++;
 385    }
 386
 387    brw_upload_initial_gpu_state(brw);
 388
 389    brw->state.dirty.mesa = ~0;
 390    brw->state.dirty.brw = ~0ull;
 391
 392    /* ~0 is a nonsensical value which won't match anything we program, so
 393     * the programming will take effect on the first time around.
 394     */
 395    brw->pma_stall_bits = ~0;
 396
 397    /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
 398     * dirty flags.
 399     */
 400    STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->state.dirty.brw));
 401
 402    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 403    ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
 404    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 405    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 406    ctx->DriverFlags.NewTextureBuffer = BRW_NEW_TEXTURE_BUFFER;
 407    ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 408 }
 409
 410
 411 void brw_destroy_state( struct brw_context *brw )
 412 {
 413    brw_destroy_caches(brw);
 414 }
 415
 416 /***********************************************************************
 417  */
 418
 419 static bool
 420 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 421 {
 422    return ((a->mesa & b->mesa) |
 423            (a->brw & b->brw) |
 424            (a->cache & b->cache)) != 0;
 425 }
 426
 427 static void accumulate_state( struct brw_state_flags *a,
 428                               const struct brw_state_flags *b )
 429 {
 430    a->mesa |= b->mesa;
 431    a->brw |= b->brw;
 432    a->cache |= b->cache;
 433 }
 434
 435
 436 static void xor_states( struct brw_state_flags *result,
 437                              const struct brw_state_flags *a,
 438                               const struct brw_state_flags *b )
 439 {
 440    result->mesa = a->mesa ^ b->mesa;
 441    result->brw = a->brw ^ b->brw;
 442    result->cache = a->cache ^ b->cache;
 443 }
 444
 445 struct dirty_bit_map {
 446    uint64_t bit;
 447    char *name;
 448    uint32_t count;
 449 };
 450
 451 #define DEFINE_BIT(name) {name, #name, 0}
 452
 453 static struct dirty_bit_map mesa_bits[] = {
 454    DEFINE_BIT(_NEW_MODELVIEW),
 455    DEFINE_BIT(_NEW_PROJECTION),
 456    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 457    DEFINE_BIT(_NEW_COLOR),
 458    DEFINE_BIT(_NEW_DEPTH),
 459    DEFINE_BIT(_NEW_EVAL),
 460    DEFINE_BIT(_NEW_FOG),
 461    DEFINE_BIT(_NEW_HINT),
 462    DEFINE_BIT(_NEW_LIGHT),
 463    DEFINE_BIT(_NEW_LINE),
 464    DEFINE_BIT(_NEW_PIXEL),
 465    DEFINE_BIT(_NEW_POINT),
 466    DEFINE_BIT(_NEW_POLYGON),
 467    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 468    DEFINE_BIT(_NEW_SCISSOR),
 469    DEFINE_BIT(_NEW_STENCIL),
 470    DEFINE_BIT(_NEW_TEXTURE),
 471    DEFINE_BIT(_NEW_TRANSFORM),
 472    DEFINE_BIT(_NEW_VIEWPORT),
 473    DEFINE_BIT(_NEW_ARRAY),
 474    DEFINE_BIT(_NEW_RENDERMODE),
 475    DEFINE_BIT(_NEW_BUFFERS),
 476    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 477    DEFINE_BIT(_NEW_MULTISAMPLE),
 478    DEFINE_BIT(_NEW_TRACK_MATRIX),
 479    DEFINE_BIT(_NEW_PROGRAM),
 480    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 481    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 482    DEFINE_BIT(_NEW_FRAG_CLAMP),
 483    /* Avoid sign extension problems. */
 484    {(unsigned) _NEW_VARYING_VP_INPUTS, "_NEW_VARYING_VP_INPUTS", 0},
 485    {0, 0, 0}
 486 };
 487
 488 static struct dirty_bit_map brw_bits[] = {
 489    DEFINE_BIT(BRW_NEW_URB_FENCE),
 490    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 491    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 492    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 493    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 494    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 495    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 496    DEFINE_BIT(BRW_NEW_CONTEXT),
 497    DEFINE_BIT(BRW_NEW_PSP),
 498    DEFINE_BIT(BRW_NEW_SURFACES),
 499    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 500    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 501    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 502    DEFINE_BIT(BRW_NEW_INDICES),
 503    DEFINE_BIT(BRW_NEW_VERTICES),
 504    DEFINE_BIT(BRW_NEW_BATCH),
 505    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 506    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 507    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 508    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 509    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 510    DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
 511    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 512    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 513    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 514    DEFINE_BIT(BRW_NEW_STATS_WM),
 515    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 516    DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
 517    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 518    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 519    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 520    DEFINE_BIT(BRW_NEW_NUM_SAMPLES),
 521    DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER),
 522    DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE),
 523    DEFINE_BIT(BRW_NEW_CC_VP),
 524    DEFINE_BIT(BRW_NEW_SF_VP),
 525    DEFINE_BIT(BRW_NEW_CLIP_VP),
 526    DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE),
 527    {0, 0, 0}
 528 };
 529
 530 static struct dirty_bit_map cache_bits[] = {
 531    DEFINE_BIT(CACHE_NEW_WM_PROG),
 532    DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG),
 533    DEFINE_BIT(CACHE_NEW_SF_PROG),
 534    DEFINE_BIT(CACHE_NEW_VS_PROG),
 535    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 536    DEFINE_BIT(CACHE_NEW_GS_PROG),
 537    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 538    {0, 0, 0}
 539 };
 540
 541
 542 static void
 543 brw_update_dirty_count(struct dirty_bit_map *bit_map, uint64_t bits)
 544 {
 545    for (int i = 0; bit_map[i].bit != 0; i++) {
 546       if (bit_map[i].bit & bits)
 547          bit_map[i].count++;
 548    }
 549 }
 550
 551 static void
 552 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 553 {
 554    for (int i = 0; bit_map[i].bit != 0; i++) {
 555       fprintf(stderr, "0x%016lx: %12d (%s)\n",
 556               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 557    }
 558 }
 559
 560 /***********************************************************************
 561  * Emit all state:
 562  */
 563 void brw_upload_state(struct brw_context *brw)
 564 {
 565    struct gl_context *ctx = &brw->ctx;
 566    struct brw_state_flags *state = &brw->state.dirty;
 567    int i;
 568    static int dirty_count = 0;
 569
 570    state->mesa |= brw->NewGLState;
 571    brw->NewGLState = 0;
 572
 573    state->brw |= ctx->NewDriverState;
 574    ctx->NewDriverState = 0;
 575
 576    if (0) {
 577       /* Always re-emit all state. */
 578       state->mesa |= ~0;
 579       state->brw |= ~0ull;
 580       state->cache |= ~0;
 581    }
 582
 583    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 584       brw->fragment_program = ctx->FragmentProgram._Current;
 585       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 586    }
 587
 588    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 589       brw->geometry_program = ctx->GeometryProgram._Current;
 590       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 591    }
 592
 593    if (brw->vertex_program != ctx->VertexProgram._Current) {
 594       brw->vertex_program = ctx->VertexProgram._Current;
 595       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 596    }
 597
 598    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 599       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 600       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 601    }
 602
 603    if (brw->num_samples != ctx->DrawBuffer->Visual.samples) {
 604       brw->num_samples = ctx->DrawBuffer->Visual.samples;
 605       brw->state.dirty.brw |= BRW_NEW_NUM_SAMPLES;
 606    }
 607
 608    if ((state->mesa | state->cache | state->brw) == 0)
 609       return;
 610
 611    if (unlikely(INTEL_DEBUG)) {
 612       /* Debug version which enforces various sanity checks on the
 613        * state flags which are generated and checked to help ensure
 614        * state atoms are ordered correctly in the list.
 615        */
 616       struct brw_state_flags examined, prev;
 617       memset(&examined, 0, sizeof(examined));
 618       prev = *state;
 619
 620       for (i = 0; i < brw->num_atoms; i++) {
 621          const struct brw_tracked_state *atom = brw->atoms[i];
 622          struct brw_state_flags generated;
 623
 624          if (check_state(state, &atom->dirty)) {
 625             atom->emit(brw);
 626          }
 627
 628          accumulate_state(&examined, &atom->dirty);
 629
 630          /* generated = (prev ^ state)
 631           * if (examined & generated)
 632           *     fail;
 633           */
 634          xor_states(&generated, &prev, state);
 635          assert(!check_state(&examined, &generated));
 636          prev = *state;
 637       }
 638    }
 639    else {
 640       for (i = 0; i < brw->num_atoms; i++) {
 641          const struct brw_tracked_state *atom = brw->atoms[i];
 642
 643          if (check_state(state, &atom->dirty)) {
 644             atom->emit(brw);
 645          }
 646       }
 647    }
 648
 649    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 650       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 651       STATIC_ASSERT(ARRAY_SIZE(cache_bits) == BRW_MAX_CACHE + 1);
 652
 653       brw_update_dirty_count(mesa_bits, state->mesa);
 654       brw_update_dirty_count(brw_bits, state->brw);
 655       brw_update_dirty_count(cache_bits, state->cache);
 656       if (dirty_count++ % 1000 == 0) {
 657          brw_print_dirty_count(mesa_bits);
 658          brw_print_dirty_count(brw_bits);
 659          brw_print_dirty_count(cache_bits);
 660          fprintf(stderr, "\n");
 661       }
 662    }
 663 }
 664
 665
 666 /**
 667  * Clear dirty bits to account for the fact that the state emitted by
 668  * brw_upload_state() has been committed to the hardware.  This is a separate
 669  * call from brw_upload_state() because it's possible that after the call to
 670  * brw_upload_state(), we will discover that we've run out of aperture space,
 671  * and need to rewind the batch buffer to the state it had before the
 672  * brw_upload_state() call.
 673  */
 674 void
 675 brw_clear_dirty_bits(struct brw_context *brw)
 676 {
 677    struct brw_state_flags *state = &brw->state.dirty;
 678    memset(state, 0, sizeof(*state));
 679 }