2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "drivers/common/meta.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_buffers.h"
40 static const struct brw_tracked_state
*gen4_atoms
[] =
42 &brw_vs_prog
, /* must do before GS prog, state base address. */
43 &brw_ff_gs_prog
, /* must do before state base address */
45 &brw_interpolation_map
,
47 &brw_clip_prog
, /* must do before state base address */
48 &brw_sf_prog
, /* must do before state base address */
49 &brw_wm_prog
, /* must do before state base address */
51 /* Once all the programs are done, we know how large urb entry
52 * sizes need to be and can decide if we need to change the urb
56 &brw_recalculate_urb_fence
,
61 /* Surface state setup. Must come before the VS/WM unit. The binding
62 * table upload must be last.
64 &brw_vs_pull_constants
,
65 &brw_wm_pull_constants
,
66 &brw_renderbuffer_surfaces
,
67 &brw_texture_surfaces
,
68 &brw_vs_binding_table
,
69 &brw_wm_binding_table
,
74 /* These set up state for brw_psp_urb_cbs */
78 &brw_vs_unit
, /* always required, enabled or not */
85 &brw_state_base_address
,
87 &brw_binding_table_pointers
,
88 &brw_blend_constant_color
,
93 &brw_polygon_stipple_offset
,
96 &brw_aa_line_parameters
,
108 static const struct brw_tracked_state
*gen6_atoms
[] =
110 &brw_vs_prog
, /* must do before state base address */
111 &brw_ff_gs_prog
, /* must do before state base address */
112 &brw_wm_prog
, /* must do before state base address */
117 /* Command packets: */
119 /* must do before binding table pointers, cc state ptrs */
120 &brw_state_base_address
,
123 &gen6_viewport_state
, /* must do after *_vp stages */
126 &gen6_blend_state
, /* must do before cc unit */
127 &gen6_color_calc_state
, /* must do before cc unit */
128 &gen6_depth_stencil_state
, /* must do before cc unit */
130 &gen6_vs_push_constants
, /* Before vs_state */
131 &gen6_wm_push_constants
, /* Before wm_state */
133 /* Surface state setup. Must come before the VS/WM unit. The binding
134 * table upload must be last.
136 &brw_vs_pull_constants
,
137 &brw_vs_ubo_surfaces
,
138 &brw_wm_pull_constants
,
139 &brw_wm_ubo_surfaces
,
140 &gen6_renderbuffer_surfaces
,
141 &brw_texture_surfaces
,
143 &brw_vs_binding_table
,
144 &gen6_gs_binding_table
,
145 &brw_wm_binding_table
,
150 &gen6_multisample_state
,
160 &gen6_binding_table_pointers
,
164 &brw_polygon_stipple
,
165 &brw_polygon_stipple_offset
,
168 &brw_aa_line_parameters
,
177 static const struct brw_tracked_state
*gen7_atoms
[] =
183 /* Command packets: */
185 /* must do before binding table pointers, cc state ptrs */
186 &brw_state_base_address
,
189 &gen7_cc_viewport_state_pointer
, /* must do after brw_cc_vp */
190 &gen7_sf_clip_viewport
,
192 &gen7_push_constant_space
,
194 &gen6_blend_state
, /* must do before cc unit */
195 &gen6_color_calc_state
, /* must do before cc unit */
196 &gen6_depth_stencil_state
, /* must do before cc unit */
198 &gen6_vs_push_constants
, /* Before vs_state */
199 &gen7_gs_push_constants
, /* Before gs_state */
200 &gen6_wm_push_constants
, /* Before wm_surfaces and constant_buffer */
202 /* Surface state setup. Must come before the VS/WM unit. The binding
203 * table upload must be last.
205 &brw_vs_pull_constants
,
206 &brw_vs_ubo_surfaces
,
207 &brw_vs_abo_surfaces
,
208 &brw_gs_pull_constants
,
209 &brw_gs_ubo_surfaces
,
210 &brw_gs_abo_surfaces
,
211 &brw_wm_pull_constants
,
212 &brw_wm_ubo_surfaces
,
213 &brw_wm_abo_surfaces
,
214 &gen6_renderbuffer_surfaces
,
215 &brw_texture_surfaces
,
216 &brw_vs_binding_table
,
217 &brw_gs_binding_table
,
218 &brw_wm_binding_table
,
223 &gen6_multisample_state
,
225 &gen7_disable_stages
,
239 &brw_polygon_stipple
,
240 &brw_polygon_stipple_offset
,
243 &brw_aa_line_parameters
,
255 brw_upload_initial_gpu_state(struct brw_context
*brw
)
257 /* On platforms with hardware contexts, we can set our initial GPU state
258 * right away rather than doing it via state atoms. This saves a small
259 * amount of overhead on every draw call.
264 brw_upload_invariant_state(brw
);
267 void brw_init_state( struct brw_context
*brw
)
269 struct gl_context
*ctx
= &brw
->ctx
;
270 const struct brw_tracked_state
**atoms
;
273 brw_init_caches(brw
);
277 num_atoms
= ARRAY_SIZE(gen7_atoms
);
278 } else if (brw
->gen
== 6) {
280 num_atoms
= ARRAY_SIZE(gen6_atoms
);
283 num_atoms
= ARRAY_SIZE(gen4_atoms
);
287 brw
->num_atoms
= num_atoms
;
289 while (num_atoms
--) {
290 assert((*atoms
)->dirty
.mesa
|
291 (*atoms
)->dirty
.brw
|
292 (*atoms
)->dirty
.cache
);
293 assert((*atoms
)->emit
);
297 brw_upload_initial_gpu_state(brw
);
299 brw
->state
.dirty
.mesa
= ~0;
300 brw
->state
.dirty
.brw
= ~0;
302 /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
305 STATIC_ASSERT(BRW_NUM_STATE_BITS
<= 8 * sizeof(brw
->state
.dirty
.brw
));
307 ctx
->DriverFlags
.NewTransformFeedback
= BRW_NEW_TRANSFORM_FEEDBACK
;
308 ctx
->DriverFlags
.NewRasterizerDiscard
= BRW_NEW_RASTERIZER_DISCARD
;
309 ctx
->DriverFlags
.NewUniformBuffer
= BRW_NEW_UNIFORM_BUFFER
;
310 ctx
->DriverFlags
.NewAtomicBuffer
= BRW_NEW_ATOMIC_BUFFER
;
314 void brw_destroy_state( struct brw_context
*brw
)
316 brw_destroy_caches(brw
);
319 /***********************************************************************
323 check_state(const struct brw_state_flags
*a
, const struct brw_state_flags
*b
)
325 return ((a
->mesa
& b
->mesa
) |
327 (a
->cache
& b
->cache
)) != 0;
330 static void accumulate_state( struct brw_state_flags
*a
,
331 const struct brw_state_flags
*b
)
335 a
->cache
|= b
->cache
;
339 static void xor_states( struct brw_state_flags
*result
,
340 const struct brw_state_flags
*a
,
341 const struct brw_state_flags
*b
)
343 result
->mesa
= a
->mesa
^ b
->mesa
;
344 result
->brw
= a
->brw
^ b
->brw
;
345 result
->cache
= a
->cache
^ b
->cache
;
348 struct dirty_bit_map
{
354 #define DEFINE_BIT(name) {name, #name, 0}
356 static struct dirty_bit_map mesa_bits
[] = {
357 DEFINE_BIT(_NEW_MODELVIEW
),
358 DEFINE_BIT(_NEW_PROJECTION
),
359 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
360 DEFINE_BIT(_NEW_COLOR
),
361 DEFINE_BIT(_NEW_DEPTH
),
362 DEFINE_BIT(_NEW_EVAL
),
363 DEFINE_BIT(_NEW_FOG
),
364 DEFINE_BIT(_NEW_HINT
),
365 DEFINE_BIT(_NEW_LIGHT
),
366 DEFINE_BIT(_NEW_LINE
),
367 DEFINE_BIT(_NEW_PIXEL
),
368 DEFINE_BIT(_NEW_POINT
),
369 DEFINE_BIT(_NEW_POLYGON
),
370 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
371 DEFINE_BIT(_NEW_SCISSOR
),
372 DEFINE_BIT(_NEW_STENCIL
),
373 DEFINE_BIT(_NEW_TEXTURE
),
374 DEFINE_BIT(_NEW_TRANSFORM
),
375 DEFINE_BIT(_NEW_VIEWPORT
),
376 DEFINE_BIT(_NEW_ARRAY
),
377 DEFINE_BIT(_NEW_RENDERMODE
),
378 DEFINE_BIT(_NEW_BUFFERS
),
379 DEFINE_BIT(_NEW_CURRENT_ATTRIB
),
380 DEFINE_BIT(_NEW_MULTISAMPLE
),
381 DEFINE_BIT(_NEW_TRACK_MATRIX
),
382 DEFINE_BIT(_NEW_PROGRAM
),
383 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
384 DEFINE_BIT(_NEW_BUFFER_OBJECT
),
385 DEFINE_BIT(_NEW_FRAG_CLAMP
),
386 DEFINE_BIT(_NEW_VARYING_VP_INPUTS
),
390 static struct dirty_bit_map brw_bits
[] = {
391 DEFINE_BIT(BRW_NEW_URB_FENCE
),
392 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
393 DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM
),
394 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
395 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS
),
396 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
397 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
398 DEFINE_BIT(BRW_NEW_CONTEXT
),
399 DEFINE_BIT(BRW_NEW_PSP
),
400 DEFINE_BIT(BRW_NEW_SURFACES
),
401 DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE
),
402 DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE
),
403 DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE
),
404 DEFINE_BIT(BRW_NEW_INDICES
),
405 DEFINE_BIT(BRW_NEW_VERTICES
),
406 DEFINE_BIT(BRW_NEW_BATCH
),
407 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
408 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
409 DEFINE_BIT(BRW_NEW_GS_CONSTBUF
),
410 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
411 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
412 DEFINE_BIT(BRW_NEW_VUE_MAP_VS
),
413 DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT
),
414 DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK
),
415 DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD
),
416 DEFINE_BIT(BRW_NEW_STATS_WM
),
417 DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER
),
418 DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER
),
419 DEFINE_BIT(BRW_NEW_META_IN_PROGRESS
),
420 DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP
),
421 DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
425 static struct dirty_bit_map cache_bits
[] = {
426 DEFINE_BIT(CACHE_NEW_CC_VP
),
427 DEFINE_BIT(CACHE_NEW_CC_UNIT
),
428 DEFINE_BIT(CACHE_NEW_WM_PROG
),
429 DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG
),
430 DEFINE_BIT(CACHE_NEW_BLORP_CONST_COLOR_PROG
),
431 DEFINE_BIT(CACHE_NEW_SAMPLER
),
432 DEFINE_BIT(CACHE_NEW_WM_UNIT
),
433 DEFINE_BIT(CACHE_NEW_SF_PROG
),
434 DEFINE_BIT(CACHE_NEW_SF_VP
),
435 DEFINE_BIT(CACHE_NEW_SF_UNIT
),
436 DEFINE_BIT(CACHE_NEW_VS_UNIT
),
437 DEFINE_BIT(CACHE_NEW_VS_PROG
),
438 DEFINE_BIT(CACHE_NEW_FF_GS_UNIT
),
439 DEFINE_BIT(CACHE_NEW_FF_GS_PROG
),
440 DEFINE_BIT(CACHE_NEW_GS_PROG
),
441 DEFINE_BIT(CACHE_NEW_CLIP_VP
),
442 DEFINE_BIT(CACHE_NEW_CLIP_UNIT
),
443 DEFINE_BIT(CACHE_NEW_CLIP_PROG
),
449 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, int32_t bits
)
453 for (i
= 0; i
< 32; i
++) {
454 if (bit_map
[i
].bit
== 0)
457 if (bit_map
[i
].bit
& bits
)
463 brw_print_dirty_count(struct dirty_bit_map
*bit_map
)
467 for (i
= 0; i
< 32; i
++) {
468 if (bit_map
[i
].bit
== 0)
471 fprintf(stderr
, "0x%08x: %12d (%s)\n",
472 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
476 /***********************************************************************
479 void brw_upload_state(struct brw_context
*brw
)
481 struct gl_context
*ctx
= &brw
->ctx
;
482 struct brw_state_flags
*state
= &brw
->state
.dirty
;
484 static int dirty_count
= 0;
486 state
->mesa
|= brw
->NewGLState
;
489 state
->brw
|= ctx
->NewDriverState
;
490 ctx
->NewDriverState
= 0;
493 /* Always re-emit all state. */
499 if (brw
->fragment_program
!= ctx
->FragmentProgram
._Current
) {
500 brw
->fragment_program
= ctx
->FragmentProgram
._Current
;
501 brw
->state
.dirty
.brw
|= BRW_NEW_FRAGMENT_PROGRAM
;
504 if (brw
->geometry_program
!= ctx
->GeometryProgram
._Current
) {
505 brw
->geometry_program
= ctx
->GeometryProgram
._Current
;
506 brw
->state
.dirty
.brw
|= BRW_NEW_GEOMETRY_PROGRAM
;
509 if (brw
->vertex_program
!= ctx
->VertexProgram
._Current
) {
510 brw
->vertex_program
= ctx
->VertexProgram
._Current
;
511 brw
->state
.dirty
.brw
|= BRW_NEW_VERTEX_PROGRAM
;
514 if (brw
->meta_in_progress
!= _mesa_meta_in_progress(ctx
)) {
515 brw
->meta_in_progress
= _mesa_meta_in_progress(ctx
);
516 brw
->state
.dirty
.brw
|= BRW_NEW_META_IN_PROGRESS
;
519 if ((state
->mesa
| state
->cache
| state
->brw
) == 0)
522 intel_check_front_buffer_rendering(brw
);
524 if (unlikely(INTEL_DEBUG
)) {
525 /* Debug version which enforces various sanity checks on the
526 * state flags which are generated and checked to help ensure
527 * state atoms are ordered correctly in the list.
529 struct brw_state_flags examined
, prev
;
530 memset(&examined
, 0, sizeof(examined
));
533 for (i
= 0; i
< brw
->num_atoms
; i
++) {
534 const struct brw_tracked_state
*atom
= brw
->atoms
[i
];
535 struct brw_state_flags generated
;
537 if (check_state(state
, &atom
->dirty
)) {
541 accumulate_state(&examined
, &atom
->dirty
);
543 /* generated = (prev ^ state)
544 * if (examined & generated)
547 xor_states(&generated
, &prev
, state
);
548 assert(!check_state(&examined
, &generated
));
553 for (i
= 0; i
< brw
->num_atoms
; i
++) {
554 const struct brw_tracked_state
*atom
= brw
->atoms
[i
];
556 if (check_state(state
, &atom
->dirty
)) {
562 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
563 STATIC_ASSERT(ARRAY_SIZE(brw_bits
) == BRW_NUM_STATE_BITS
+ 1);
564 STATIC_ASSERT(ARRAY_SIZE(cache_bits
) == BRW_MAX_CACHE
+ 1);
566 brw_update_dirty_count(mesa_bits
, state
->mesa
);
567 brw_update_dirty_count(brw_bits
, state
->brw
);
568 brw_update_dirty_count(cache_bits
, state
->cache
);
569 if (dirty_count
++ % 1000 == 0) {
570 brw_print_dirty_count(mesa_bits
);
571 brw_print_dirty_count(brw_bits
);
572 brw_print_dirty_count(cache_bits
);
573 fprintf(stderr
, "\n");
577 memset(state
, 0, sizeof(*state
));