src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  67     * table upload must be last.
  68     */
  69    &brw_vs_pull_constants,
  70    &brw_wm_pull_constants,
  71    &brw_renderbuffer_surfaces,
  72    &brw_texture_surfaces,
  73    &brw_binding_table,
  74
  75    &brw_samplers,
  76
  77    /* These set up state for brw_psp_urb_cbs */
  78    &brw_wm_unit,
  79    &brw_sf_vp,
  80    &brw_sf_unit,
  81    &brw_vs_unit,                /* always required, enabled or not */
  82    &brw_clip_unit,
  83    &brw_gs_unit,
  84
  85    /* Command packets:
  86     */
  87    &brw_invarient_state,
  88    &brw_state_base_address,
  89
  90    &brw_binding_table_pointers,
  91    &brw_blend_constant_color,
  92
  93    &brw_depthbuffer,
  94
  95    &brw_polygon_stipple,
  96    &brw_polygon_stipple_offset,
  97
  98    &brw_line_stipple,
  99    &brw_aa_line_parameters,
 100
 101    &brw_psp_urb_cbs,
 102
 103    &brw_drawing_rect,
 104    &brw_indices,
 105    &brw_index_buffer,
 106    &brw_vertices,
 107
 108    &brw_constant_buffer
 109 };
 110
 111 static const struct brw_tracked_state *gen6_atoms[] =
 112 {
 113    &brw_check_fallback,
 114
 115    &brw_wm_input_sizes,
 116    &brw_vs_prog, /* must do before state base address */
 117    &brw_gs_prog, /* must do before state base address */
 118    &brw_wm_prog, /* must do before state base address */
 119
 120    &gen6_clip_vp,
 121    &gen6_sf_vp,
 122
 123    /* Command packets: */
 124    &brw_invarient_state,
 125
 126    /* must do before binding table pointers, cc state ptrs */
 127    &brw_state_base_address,
 128
 129    &brw_cc_vp,
 130    &gen6_viewport_state,        /* must do after *_vp stages */
 131
 132    &gen6_urb,
 133    &gen6_blend_state,           /* must do before cc unit */
 134    &gen6_color_calc_state,      /* must do before cc unit */
 135    &gen6_depth_stencil_state,   /* must do before cc unit */
 136    &gen6_cc_state_pointers,
 137
 138    &gen6_vs_push_constants, /* Before vs_state */
 139    &gen6_wm_push_constants, /* Before wm_state */
 140
 141    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 142     * table upload must be last.
 143     */
 144    &brw_vs_pull_constants,
 145    &brw_wm_pull_constants,
 146    &gen6_renderbuffer_surfaces,
 147    &brw_texture_surfaces,
 148    &gen6_sol_surface,
 149    &brw_binding_table,
 150
 151    &brw_samplers,
 152    &gen6_sampler_state,
 153
 154    &gen6_vs_state,
 155    &gen6_gs_state,
 156    &gen6_clip_state,
 157    &gen6_sf_state,
 158    &gen6_wm_state,
 159
 160    &gen6_scissor_state,
 161
 162    &gen6_binding_table_pointers,
 163
 164    &brw_depthbuffer,
 165
 166    &brw_polygon_stipple,
 167    &brw_polygon_stipple_offset,
 168
 169    &brw_line_stipple,
 170    &brw_aa_line_parameters,
 171
 172    &brw_drawing_rect,
 173
 174    &gen6_sol_indices,
 175    &brw_indices,
 176    &brw_index_buffer,
 177    &brw_vertices,
 178 };
 179
 180 const struct brw_tracked_state *gen7_atoms[] =
 181 {
 182    &brw_check_fallback,
 183
 184    &brw_wm_input_sizes,
 185    &brw_vs_prog,
 186    &brw_gs_prog,
 187    &brw_wm_prog,
 188
 189    /* Command packets: */
 190    &brw_invarient_state,
 191
 192    /* must do before binding table pointers, cc state ptrs */
 193    &brw_state_base_address,
 194
 195    &brw_cc_vp,
 196    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 197    &gen7_sf_clip_viewport,
 198
 199    &gen7_urb,
 200    &gen6_blend_state,           /* must do before cc unit */
 201    &gen6_color_calc_state,      /* must do before cc unit */
 202    &gen6_depth_stencil_state,   /* must do before cc unit */
 203    &gen7_blend_state_pointer,
 204    &gen7_cc_state_pointer,
 205    &gen7_depth_stencil_state_pointer,
 206
 207    &gen6_vs_push_constants, /* Before vs_state */
 208    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 209
 210    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 211     * table upload must be last.
 212     */
 213    &brw_vs_pull_constants,
 214    &brw_wm_pull_constants,
 215    &gen6_renderbuffer_surfaces,
 216    &brw_texture_surfaces,
 217    &brw_binding_table,
 218
 219    &gen7_samplers,
 220
 221    &gen7_disable_stages,
 222    &gen7_vs_state,
 223    &gen7_clip_state,
 224    &gen7_sbe_state,
 225    &gen7_sf_state,
 226    &gen7_wm_state,
 227    &gen7_ps_state,
 228
 229    &gen6_scissor_state,
 230
 231    &gen7_depthbuffer,
 232
 233    &brw_polygon_stipple,
 234    &brw_polygon_stipple_offset,
 235
 236    &brw_line_stipple,
 237    &brw_aa_line_parameters,
 238
 239    &brw_drawing_rect,
 240
 241    &brw_indices,
 242    &brw_index_buffer,
 243    &brw_vertices,
 244 };
 245
 246
 247 void brw_init_state( struct brw_context *brw )
 248 {
 249    const struct brw_tracked_state **atoms;
 250    int num_atoms;
 251
 252    brw_init_caches(brw);
 253
 254    if (brw->intel.gen >= 7) {
 255       atoms = gen7_atoms;
 256       num_atoms = ARRAY_SIZE(gen7_atoms);
 257    } else if (brw->intel.gen == 6) {
 258       atoms = gen6_atoms;
 259       num_atoms = ARRAY_SIZE(gen6_atoms);
 260    } else {
 261       atoms = gen4_atoms;
 262       num_atoms = ARRAY_SIZE(gen4_atoms);
 263    }
 264
 265    brw->atoms = atoms;
 266    brw->num_atoms = num_atoms;
 267
 268    while (num_atoms--) {
 269       assert((*atoms)->dirty.mesa |
 270              (*atoms)->dirty.brw |
 271              (*atoms)->dirty.cache);
 272       assert((*atoms)->emit);
 273       atoms++;
 274    }
 275 }
 276
 277
 278 void brw_destroy_state( struct brw_context *brw )
 279 {
 280    brw_destroy_caches(brw);
 281 }
 282
 283 /***********************************************************************
 284  */
 285
 286 static GLuint check_state( const struct brw_state_flags *a,
 287                            const struct brw_state_flags *b )
 288 {
 289    return ((a->mesa & b->mesa) |
 290            (a->brw & b->brw) |
 291            (a->cache & b->cache)) != 0;
 292 }
 293
 294 static void accumulate_state( struct brw_state_flags *a,
 295                               const struct brw_state_flags *b )
 296 {
 297    a->mesa |= b->mesa;
 298    a->brw |= b->brw;
 299    a->cache |= b->cache;
 300 }
 301
 302
 303 static void xor_states( struct brw_state_flags *result,
 304                              const struct brw_state_flags *a,
 305                               const struct brw_state_flags *b )
 306 {
 307    result->mesa = a->mesa ^ b->mesa;
 308    result->brw = a->brw ^ b->brw;
 309    result->cache = a->cache ^ b->cache;
 310 }
 311
 312 struct dirty_bit_map {
 313    uint32_t bit;
 314    char *name;
 315    uint32_t count;
 316 };
 317
 318 #define DEFINE_BIT(name) {name, #name, 0}
 319
 320 static struct dirty_bit_map mesa_bits[] = {
 321    DEFINE_BIT(_NEW_MODELVIEW),
 322    DEFINE_BIT(_NEW_PROJECTION),
 323    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 324    DEFINE_BIT(_NEW_COLOR),
 325    DEFINE_BIT(_NEW_DEPTH),
 326    DEFINE_BIT(_NEW_EVAL),
 327    DEFINE_BIT(_NEW_FOG),
 328    DEFINE_BIT(_NEW_HINT),
 329    DEFINE_BIT(_NEW_LIGHT),
 330    DEFINE_BIT(_NEW_LINE),
 331    DEFINE_BIT(_NEW_PIXEL),
 332    DEFINE_BIT(_NEW_POINT),
 333    DEFINE_BIT(_NEW_POLYGON),
 334    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 335    DEFINE_BIT(_NEW_SCISSOR),
 336    DEFINE_BIT(_NEW_STENCIL),
 337    DEFINE_BIT(_NEW_TEXTURE),
 338    DEFINE_BIT(_NEW_TRANSFORM),
 339    DEFINE_BIT(_NEW_VIEWPORT),
 340    DEFINE_BIT(_NEW_PACKUNPACK),
 341    DEFINE_BIT(_NEW_ARRAY),
 342    DEFINE_BIT(_NEW_RENDERMODE),
 343    DEFINE_BIT(_NEW_BUFFERS),
 344    DEFINE_BIT(_NEW_MULTISAMPLE),
 345    DEFINE_BIT(_NEW_TRACK_MATRIX),
 346    DEFINE_BIT(_NEW_PROGRAM),
 347    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 348    {0, 0, 0}
 349 };
 350
 351 static struct dirty_bit_map brw_bits[] = {
 352    DEFINE_BIT(BRW_NEW_URB_FENCE),
 353    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 354    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 355    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 356    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 357    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 358    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 359    DEFINE_BIT(BRW_NEW_CONTEXT),
 360    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 361    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 362    DEFINE_BIT(BRW_NEW_PSP),
 363    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 364    DEFINE_BIT(BRW_NEW_INDICES),
 365    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 366    DEFINE_BIT(BRW_NEW_VERTICES),
 367    DEFINE_BIT(BRW_NEW_BATCH),
 368    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 369    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 370    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 371    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 372    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 373    DEFINE_BIT(BRW_NEW_HIZ),
 374    {0, 0, 0}
 375 };
 376
 377 static struct dirty_bit_map cache_bits[] = {
 378    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 379    DEFINE_BIT(CACHE_NEW_CC_VP),
 380    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 381    DEFINE_BIT(CACHE_NEW_WM_PROG),
 382    DEFINE_BIT(CACHE_NEW_SAMPLER),
 383    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 384    DEFINE_BIT(CACHE_NEW_SF_PROG),
 385    DEFINE_BIT(CACHE_NEW_SF_VP),
 386    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 387    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 388    DEFINE_BIT(CACHE_NEW_VS_PROG),
 389    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 390    DEFINE_BIT(CACHE_NEW_GS_PROG),
 391    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 392    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 393    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 394    {0, 0, 0}
 395 };
 396
 397
 398 static void
 399 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 400 {
 401    int i;
 402
 403    for (i = 0; i < 32; i++) {
 404       if (bit_map[i].bit == 0)
 405          return;
 406
 407       if (bit_map[i].bit & bits)
 408          bit_map[i].count++;
 409    }
 410 }
 411
 412 static void
 413 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 414 {
 415    int i;
 416
 417    for (i = 0; i < 32; i++) {
 418       if (bit_map[i].bit == 0)
 419          return;
 420
 421       fprintf(stderr, "0x%08x: %12d (%s)\n",
 422               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 423    }
 424 }
 425
 426 /***********************************************************************
 427  * Emit all state:
 428  */
 429 void brw_upload_state(struct brw_context *brw)
 430 {
 431    struct gl_context *ctx = &brw->intel.ctx;
 432    struct intel_context *intel = &brw->intel;
 433    struct brw_state_flags *state = &brw->state.dirty;
 434    int i;
 435    static int dirty_count = 0;
 436
 437    state->mesa |= brw->intel.NewGLState;
 438    brw->intel.NewGLState = 0;
 439
 440    if (brw->emit_state_always) {
 441       state->mesa |= ~0;
 442       state->brw |= ~0;
 443       state->cache |= ~0;
 444    }
 445
 446    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 447       brw->fragment_program = ctx->FragmentProgram._Current;
 448       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 449    }
 450
 451    if (brw->vertex_program != ctx->VertexProgram._Current) {
 452       brw->vertex_program = ctx->VertexProgram._Current;
 453       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 454    }
 455
 456    if ((state->mesa | state->cache | state->brw) == 0)
 457       return;
 458
 459    brw->intel.Fallback = false; /* boolean, not bitfield */
 460
 461    intel_check_front_buffer_rendering(intel);
 462
 463    if (unlikely(INTEL_DEBUG)) {
 464       /* Debug version which enforces various sanity checks on the
 465        * state flags which are generated and checked to help ensure
 466        * state atoms are ordered correctly in the list.
 467        */
 468       struct brw_state_flags examined, prev;
 469       memset(&examined, 0, sizeof(examined));
 470       prev = *state;
 471
 472       for (i = 0; i < brw->num_atoms; i++) {
 473          const struct brw_tracked_state *atom = brw->atoms[i];
 474          struct brw_state_flags generated;
 475
 476          if (brw->intel.Fallback)
 477             break;
 478
 479          if (check_state(state, &atom->dirty)) {
 480             atom->emit(brw);
 481          }
 482
 483          accumulate_state(&examined, &atom->dirty);
 484
 485          /* generated = (prev ^ state)
 486           * if (examined & generated)
 487           *     fail;
 488           */
 489          xor_states(&generated, &prev, state);
 490          assert(!check_state(&examined, &generated));
 491          prev = *state;
 492       }
 493    }
 494    else {
 495       for (i = 0; i < brw->num_atoms; i++) {
 496          const struct brw_tracked_state *atom = brw->atoms[i];
 497
 498          if (brw->intel.Fallback)
 499             break;
 500
 501          if (check_state(state, &atom->dirty)) {
 502             atom->emit(brw);
 503          }
 504       }
 505    }
 506
 507    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 508       brw_update_dirty_count(mesa_bits, state->mesa);
 509       brw_update_dirty_count(brw_bits, state->brw);
 510       brw_update_dirty_count(cache_bits, state->cache);
 511       if (dirty_count++ % 1000 == 0) {
 512          brw_print_dirty_count(mesa_bits, state->mesa);
 513          brw_print_dirty_count(brw_bits, state->brw);
 514          brw_print_dirty_count(cache_bits, state->cache);
 515          fprintf(stderr, "\n");
 516       }
 517    }
 518
 519    if (!brw->intel.Fallback)
 520       memset(state, 0, sizeof(*state));
 521 }