src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_gs_prog, /* must do before state base address */
  44    &brw_clip_prog, /* must do before state base address */
  45    &brw_sf_prog, /* must do before state base address */
  46    &brw_wm_prog, /* must do before state base address */
  47
  48    /* Once all the programs are done, we know how large urb entry
  49     * sizes need to be and can decide if we need to change the urb
  50     * layout.
  51     */
  52    &brw_curbe_offsets,
  53    &brw_recalculate_urb_fence,
  54
  55    &brw_cc_vp,
  56    &brw_cc_unit,
  57
  58    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  59     * table upload must be last.
  60     */
  61    &brw_vs_pull_constants,
  62    &brw_wm_pull_constants,
  63    &brw_renderbuffer_surfaces,
  64    &brw_texture_surfaces,
  65    &brw_vs_binding_table,
  66    &brw_wm_binding_table,
  67
  68    &brw_samplers,
  69
  70    /* These set up state for brw_psp_urb_cbs */
  71    &brw_wm_unit,
  72    &brw_sf_vp,
  73    &brw_sf_unit,
  74    &brw_vs_unit,                /* always required, enabled or not */
  75    &brw_clip_unit,
  76    &brw_gs_unit,
  77
  78    /* Command packets:
  79     */
  80    &brw_invariant_state,
  81    &brw_state_base_address,
  82
  83    &brw_binding_table_pointers,
  84    &brw_blend_constant_color,
  85
  86    &brw_depthbuffer,
  87
  88    &brw_polygon_stipple,
  89    &brw_polygon_stipple_offset,
  90
  91    &brw_line_stipple,
  92    &brw_aa_line_parameters,
  93
  94    &brw_psp_urb_cbs,
  95
  96    &brw_drawing_rect,
  97    &brw_indices,
  98    &brw_index_buffer,
  99    &brw_vertices,
 100
 101    &brw_constant_buffer
 102 };
 103
 104 static const struct brw_tracked_state *gen6_atoms[] =
 105 {
 106    &brw_vs_prog, /* must do before state base address */
 107    &brw_gs_prog, /* must do before state base address */
 108    &brw_wm_prog, /* must do before state base address */
 109
 110    &gen6_clip_vp,
 111    &gen6_sf_vp,
 112
 113    /* Command packets: */
 114    &brw_invariant_state,
 115
 116    /* must do before binding table pointers, cc state ptrs */
 117    &brw_state_base_address,
 118
 119    &brw_cc_vp,
 120    &gen6_viewport_state,        /* must do after *_vp stages */
 121
 122    &gen6_urb,
 123    &gen6_blend_state,           /* must do before cc unit */
 124    &gen6_color_calc_state,      /* must do before cc unit */
 125    &gen6_depth_stencil_state,   /* must do before cc unit */
 126    &gen6_cc_state_pointers,
 127
 128    &gen6_vs_push_constants, /* Before vs_state */
 129    &gen6_wm_push_constants, /* Before wm_state */
 130
 131    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 132     * table upload must be last.
 133     */
 134    &brw_vs_pull_constants,
 135    &brw_vs_ubo_surfaces,
 136    &brw_wm_pull_constants,
 137    &brw_wm_ubo_surfaces,
 138    &gen6_renderbuffer_surfaces,
 139    &brw_texture_surfaces,
 140    &gen6_sol_surface,
 141    &brw_vs_binding_table,
 142    &gen6_gs_binding_table,
 143    &brw_wm_binding_table,
 144
 145    &brw_samplers,
 146    &gen6_sampler_state,
 147    &gen6_multisample_state,
 148
 149    &gen6_vs_state,
 150    &gen6_gs_state,
 151    &gen6_clip_state,
 152    &gen6_sf_state,
 153    &gen6_wm_state,
 154
 155    &gen6_scissor_state,
 156
 157    &gen6_binding_table_pointers,
 158
 159    &brw_depthbuffer,
 160
 161    &brw_polygon_stipple,
 162    &brw_polygon_stipple_offset,
 163
 164    &brw_line_stipple,
 165    &brw_aa_line_parameters,
 166
 167    &brw_drawing_rect,
 168
 169    &gen6_sol_indices,
 170    &brw_indices,
 171    &brw_index_buffer,
 172    &brw_vertices,
 173 };
 174
 175 static const struct brw_tracked_state *gen7_atoms[] =
 176 {
 177    &brw_vs_prog,
 178    &brw_wm_prog,
 179
 180    /* Command packets: */
 181    &brw_invariant_state,
 182    &gen7_push_constant_alloc,
 183
 184    /* must do before binding table pointers, cc state ptrs */
 185    &brw_state_base_address,
 186
 187    &brw_cc_vp,
 188    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 189    &gen7_sf_clip_viewport,
 190
 191    &gen7_urb,
 192    &gen6_blend_state,           /* must do before cc unit */
 193    &gen6_color_calc_state,      /* must do before cc unit */
 194    &gen6_depth_stencil_state,   /* must do before cc unit */
 195    &gen7_blend_state_pointer,
 196    &gen7_cc_state_pointer,
 197    &gen7_depth_stencil_state_pointer,
 198
 199    &gen6_vs_push_constants, /* Before vs_state */
 200    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 201
 202    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 203     * table upload must be last.
 204     */
 205    &brw_vs_pull_constants,
 206    &brw_vs_ubo_surfaces,
 207    &brw_wm_pull_constants,
 208    &brw_wm_ubo_surfaces,
 209    &gen6_renderbuffer_surfaces,
 210    &brw_texture_surfaces,
 211    &brw_vs_binding_table,
 212    &brw_wm_binding_table,
 213
 214    &gen7_samplers,
 215    &gen6_multisample_state,
 216
 217    &gen7_disable_stages,
 218    &gen7_vs_state,
 219    &gen7_sol_state,
 220    &gen7_clip_state,
 221    &gen7_sbe_state,
 222    &gen7_sf_state,
 223    &gen7_wm_state,
 224    &gen7_ps_state,
 225
 226    &gen6_scissor_state,
 227
 228    &gen7_depthbuffer,
 229
 230    &brw_polygon_stipple,
 231    &brw_polygon_stipple_offset,
 232
 233    &brw_line_stipple,
 234    &brw_aa_line_parameters,
 235
 236    &brw_drawing_rect,
 237
 238    &brw_indices,
 239    &brw_index_buffer,
 240    &brw_vertices,
 241
 242    &haswell_cut_index,
 243 };
 244
 245
 246 void brw_init_state( struct brw_context *brw )
 247 {
 248    const struct brw_tracked_state **atoms;
 249    int num_atoms;
 250
 251    brw_init_caches(brw);
 252
 253    if (brw->intel.gen >= 7) {
 254       atoms = gen7_atoms;
 255       num_atoms = ARRAY_SIZE(gen7_atoms);
 256    } else if (brw->intel.gen == 6) {
 257       atoms = gen6_atoms;
 258       num_atoms = ARRAY_SIZE(gen6_atoms);
 259    } else {
 260       atoms = gen4_atoms;
 261       num_atoms = ARRAY_SIZE(gen4_atoms);
 262    }
 263
 264    brw->atoms = atoms;
 265    brw->num_atoms = num_atoms;
 266
 267    while (num_atoms--) {
 268       assert((*atoms)->dirty.mesa |
 269              (*atoms)->dirty.brw |
 270              (*atoms)->dirty.cache);
 271       assert((*atoms)->emit);
 272       atoms++;
 273    }
 274 }
 275
 276
 277 void brw_destroy_state( struct brw_context *brw )
 278 {
 279    brw_destroy_caches(brw);
 280 }
 281
 282 /***********************************************************************
 283  */
 284
 285 static GLuint check_state( const struct brw_state_flags *a,
 286                            const struct brw_state_flags *b )
 287 {
 288    return ((a->mesa & b->mesa) |
 289            (a->brw & b->brw) |
 290            (a->cache & b->cache)) != 0;
 291 }
 292
 293 static void accumulate_state( struct brw_state_flags *a,
 294                               const struct brw_state_flags *b )
 295 {
 296    a->mesa |= b->mesa;
 297    a->brw |= b->brw;
 298    a->cache |= b->cache;
 299 }
 300
 301
 302 static void xor_states( struct brw_state_flags *result,
 303                              const struct brw_state_flags *a,
 304                               const struct brw_state_flags *b )
 305 {
 306    result->mesa = a->mesa ^ b->mesa;
 307    result->brw = a->brw ^ b->brw;
 308    result->cache = a->cache ^ b->cache;
 309 }
 310
 311 struct dirty_bit_map {
 312    uint32_t bit;
 313    char *name;
 314    uint32_t count;
 315 };
 316
 317 #define DEFINE_BIT(name) {name, #name, 0}
 318
 319 static struct dirty_bit_map mesa_bits[] = {
 320    DEFINE_BIT(_NEW_MODELVIEW),
 321    DEFINE_BIT(_NEW_PROJECTION),
 322    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 323    DEFINE_BIT(_NEW_COLOR),
 324    DEFINE_BIT(_NEW_DEPTH),
 325    DEFINE_BIT(_NEW_EVAL),
 326    DEFINE_BIT(_NEW_FOG),
 327    DEFINE_BIT(_NEW_HINT),
 328    DEFINE_BIT(_NEW_LIGHT),
 329    DEFINE_BIT(_NEW_LINE),
 330    DEFINE_BIT(_NEW_PIXEL),
 331    DEFINE_BIT(_NEW_POINT),
 332    DEFINE_BIT(_NEW_POLYGON),
 333    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 334    DEFINE_BIT(_NEW_SCISSOR),
 335    DEFINE_BIT(_NEW_STENCIL),
 336    DEFINE_BIT(_NEW_TEXTURE),
 337    DEFINE_BIT(_NEW_TRANSFORM),
 338    DEFINE_BIT(_NEW_VIEWPORT),
 339    DEFINE_BIT(_NEW_ARRAY),
 340    DEFINE_BIT(_NEW_RENDERMODE),
 341    DEFINE_BIT(_NEW_BUFFERS),
 342    DEFINE_BIT(_NEW_MULTISAMPLE),
 343    DEFINE_BIT(_NEW_TRACK_MATRIX),
 344    DEFINE_BIT(_NEW_PROGRAM),
 345    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 346    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 347    DEFINE_BIT(_NEW_FRAG_CLAMP),
 348    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 349    {0, 0, 0}
 350 };
 351
 352 static struct dirty_bit_map brw_bits[] = {
 353    DEFINE_BIT(BRW_NEW_URB_FENCE),
 354    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 355    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 356    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 357    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 358    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 359    DEFINE_BIT(BRW_NEW_CONTEXT),
 360    DEFINE_BIT(BRW_NEW_PSP),
 361    DEFINE_BIT(BRW_NEW_SURFACES),
 362    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 363    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 364    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 365    DEFINE_BIT(BRW_NEW_INDICES),
 366    DEFINE_BIT(BRW_NEW_VERTICES),
 367    DEFINE_BIT(BRW_NEW_BATCH),
 368    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 369    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 370    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 371    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 372    DEFINE_BIT(BRW_NEW_SOL_INDICES),
 373    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 374    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 375    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 376    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 377    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 378    {0, 0, 0}
 379 };
 380
 381 static struct dirty_bit_map cache_bits[] = {
 382    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 383    DEFINE_BIT(CACHE_NEW_DEPTH_STENCIL_STATE),
 384    DEFINE_BIT(CACHE_NEW_COLOR_CALC_STATE),
 385    DEFINE_BIT(CACHE_NEW_CC_VP),
 386    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 387    DEFINE_BIT(CACHE_NEW_WM_PROG),
 388    DEFINE_BIT(CACHE_NEW_SAMPLER),
 389    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 390    DEFINE_BIT(CACHE_NEW_SF_PROG),
 391    DEFINE_BIT(CACHE_NEW_SF_VP),
 392    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 393    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 394    DEFINE_BIT(CACHE_NEW_VS_PROG),
 395    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 396    DEFINE_BIT(CACHE_NEW_GS_PROG),
 397    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 398    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 399    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 400    {0, 0, 0}
 401 };
 402
 403
 404 static void
 405 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 406 {
 407    int i;
 408
 409    for (i = 0; i < 32; i++) {
 410       if (bit_map[i].bit == 0)
 411          return;
 412
 413       if (bit_map[i].bit & bits)
 414          bit_map[i].count++;
 415    }
 416 }
 417
 418 static void
 419 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 420 {
 421    int i;
 422
 423    for (i = 0; i < 32; i++) {
 424       if (bit_map[i].bit == 0)
 425          return;
 426
 427       fprintf(stderr, "0x%08x: %12d (%s)\n",
 428               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 429    }
 430 }
 431
 432 /***********************************************************************
 433  * Emit all state:
 434  */
 435 void brw_upload_state(struct brw_context *brw)
 436 {
 437    struct gl_context *ctx = &brw->intel.ctx;
 438    struct intel_context *intel = &brw->intel;
 439    struct brw_state_flags *state = &brw->state.dirty;
 440    int i;
 441    static int dirty_count = 0;
 442
 443    state->mesa |= brw->intel.NewGLState;
 444    brw->intel.NewGLState = 0;
 445
 446    state->brw |= ctx->NewDriverState;
 447    ctx->NewDriverState = 0;
 448
 449    if (brw->emit_state_always) {
 450       state->mesa |= ~0;
 451       state->brw |= ~0;
 452       state->cache |= ~0;
 453    }
 454
 455    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 456       brw->fragment_program = ctx->FragmentProgram._Current;
 457       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 458    }
 459
 460    if (brw->vertex_program != ctx->VertexProgram._Current) {
 461       brw->vertex_program = ctx->VertexProgram._Current;
 462       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 463    }
 464
 465    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 466       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 467       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 468    }
 469
 470    if ((state->mesa | state->cache | state->brw) == 0)
 471       return;
 472
 473    intel_check_front_buffer_rendering(intel);
 474
 475    if (unlikely(INTEL_DEBUG)) {
 476       /* Debug version which enforces various sanity checks on the
 477        * state flags which are generated and checked to help ensure
 478        * state atoms are ordered correctly in the list.
 479        */
 480       struct brw_state_flags examined, prev;
 481       memset(&examined, 0, sizeof(examined));
 482       prev = *state;
 483
 484       for (i = 0; i < brw->num_atoms; i++) {
 485          const struct brw_tracked_state *atom = brw->atoms[i];
 486          struct brw_state_flags generated;
 487
 488          if (check_state(state, &atom->dirty)) {
 489             atom->emit(brw);
 490          }
 491
 492          accumulate_state(&examined, &atom->dirty);
 493
 494          /* generated = (prev ^ state)
 495           * if (examined & generated)
 496           *     fail;
 497           */
 498          xor_states(&generated, &prev, state);
 499          assert(!check_state(&examined, &generated));
 500          prev = *state;
 501       }
 502    }
 503    else {
 504       for (i = 0; i < brw->num_atoms; i++) {
 505          const struct brw_tracked_state *atom = brw->atoms[i];
 506
 507          if (check_state(state, &atom->dirty)) {
 508             atom->emit(brw);
 509          }
 510       }
 511    }
 512
 513    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 514       brw_update_dirty_count(mesa_bits, state->mesa);
 515       brw_update_dirty_count(brw_bits, state->brw);
 516       brw_update_dirty_count(cache_bits, state->cache);
 517       if (dirty_count++ % 1000 == 0) {
 518          brw_print_dirty_count(mesa_bits, state->mesa);
 519          brw_print_dirty_count(brw_bits, state->brw);
 520          brw_print_dirty_count(cache_bits, state->cache);
 521          fprintf(stderr, "\n");
 522       }
 523    }
 524
 525    memset(state, 0, sizeof(*state));
 526 }