2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "brw_context.h"
35 #include "brw_defines.h"
36 #include "brw_state.h"
37 #include "brw_program.h"
38 #include "drivers/common/meta.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_buffers.h"
42 #include "brw_ff_gs.h"
46 #include "main/framebuffer.h"
49 brw_upload_initial_gpu_state(struct brw_context
*brw
)
51 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
53 /* On platforms with hardware contexts, we can set our initial GPU state
54 * right away rather than doing it via state atoms. This saves a small
55 * amount of overhead on every draw call.
60 if (devinfo
->gen
== 6)
61 brw_emit_post_sync_nonzero_flush(brw
);
63 brw_upload_invariant_state(brw
);
65 if (devinfo
->gen
== 10 || devinfo
->gen
== 11) {
66 brw_load_register_imm32(brw
, GEN10_CACHE_MODE_SS
,
67 REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE
) |
68 GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE
);
70 /* From gen10 workaround table in h/w specs:
72 * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
75 * This means that we end up setting the entire 3D_MODE state. Bits
76 * in this register control things such as slice hashing and we want
77 * the default values of zero at the moment.
80 OUT_BATCH(_3DSTATE_3D_MODE
<< 16 | (2 - 2));
81 OUT_BATCH(0xFFFF << 16);
85 if (devinfo
->gen
== 9) {
86 /* Recommended optimizations for Victim Cache eviction and floating
89 brw_load_register_imm32(brw
, GEN7_CACHE_MODE_1
,
90 REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
) |
91 REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
) |
92 GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
|
93 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
);
95 if (gen_device_info_is_9lp(devinfo
)) {
96 brw_load_register_imm32(brw
, GEN7_GT_MODE
,
97 GEN9_SUBSLICE_HASHING_MASK_BITS
|
98 GEN9_SUBSLICE_HASHING_16x16
);
102 if (devinfo
->gen
>= 8) {
103 gen8_emit_3dstate_sample_pattern(brw
);
106 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
114 OUT_BATCH(_3DSTATE_WM_CHROMAKEY
<< 16 | (2 - 2));
120 static inline const struct brw_tracked_state
*
121 brw_get_pipeline_atoms(struct brw_context
*brw
,
122 enum brw_pipeline pipeline
)
125 case BRW_RENDER_PIPELINE
:
126 return brw
->render_atoms
;
127 case BRW_COMPUTE_PIPELINE
:
128 return brw
->compute_atoms
;
130 STATIC_ASSERT(BRW_NUM_PIPELINES
== 2);
131 unreachable("Unsupported pipeline");
137 brw_copy_pipeline_atoms(struct brw_context
*brw
,
138 enum brw_pipeline pipeline
,
139 const struct brw_tracked_state
**atoms
,
142 /* This is to work around brw_context::atoms being declared const. We want
143 * it to be const, but it needs to be initialized somehow!
145 struct brw_tracked_state
*context_atoms
=
146 (struct brw_tracked_state
*) brw_get_pipeline_atoms(brw
, pipeline
);
148 for (int i
= 0; i
< num_atoms
; i
++) {
149 context_atoms
[i
] = *atoms
[i
];
150 assert(context_atoms
[i
].dirty
.mesa
| context_atoms
[i
].dirty
.brw
);
151 assert(context_atoms
[i
].emit
);
154 brw
->num_atoms
[pipeline
] = num_atoms
;
157 void brw_init_state( struct brw_context
*brw
)
159 struct gl_context
*ctx
= &brw
->ctx
;
160 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
162 /* Force the first brw_select_pipeline to emit pipeline select */
163 brw
->last_pipeline
= BRW_NUM_PIPELINES
;
165 brw_init_caches(brw
);
167 if (devinfo
->gen
>= 11)
168 gen11_init_atoms(brw
);
169 else if (devinfo
->gen
>= 10)
170 gen10_init_atoms(brw
);
171 else if (devinfo
->gen
>= 9)
172 gen9_init_atoms(brw
);
173 else if (devinfo
->gen
>= 8)
174 gen8_init_atoms(brw
);
175 else if (devinfo
->is_haswell
)
176 gen75_init_atoms(brw
);
177 else if (devinfo
->gen
>= 7)
178 gen7_init_atoms(brw
);
179 else if (devinfo
->gen
>= 6)
180 gen6_init_atoms(brw
);
181 else if (devinfo
->gen
>= 5)
182 gen5_init_atoms(brw
);
183 else if (devinfo
->is_g4x
)
184 gen45_init_atoms(brw
);
186 gen4_init_atoms(brw
);
188 brw_upload_initial_gpu_state(brw
);
190 brw
->NewGLState
= ~0;
191 brw
->ctx
.NewDriverState
= ~0ull;
193 /* ~0 is a nonsensical value which won't match anything we program, so
194 * the programming will take effect on the first time around.
196 brw
->pma_stall_bits
= ~0;
198 /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
201 STATIC_ASSERT(BRW_NUM_STATE_BITS
<= 8 * sizeof(brw
->ctx
.NewDriverState
));
203 ctx
->DriverFlags
.NewTransformFeedback
= BRW_NEW_TRANSFORM_FEEDBACK
;
204 ctx
->DriverFlags
.NewTransformFeedbackProg
= BRW_NEW_TRANSFORM_FEEDBACK
;
205 ctx
->DriverFlags
.NewRasterizerDiscard
= BRW_NEW_RASTERIZER_DISCARD
;
206 ctx
->DriverFlags
.NewUniformBuffer
= BRW_NEW_UNIFORM_BUFFER
;
207 ctx
->DriverFlags
.NewShaderStorageBuffer
= BRW_NEW_UNIFORM_BUFFER
;
208 ctx
->DriverFlags
.NewTextureBuffer
= BRW_NEW_TEXTURE_BUFFER
;
209 ctx
->DriverFlags
.NewAtomicBuffer
= BRW_NEW_UNIFORM_BUFFER
;
210 ctx
->DriverFlags
.NewImageUnits
= BRW_NEW_IMAGE_UNITS
;
211 ctx
->DriverFlags
.NewDefaultTessLevels
= BRW_NEW_DEFAULT_TESS_LEVELS
;
212 ctx
->DriverFlags
.NewIntelConservativeRasterization
= BRW_NEW_CONSERVATIVE_RASTERIZATION
;
216 void brw_destroy_state( struct brw_context
*brw
)
218 brw_destroy_caches(brw
);
221 /***********************************************************************
225 check_state(const struct brw_state_flags
*a
, const struct brw_state_flags
*b
)
227 return ((a
->mesa
& b
->mesa
) | (a
->brw
& b
->brw
)) != 0;
230 static void accumulate_state( struct brw_state_flags
*a
,
231 const struct brw_state_flags
*b
)
238 static void xor_states( struct brw_state_flags
*result
,
239 const struct brw_state_flags
*a
,
240 const struct brw_state_flags
*b
)
242 result
->mesa
= a
->mesa
^ b
->mesa
;
243 result
->brw
= a
->brw
^ b
->brw
;
246 struct dirty_bit_map
{
252 #define DEFINE_BIT(name) {name, #name, 0}
254 static struct dirty_bit_map mesa_bits
[] = {
255 DEFINE_BIT(_NEW_MODELVIEW
),
256 DEFINE_BIT(_NEW_PROJECTION
),
257 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
258 DEFINE_BIT(_NEW_COLOR
),
259 DEFINE_BIT(_NEW_DEPTH
),
260 DEFINE_BIT(_NEW_EVAL
),
261 DEFINE_BIT(_NEW_FOG
),
262 DEFINE_BIT(_NEW_HINT
),
263 DEFINE_BIT(_NEW_LIGHT
),
264 DEFINE_BIT(_NEW_LINE
),
265 DEFINE_BIT(_NEW_PIXEL
),
266 DEFINE_BIT(_NEW_POINT
),
267 DEFINE_BIT(_NEW_POLYGON
),
268 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
269 DEFINE_BIT(_NEW_SCISSOR
),
270 DEFINE_BIT(_NEW_STENCIL
),
271 DEFINE_BIT(_NEW_TEXTURE_OBJECT
),
272 DEFINE_BIT(_NEW_TRANSFORM
),
273 DEFINE_BIT(_NEW_VIEWPORT
),
274 DEFINE_BIT(_NEW_TEXTURE_STATE
),
275 DEFINE_BIT(_NEW_ARRAY
),
276 DEFINE_BIT(_NEW_RENDERMODE
),
277 DEFINE_BIT(_NEW_BUFFERS
),
278 DEFINE_BIT(_NEW_CURRENT_ATTRIB
),
279 DEFINE_BIT(_NEW_MULTISAMPLE
),
280 DEFINE_BIT(_NEW_TRACK_MATRIX
),
281 DEFINE_BIT(_NEW_PROGRAM
),
282 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
283 DEFINE_BIT(_NEW_FRAG_CLAMP
),
284 /* Avoid sign extension problems. */
285 {(unsigned) _NEW_VARYING_VP_INPUTS
, "_NEW_VARYING_VP_INPUTS", 0},
289 static struct dirty_bit_map brw_bits
[] = {
290 DEFINE_BIT(BRW_NEW_FS_PROG_DATA
),
291 DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA
),
292 DEFINE_BIT(BRW_NEW_SF_PROG_DATA
),
293 DEFINE_BIT(BRW_NEW_VS_PROG_DATA
),
294 DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA
),
295 DEFINE_BIT(BRW_NEW_GS_PROG_DATA
),
296 DEFINE_BIT(BRW_NEW_TCS_PROG_DATA
),
297 DEFINE_BIT(BRW_NEW_TES_PROG_DATA
),
298 DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA
),
299 DEFINE_BIT(BRW_NEW_CS_PROG_DATA
),
300 DEFINE_BIT(BRW_NEW_URB_FENCE
),
301 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
302 DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM
),
303 DEFINE_BIT(BRW_NEW_TESS_PROGRAMS
),
304 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
305 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
306 DEFINE_BIT(BRW_NEW_PATCH_PRIMITIVE
),
307 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
308 DEFINE_BIT(BRW_NEW_CONTEXT
),
309 DEFINE_BIT(BRW_NEW_PSP
),
310 DEFINE_BIT(BRW_NEW_SURFACES
),
311 DEFINE_BIT(BRW_NEW_BINDING_TABLE_POINTERS
),
312 DEFINE_BIT(BRW_NEW_INDICES
),
313 DEFINE_BIT(BRW_NEW_VERTICES
),
314 DEFINE_BIT(BRW_NEW_DEFAULT_TESS_LEVELS
),
315 DEFINE_BIT(BRW_NEW_BATCH
),
316 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
317 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
318 DEFINE_BIT(BRW_NEW_TCS_CONSTBUF
),
319 DEFINE_BIT(BRW_NEW_TES_CONSTBUF
),
320 DEFINE_BIT(BRW_NEW_GS_CONSTBUF
),
321 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
322 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
323 DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT
),
324 DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK
),
325 DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD
),
326 DEFINE_BIT(BRW_NEW_STATS_WM
),
327 DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER
),
328 DEFINE_BIT(BRW_NEW_IMAGE_UNITS
),
329 DEFINE_BIT(BRW_NEW_META_IN_PROGRESS
),
330 DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
331 DEFINE_BIT(BRW_NEW_NUM_SAMPLES
),
332 DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER
),
333 DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE
),
334 DEFINE_BIT(BRW_NEW_CC_VP
),
335 DEFINE_BIT(BRW_NEW_SF_VP
),
336 DEFINE_BIT(BRW_NEW_CLIP_VP
),
337 DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE
),
338 DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS
),
339 DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM
),
340 DEFINE_BIT(BRW_NEW_CS_WORK_GROUPS
),
341 DEFINE_BIT(BRW_NEW_URB_SIZE
),
342 DEFINE_BIT(BRW_NEW_CC_STATE
),
343 DEFINE_BIT(BRW_NEW_BLORP
),
344 DEFINE_BIT(BRW_NEW_VIEWPORT_COUNT
),
345 DEFINE_BIT(BRW_NEW_CONSERVATIVE_RASTERIZATION
),
346 DEFINE_BIT(BRW_NEW_DRAW_CALL
),
347 DEFINE_BIT(BRW_NEW_AUX_STATE
),
352 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, uint64_t bits
)
354 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
355 if (bit_map
[i
].bit
& bits
)
361 brw_print_dirty_count(struct dirty_bit_map
*bit_map
)
363 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
364 if (bit_map
[i
].count
> 1) {
365 fprintf(stderr
, "0x%016"PRIx64
": %12d (%s)\n",
366 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
372 brw_upload_tess_programs(struct brw_context
*brw
)
374 if (brw
->programs
[MESA_SHADER_TESS_EVAL
]) {
375 brw_upload_tcs_prog(brw
);
376 brw_upload_tes_prog(brw
);
378 brw
->tcs
.base
.prog_data
= NULL
;
379 brw
->tes
.base
.prog_data
= NULL
;
384 brw_upload_programs(struct brw_context
*brw
,
385 enum brw_pipeline pipeline
)
387 struct gl_context
*ctx
= &brw
->ctx
;
388 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
390 if (pipeline
== BRW_RENDER_PIPELINE
) {
391 brw_upload_vs_prog(brw
);
392 brw_upload_tess_programs(brw
);
394 if (brw
->programs
[MESA_SHADER_GEOMETRY
]) {
395 brw_upload_gs_prog(brw
);
397 brw
->gs
.base
.prog_data
= NULL
;
398 if (devinfo
->gen
< 7)
399 brw_upload_ff_gs_prog(brw
);
402 /* Update the VUE map for data exiting the GS stage of the pipeline.
403 * This comes from the last enabled shader stage.
405 GLbitfield64 old_slots
= brw
->vue_map_geom_out
.slots_valid
;
406 bool old_separate
= brw
->vue_map_geom_out
.separate
;
407 struct brw_vue_prog_data
*vue_prog_data
;
408 if (brw
->programs
[MESA_SHADER_GEOMETRY
])
409 vue_prog_data
= brw_vue_prog_data(brw
->gs
.base
.prog_data
);
410 else if (brw
->programs
[MESA_SHADER_TESS_EVAL
])
411 vue_prog_data
= brw_vue_prog_data(brw
->tes
.base
.prog_data
);
413 vue_prog_data
= brw_vue_prog_data(brw
->vs
.base
.prog_data
);
415 brw
->vue_map_geom_out
= vue_prog_data
->vue_map
;
417 /* If the layout has changed, signal BRW_NEW_VUE_MAP_GEOM_OUT. */
418 if (old_slots
!= brw
->vue_map_geom_out
.slots_valid
||
419 old_separate
!= brw
->vue_map_geom_out
.separate
)
420 brw
->ctx
.NewDriverState
|= BRW_NEW_VUE_MAP_GEOM_OUT
;
422 if ((old_slots
^ brw
->vue_map_geom_out
.slots_valid
) &
423 VARYING_BIT_VIEWPORT
) {
424 ctx
->NewDriverState
|= BRW_NEW_VIEWPORT_COUNT
;
425 brw
->clip
.viewport_count
=
426 (brw
->vue_map_geom_out
.slots_valid
& VARYING_BIT_VIEWPORT
) ?
427 ctx
->Const
.MaxViewports
: 1;
430 brw_upload_wm_prog(brw
);
432 if (devinfo
->gen
< 6) {
433 brw_upload_clip_prog(brw
);
434 brw_upload_sf_prog(brw
);
437 brw_disk_cache_write_render_programs(brw
);
438 } else if (pipeline
== BRW_COMPUTE_PIPELINE
) {
439 brw_upload_cs_prog(brw
);
440 brw_disk_cache_write_compute_program(brw
);
445 merge_ctx_state(struct brw_context
*brw
,
446 struct brw_state_flags
*state
)
448 state
->mesa
|= brw
->NewGLState
;
449 state
->brw
|= brw
->ctx
.NewDriverState
;
452 static ALWAYS_INLINE
void
453 check_and_emit_atom(struct brw_context
*brw
,
454 struct brw_state_flags
*state
,
455 const struct brw_tracked_state
*atom
)
457 if (check_state(state
, &atom
->dirty
)) {
459 merge_ctx_state(brw
, state
);
464 brw_upload_pipeline_state(struct brw_context
*brw
,
465 enum brw_pipeline pipeline
)
467 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
468 struct gl_context
*ctx
= &brw
->ctx
;
470 static int dirty_count
= 0;
471 struct brw_state_flags state
= brw
->state
.pipelines
[pipeline
];
472 const unsigned fb_samples
=
473 MAX2(_mesa_geometric_samples(ctx
->DrawBuffer
), 1);
475 brw_select_pipeline(brw
, pipeline
);
477 if (unlikely(INTEL_DEBUG
& DEBUG_REEMIT
)) {
478 /* Always re-emit all state. */
479 brw
->NewGLState
= ~0;
480 ctx
->NewDriverState
= ~0ull;
483 if (pipeline
== BRW_RENDER_PIPELINE
) {
484 if (brw
->programs
[MESA_SHADER_FRAGMENT
] !=
485 ctx
->FragmentProgram
._Current
) {
486 brw
->programs
[MESA_SHADER_FRAGMENT
] = ctx
->FragmentProgram
._Current
;
487 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
490 if (brw
->programs
[MESA_SHADER_TESS_EVAL
] !=
491 ctx
->TessEvalProgram
._Current
) {
492 brw
->programs
[MESA_SHADER_TESS_EVAL
] = ctx
->TessEvalProgram
._Current
;
493 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
496 if (brw
->programs
[MESA_SHADER_TESS_CTRL
] !=
497 ctx
->TessCtrlProgram
._Current
) {
498 brw
->programs
[MESA_SHADER_TESS_CTRL
] = ctx
->TessCtrlProgram
._Current
;
499 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
502 if (brw
->programs
[MESA_SHADER_GEOMETRY
] !=
503 ctx
->GeometryProgram
._Current
) {
504 brw
->programs
[MESA_SHADER_GEOMETRY
] = ctx
->GeometryProgram
._Current
;
505 brw
->ctx
.NewDriverState
|= BRW_NEW_GEOMETRY_PROGRAM
;
508 if (brw
->programs
[MESA_SHADER_VERTEX
] != ctx
->VertexProgram
._Current
) {
509 brw
->programs
[MESA_SHADER_VERTEX
] = ctx
->VertexProgram
._Current
;
510 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
514 if (brw
->programs
[MESA_SHADER_COMPUTE
] != ctx
->ComputeProgram
._Current
) {
515 brw
->programs
[MESA_SHADER_COMPUTE
] = ctx
->ComputeProgram
._Current
;
516 brw
->ctx
.NewDriverState
|= BRW_NEW_COMPUTE_PROGRAM
;
519 if (brw
->meta_in_progress
!= _mesa_meta_in_progress(ctx
)) {
520 brw
->meta_in_progress
= _mesa_meta_in_progress(ctx
);
521 brw
->ctx
.NewDriverState
|= BRW_NEW_META_IN_PROGRESS
;
524 if (brw
->num_samples
!= fb_samples
) {
525 brw
->num_samples
= fb_samples
;
526 brw
->ctx
.NewDriverState
|= BRW_NEW_NUM_SAMPLES
;
529 /* Exit early if no state is flagged as dirty */
530 merge_ctx_state(brw
, &state
);
531 if ((state
.mesa
| state
.brw
) == 0)
534 /* Emit Sandybridge workaround flushes on every primitive, for safety. */
535 if (devinfo
->gen
== 6)
536 brw_emit_post_sync_nonzero_flush(brw
);
538 brw_upload_programs(brw
, pipeline
);
539 merge_ctx_state(brw
, &state
);
541 brw_upload_state_base_address(brw
);
543 const struct brw_tracked_state
*atoms
=
544 brw_get_pipeline_atoms(brw
, pipeline
);
545 const int num_atoms
= brw
->num_atoms
[pipeline
];
547 if (unlikely(INTEL_DEBUG
)) {
548 /* Debug version which enforces various sanity checks on the
549 * state flags which are generated and checked to help ensure
550 * state atoms are ordered correctly in the list.
552 struct brw_state_flags examined
, prev
;
553 memset(&examined
, 0, sizeof(examined
));
556 for (i
= 0; i
< num_atoms
; i
++) {
557 const struct brw_tracked_state
*atom
= &atoms
[i
];
558 struct brw_state_flags generated
;
560 check_and_emit_atom(brw
, &state
, atom
);
562 accumulate_state(&examined
, &atom
->dirty
);
564 /* generated = (prev ^ state)
565 * if (examined & generated)
568 xor_states(&generated
, &prev
, &state
);
569 assert(!check_state(&examined
, &generated
));
574 for (i
= 0; i
< num_atoms
; i
++) {
575 const struct brw_tracked_state
*atom
= &atoms
[i
];
577 check_and_emit_atom(brw
, &state
, atom
);
581 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
582 STATIC_ASSERT(ARRAY_SIZE(brw_bits
) == BRW_NUM_STATE_BITS
+ 1);
584 brw_update_dirty_count(mesa_bits
, state
.mesa
);
585 brw_update_dirty_count(brw_bits
, state
.brw
);
586 if (dirty_count
++ % 1000 == 0) {
587 brw_print_dirty_count(mesa_bits
);
588 brw_print_dirty_count(brw_bits
);
589 fprintf(stderr
, "\n");
594 /***********************************************************************
597 void brw_upload_render_state(struct brw_context
*brw
)
599 brw_upload_pipeline_state(brw
, BRW_RENDER_PIPELINE
);
603 brw_pipeline_state_finished(struct brw_context
*brw
,
604 enum brw_pipeline pipeline
)
606 /* Save all dirty state into the other pipelines */
607 for (unsigned i
= 0; i
< BRW_NUM_PIPELINES
; i
++) {
609 brw
->state
.pipelines
[i
].mesa
|= brw
->NewGLState
;
610 brw
->state
.pipelines
[i
].brw
|= brw
->ctx
.NewDriverState
;
612 memset(&brw
->state
.pipelines
[i
], 0, sizeof(struct brw_state_flags
));
617 brw
->ctx
.NewDriverState
= 0ull;
621 * Clear dirty bits to account for the fact that the state emitted by
622 * brw_upload_render_state() has been committed to the hardware. This is a
623 * separate call from brw_upload_render_state() because it's possible that
624 * after the call to brw_upload_render_state(), we will discover that we've
625 * run out of aperture space, and need to rewind the batch buffer to the state
626 * it had before the brw_upload_render_state() call.
629 brw_render_state_finished(struct brw_context
*brw
)
631 brw_pipeline_state_finished(brw
, BRW_RENDER_PIPELINE
);
635 brw_upload_compute_state(struct brw_context
*brw
)
637 brw_upload_pipeline_state(brw
, BRW_COMPUTE_PIPELINE
);
641 brw_compute_state_finished(struct brw_context
*brw
)
643 brw_pipeline_state_finished(brw
, BRW_COMPUTE_PIPELINE
);