src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_ff_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_wm_push_constants, /* Before wm_state */
 132
 133    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 134     * table upload must be last.
 135     */
 136    &brw_vs_pull_constants,
 137    &brw_vs_ubo_surfaces,
 138    &brw_wm_pull_constants,
 139    &brw_wm_ubo_surfaces,
 140    &gen6_renderbuffer_surfaces,
 141    &brw_texture_surfaces,
 142    &gen6_sol_surface,
 143    &brw_vs_binding_table,
 144    &gen6_gs_binding_table,
 145    &brw_wm_binding_table,
 146
 147    &brw_fs_samplers,
 148    &brw_vs_samplers,
 149    &gen6_sampler_state,
 150    &gen6_multisample_state,
 151
 152    &gen6_vs_state,
 153    &gen6_gs_state,
 154    &gen6_clip_state,
 155    &gen6_sf_state,
 156    &gen6_wm_state,
 157
 158    &gen6_scissor_state,
 159
 160    &gen6_binding_table_pointers,
 161
 162    &brw_depthbuffer,
 163
 164    &brw_polygon_stipple,
 165    &brw_polygon_stipple_offset,
 166
 167    &brw_line_stipple,
 168    &brw_aa_line_parameters,
 169
 170    &brw_drawing_rect,
 171
 172    &brw_indices,
 173    &brw_index_buffer,
 174    &brw_vertices,
 175 };
 176
 177 static const struct brw_tracked_state *gen7_atoms[] =
 178 {
 179    &brw_vs_prog,
 180    &brw_wm_prog,
 181
 182    /* Command packets: */
 183
 184    /* must do before binding table pointers, cc state ptrs */
 185    &brw_state_base_address,
 186
 187    &brw_cc_vp,
 188    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 189    &gen7_sf_clip_viewport,
 190
 191    &gen7_push_constant_space,
 192    &gen7_urb,
 193    &gen6_blend_state,           /* must do before cc unit */
 194    &gen6_color_calc_state,      /* must do before cc unit */
 195    &gen6_depth_stencil_state,   /* must do before cc unit */
 196
 197    &gen6_vs_push_constants, /* Before vs_state */
 198    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 199
 200    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 201     * table upload must be last.
 202     */
 203    &brw_vs_pull_constants,
 204    &brw_vs_ubo_surfaces,
 205    &brw_wm_pull_constants,
 206    &brw_wm_ubo_surfaces,
 207    &gen6_renderbuffer_surfaces,
 208    &brw_texture_surfaces,
 209    &brw_vs_binding_table,
 210    &brw_wm_binding_table,
 211
 212    &brw_fs_samplers,
 213    &brw_vs_samplers,
 214    &gen6_multisample_state,
 215
 216    &gen7_disable_stages,
 217    &gen7_vs_state,
 218    &gen7_sol_state,
 219    &gen7_clip_state,
 220    &gen7_sbe_state,
 221    &gen7_sf_state,
 222    &gen7_wm_state,
 223    &gen7_ps_state,
 224
 225    &gen6_scissor_state,
 226
 227    &gen7_depthbuffer,
 228
 229    &brw_polygon_stipple,
 230    &brw_polygon_stipple_offset,
 231
 232    &brw_line_stipple,
 233    &brw_aa_line_parameters,
 234
 235    &brw_drawing_rect,
 236
 237    &brw_indices,
 238    &brw_index_buffer,
 239    &brw_vertices,
 240
 241    &haswell_cut_index,
 242 };
 243
 244 static void
 245 brw_upload_initial_gpu_state(struct brw_context *brw)
 246 {
 247    /* On platforms with hardware contexts, we can set our initial GPU state
 248     * right away rather than doing it via state atoms.  This saves a small
 249     * amount of overhead on every draw call.
 250     */
 251    if (!brw->hw_ctx)
 252       return;
 253
 254    brw_upload_invariant_state(brw);
 255 }
 256
 257 void brw_init_state( struct brw_context *brw )
 258 {
 259    const struct brw_tracked_state **atoms;
 260    int num_atoms;
 261
 262    brw_init_caches(brw);
 263
 264    if (brw->gen >= 7) {
 265       atoms = gen7_atoms;
 266       num_atoms = ARRAY_SIZE(gen7_atoms);
 267    } else if (brw->gen == 6) {
 268       atoms = gen6_atoms;
 269       num_atoms = ARRAY_SIZE(gen6_atoms);
 270    } else {
 271       atoms = gen4_atoms;
 272       num_atoms = ARRAY_SIZE(gen4_atoms);
 273    }
 274
 275    brw->atoms = atoms;
 276    brw->num_atoms = num_atoms;
 277
 278    while (num_atoms--) {
 279       assert((*atoms)->dirty.mesa |
 280              (*atoms)->dirty.brw |
 281              (*atoms)->dirty.cache);
 282       assert((*atoms)->emit);
 283       atoms++;
 284    }
 285
 286    brw_upload_initial_gpu_state(brw);
 287 }
 288
 289
 290 void brw_destroy_state( struct brw_context *brw )
 291 {
 292    brw_destroy_caches(brw);
 293 }
 294
 295 /***********************************************************************
 296  */
 297
 298 static bool
 299 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 300 {
 301    return ((a->mesa & b->mesa) |
 302            (a->brw & b->brw) |
 303            (a->cache & b->cache)) != 0;
 304 }
 305
 306 static void accumulate_state( struct brw_state_flags *a,
 307                               const struct brw_state_flags *b )
 308 {
 309    a->mesa |= b->mesa;
 310    a->brw |= b->brw;
 311    a->cache |= b->cache;
 312 }
 313
 314
 315 static void xor_states( struct brw_state_flags *result,
 316                              const struct brw_state_flags *a,
 317                               const struct brw_state_flags *b )
 318 {
 319    result->mesa = a->mesa ^ b->mesa;
 320    result->brw = a->brw ^ b->brw;
 321    result->cache = a->cache ^ b->cache;
 322 }
 323
 324 struct dirty_bit_map {
 325    uint32_t bit;
 326    char *name;
 327    uint32_t count;
 328 };
 329
 330 #define DEFINE_BIT(name) {name, #name, 0}
 331
 332 static struct dirty_bit_map mesa_bits[] = {
 333    DEFINE_BIT(_NEW_MODELVIEW),
 334    DEFINE_BIT(_NEW_PROJECTION),
 335    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 336    DEFINE_BIT(_NEW_COLOR),
 337    DEFINE_BIT(_NEW_DEPTH),
 338    DEFINE_BIT(_NEW_EVAL),
 339    DEFINE_BIT(_NEW_FOG),
 340    DEFINE_BIT(_NEW_HINT),
 341    DEFINE_BIT(_NEW_LIGHT),
 342    DEFINE_BIT(_NEW_LINE),
 343    DEFINE_BIT(_NEW_PIXEL),
 344    DEFINE_BIT(_NEW_POINT),
 345    DEFINE_BIT(_NEW_POLYGON),
 346    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 347    DEFINE_BIT(_NEW_SCISSOR),
 348    DEFINE_BIT(_NEW_STENCIL),
 349    DEFINE_BIT(_NEW_TEXTURE),
 350    DEFINE_BIT(_NEW_TRANSFORM),
 351    DEFINE_BIT(_NEW_VIEWPORT),
 352    DEFINE_BIT(_NEW_ARRAY),
 353    DEFINE_BIT(_NEW_RENDERMODE),
 354    DEFINE_BIT(_NEW_BUFFERS),
 355    DEFINE_BIT(_NEW_MULTISAMPLE),
 356    DEFINE_BIT(_NEW_TRACK_MATRIX),
 357    DEFINE_BIT(_NEW_PROGRAM),
 358    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 359    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 360    DEFINE_BIT(_NEW_FRAG_CLAMP),
 361    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 362    {0, 0, 0}
 363 };
 364
 365 static struct dirty_bit_map brw_bits[] = {
 366    DEFINE_BIT(BRW_NEW_URB_FENCE),
 367    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 368    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 369    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 370    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 371    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 372    DEFINE_BIT(BRW_NEW_CONTEXT),
 373    DEFINE_BIT(BRW_NEW_PSP),
 374    DEFINE_BIT(BRW_NEW_SURFACES),
 375    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 376    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 377    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 378    DEFINE_BIT(BRW_NEW_INDICES),
 379    DEFINE_BIT(BRW_NEW_VERTICES),
 380    DEFINE_BIT(BRW_NEW_BATCH),
 381    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 382    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 383    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 384    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 385    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 386    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 387    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 388    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 389    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 390    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 391    {0, 0, 0}
 392 };
 393
 394 static struct dirty_bit_map cache_bits[] = {
 395    DEFINE_BIT(CACHE_NEW_CC_VP),
 396    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 397    DEFINE_BIT(CACHE_NEW_WM_PROG),
 398    DEFINE_BIT(CACHE_NEW_SAMPLER),
 399    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 400    DEFINE_BIT(CACHE_NEW_SF_PROG),
 401    DEFINE_BIT(CACHE_NEW_SF_VP),
 402    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 403    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 404    DEFINE_BIT(CACHE_NEW_VS_PROG),
 405    DEFINE_BIT(CACHE_NEW_FF_GS_UNIT),
 406    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 407    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 408    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 409    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 410    {0, 0, 0}
 411 };
 412
 413
 414 static void
 415 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 416 {
 417    int i;
 418
 419    for (i = 0; i < 32; i++) {
 420       if (bit_map[i].bit == 0)
 421          return;
 422
 423       if (bit_map[i].bit & bits)
 424          bit_map[i].count++;
 425    }
 426 }
 427
 428 static void
 429 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 430 {
 431    int i;
 432
 433    for (i = 0; i < 32; i++) {
 434       if (bit_map[i].bit == 0)
 435          return;
 436
 437       fprintf(stderr, "0x%08x: %12d (%s)\n",
 438               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 439    }
 440 }
 441
 442 /***********************************************************************
 443  * Emit all state:
 444  */
 445 void brw_upload_state(struct brw_context *brw)
 446 {
 447    struct gl_context *ctx = &brw->ctx;
 448    struct brw_state_flags *state = &brw->state.dirty;
 449    int i;
 450    static int dirty_count = 0;
 451
 452    state->mesa |= brw->NewGLState;
 453    brw->NewGLState = 0;
 454
 455    state->brw |= ctx->NewDriverState;
 456    ctx->NewDriverState = 0;
 457
 458    if (brw->emit_state_always) {
 459       state->mesa |= ~0;
 460       state->brw |= ~0;
 461       state->cache |= ~0;
 462    }
 463
 464    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 465       brw->fragment_program = ctx->FragmentProgram._Current;
 466       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 467    }
 468
 469    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 470       brw->geometry_program = ctx->GeometryProgram._Current;
 471       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 472    }
 473
 474    if (brw->vertex_program != ctx->VertexProgram._Current) {
 475       brw->vertex_program = ctx->VertexProgram._Current;
 476       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 477    }
 478
 479    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 480       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 481       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 482    }
 483
 484    if ((state->mesa | state->cache | state->brw) == 0)
 485       return;
 486
 487    intel_check_front_buffer_rendering(brw);
 488
 489    if (unlikely(INTEL_DEBUG)) {
 490       /* Debug version which enforces various sanity checks on the
 491        * state flags which are generated and checked to help ensure
 492        * state atoms are ordered correctly in the list.
 493        */
 494       struct brw_state_flags examined, prev;
 495       memset(&examined, 0, sizeof(examined));
 496       prev = *state;
 497
 498       for (i = 0; i < brw->num_atoms; i++) {
 499          const struct brw_tracked_state *atom = brw->atoms[i];
 500          struct brw_state_flags generated;
 501
 502          if (check_state(state, &atom->dirty)) {
 503             atom->emit(brw);
 504          }
 505
 506          accumulate_state(&examined, &atom->dirty);
 507
 508          /* generated = (prev ^ state)
 509           * if (examined & generated)
 510           *     fail;
 511           */
 512          xor_states(&generated, &prev, state);
 513          assert(!check_state(&examined, &generated));
 514          prev = *state;
 515       }
 516    }
 517    else {
 518       for (i = 0; i < brw->num_atoms; i++) {
 519          const struct brw_tracked_state *atom = brw->atoms[i];
 520
 521          if (check_state(state, &atom->dirty)) {
 522             atom->emit(brw);
 523          }
 524       }
 525    }
 526
 527    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 528       brw_update_dirty_count(mesa_bits, state->mesa);
 529       brw_update_dirty_count(brw_bits, state->brw);
 530       brw_update_dirty_count(cache_bits, state->cache);
 531       if (dirty_count++ % 1000 == 0) {
 532          brw_print_dirty_count(mesa_bits);
 533          brw_print_dirty_count(brw_bits);
 534          brw_print_dirty_count(cache_bits);
 535          fprintf(stderr, "\n");
 536       }
 537    }
 538
 539    memset(state, 0, sizeof(*state));
 540 }