2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "drivers/common/meta.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_buffers.h"
40 #include "brw_ff_gs.h"
44 #include "main/framebuffer.h"
46 static const struct brw_tracked_state
*gen4_atoms
[] =
48 &brw_interpolation_map
,
50 &brw_clip_prog
, /* must do before state base address */
51 &brw_sf_prog
, /* must do before state base address */
53 /* Once all the programs are done, we know how large urb entry
54 * sizes need to be and can decide if we need to change the urb
58 &brw_recalculate_urb_fence
,
63 /* Surface state setup. Must come before the VS/WM unit. The binding
64 * table upload must be last.
66 &brw_vs_pull_constants
,
67 &brw_wm_pull_constants
,
68 &brw_renderbuffer_surfaces
,
69 &brw_texture_surfaces
,
70 &brw_vs_binding_table
,
71 &brw_wm_binding_table
,
76 /* These set up state for brw_psp_urb_cbs */
80 &brw_vs_unit
, /* always required, enabled or not */
87 &brw_state_base_address
,
89 &brw_binding_table_pointers
,
90 &brw_blend_constant_color
,
95 &brw_polygon_stipple_offset
,
98 &brw_aa_line_parameters
,
103 &brw_indices
, /* must come before brw_vertices */
110 static const struct brw_tracked_state
*gen6_atoms
[] =
115 /* Command packets: */
117 /* must do before binding table pointers, cc state ptrs */
118 &brw_state_base_address
,
121 &gen6_viewport_state
, /* must do after *_vp stages */
124 &gen6_blend_state
, /* must do before cc unit */
125 &gen6_color_calc_state
, /* must do before cc unit */
126 &gen6_depth_stencil_state
, /* must do before cc unit */
128 &gen6_vs_push_constants
, /* Before vs_state */
129 &gen6_gs_push_constants
, /* Before gs_state */
130 &gen6_wm_push_constants
, /* Before wm_state */
132 /* Surface state setup. Must come before the VS/WM unit. The binding
133 * table upload must be last.
135 &brw_vs_pull_constants
,
136 &brw_vs_ubo_surfaces
,
137 &brw_gs_pull_constants
,
138 &brw_gs_ubo_surfaces
,
139 &brw_wm_pull_constants
,
140 &brw_wm_ubo_surfaces
,
141 &gen6_renderbuffer_surfaces
,
142 &brw_texture_surfaces
,
144 &brw_vs_binding_table
,
145 &gen6_gs_binding_table
,
146 &brw_wm_binding_table
,
152 &gen6_multisample_state
,
162 &gen6_binding_table_pointers
,
166 &brw_polygon_stipple
,
167 &brw_polygon_stipple_offset
,
170 &brw_aa_line_parameters
,
174 &brw_indices
, /* must come before brw_vertices */
179 static const struct brw_tracked_state
*gen7_render_atoms
[] =
181 /* Command packets: */
183 /* must do before binding table pointers, cc state ptrs */
184 &brw_state_base_address
,
187 &gen7_sf_clip_viewport
,
189 &gen7_push_constant_space
,
191 &gen6_blend_state
, /* must do before cc unit */
192 &gen6_color_calc_state
, /* must do before cc unit */
193 &gen6_depth_stencil_state
, /* must do before cc unit */
195 &gen7_hw_binding_tables
, /* Enable hw-generated binding tables for Haswell */
197 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
198 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
199 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
201 &gen6_vs_push_constants
, /* Before vs_state */
202 &gen6_gs_push_constants
, /* Before gs_state */
203 &gen6_wm_push_constants
, /* Before wm_surfaces and constant_buffer */
205 /* Surface state setup. Must come before the VS/WM unit. The binding
206 * table upload must be last.
208 &brw_vs_pull_constants
,
209 &brw_vs_ubo_surfaces
,
210 &brw_vs_abo_surfaces
,
211 &brw_gs_pull_constants
,
212 &brw_gs_ubo_surfaces
,
213 &brw_gs_abo_surfaces
,
214 &brw_wm_pull_constants
,
215 &brw_wm_ubo_surfaces
,
216 &brw_wm_abo_surfaces
,
217 &gen6_renderbuffer_surfaces
,
218 &brw_texture_surfaces
,
219 &brw_vs_binding_table
,
220 &brw_gs_binding_table
,
221 &brw_wm_binding_table
,
226 &gen6_multisample_state
,
228 &gen7_disable_stages
,
242 &brw_polygon_stipple
,
243 &brw_polygon_stipple_offset
,
246 &brw_aa_line_parameters
,
250 &brw_indices
, /* must come before brw_vertices */
257 static const struct brw_tracked_state
*gen7_compute_atoms
[] =
259 &brw_state_base_address
,
260 &brw_cs_image_surfaces
,
261 &gen7_cs_push_constants
,
262 &brw_cs_abo_surfaces
,
266 static const struct brw_tracked_state
*gen8_render_atoms
[] =
268 /* Command packets: */
269 &gen8_state_base_address
,
272 &gen8_sf_clip_viewport
,
274 &gen7_push_constant_space
,
277 &gen6_color_calc_state
,
279 &gen7_hw_binding_tables
, /* Enable hw-generated binding tables for Broadwell */
281 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
282 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
283 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
285 &gen6_vs_push_constants
, /* Before vs_state */
286 &gen6_gs_push_constants
, /* Before gs_state */
287 &gen6_wm_push_constants
, /* Before wm_surfaces and constant_buffer */
289 /* Surface state setup. Must come before the VS/WM unit. The binding
290 * table upload must be last.
292 &brw_vs_pull_constants
,
293 &brw_vs_ubo_surfaces
,
294 &brw_vs_abo_surfaces
,
295 &brw_gs_pull_constants
,
296 &brw_gs_ubo_surfaces
,
297 &brw_gs_abo_surfaces
,
298 &brw_wm_pull_constants
,
299 &brw_wm_ubo_surfaces
,
300 &brw_wm_abo_surfaces
,
301 &gen6_renderbuffer_surfaces
,
302 &brw_texture_surfaces
,
303 &brw_vs_binding_table
,
304 &brw_gs_binding_table
,
305 &brw_wm_binding_table
,
310 &gen8_multisample_state
,
312 &gen8_disable_stages
,
323 &gen8_wm_depth_stencil
,
330 &brw_polygon_stipple
,
331 &brw_polygon_stipple_offset
,
334 &brw_aa_line_parameters
,
348 static const struct brw_tracked_state
*gen8_compute_atoms
[] =
350 &gen8_state_base_address
,
351 &brw_cs_image_surfaces
,
352 &gen7_cs_push_constants
,
353 &brw_cs_abo_surfaces
,
358 brw_upload_initial_gpu_state(struct brw_context
*brw
)
360 /* On platforms with hardware contexts, we can set our initial GPU state
361 * right away rather than doing it via state atoms. This saves a small
362 * amount of overhead on every draw call.
368 brw_emit_post_sync_nonzero_flush(brw
);
370 brw_upload_invariant_state(brw
);
372 /* Recommended optimization for Victim Cache eviction in pixel backend. */
375 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
376 OUT_BATCH(GEN7_CACHE_MODE_1
);
377 OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
<< 16) |
378 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
);
383 gen8_emit_3dstate_sample_pattern(brw
);
387 static inline const struct brw_tracked_state
*
388 brw_get_pipeline_atoms(struct brw_context
*brw
,
389 enum brw_pipeline pipeline
)
392 case BRW_RENDER_PIPELINE
:
393 return brw
->render_atoms
;
394 case BRW_COMPUTE_PIPELINE
:
395 return brw
->compute_atoms
;
397 STATIC_ASSERT(BRW_NUM_PIPELINES
== 2);
398 unreachable("Unsupported pipeline");
404 brw_copy_pipeline_atoms(struct brw_context
*brw
,
405 enum brw_pipeline pipeline
,
406 const struct brw_tracked_state
**atoms
,
409 /* This is to work around brw_context::atoms being declared const. We want
410 * it to be const, but it needs to be initialized somehow!
412 struct brw_tracked_state
*context_atoms
=
413 (struct brw_tracked_state
*) brw_get_pipeline_atoms(brw
, pipeline
);
415 for (int i
= 0; i
< num_atoms
; i
++) {
416 context_atoms
[i
] = *atoms
[i
];
417 assert(context_atoms
[i
].dirty
.mesa
| context_atoms
[i
].dirty
.brw
);
418 assert(context_atoms
[i
].emit
);
421 brw
->num_atoms
[pipeline
] = num_atoms
;
424 void brw_init_state( struct brw_context
*brw
)
426 struct gl_context
*ctx
= &brw
->ctx
;
428 /* Force the first brw_select_pipeline to emit pipeline select */
429 brw
->last_pipeline
= BRW_NUM_PIPELINES
;
431 STATIC_ASSERT(ARRAY_SIZE(gen4_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
432 STATIC_ASSERT(ARRAY_SIZE(gen6_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
433 STATIC_ASSERT(ARRAY_SIZE(gen7_render_atoms
) <=
434 ARRAY_SIZE(brw
->render_atoms
));
435 STATIC_ASSERT(ARRAY_SIZE(gen8_render_atoms
) <=
436 ARRAY_SIZE(brw
->render_atoms
));
437 STATIC_ASSERT(ARRAY_SIZE(gen7_compute_atoms
) <=
438 ARRAY_SIZE(brw
->compute_atoms
));
439 STATIC_ASSERT(ARRAY_SIZE(gen8_compute_atoms
) <=
440 ARRAY_SIZE(brw
->compute_atoms
));
442 brw_init_caches(brw
);
445 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
447 ARRAY_SIZE(gen8_render_atoms
));
448 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
450 ARRAY_SIZE(gen8_compute_atoms
));
451 } else if (brw
->gen
== 7) {
452 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
454 ARRAY_SIZE(gen7_render_atoms
));
455 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
457 ARRAY_SIZE(gen7_compute_atoms
));
458 } else if (brw
->gen
== 6) {
459 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
460 gen6_atoms
, ARRAY_SIZE(gen6_atoms
));
462 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
463 gen4_atoms
, ARRAY_SIZE(gen4_atoms
));
466 brw_upload_initial_gpu_state(brw
);
468 brw
->NewGLState
= ~0;
469 brw
->ctx
.NewDriverState
= ~0ull;
471 /* ~0 is a nonsensical value which won't match anything we program, so
472 * the programming will take effect on the first time around.
474 brw
->pma_stall_bits
= ~0;
476 /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
479 STATIC_ASSERT(BRW_NUM_STATE_BITS
<= 8 * sizeof(brw
->ctx
.NewDriverState
));
481 ctx
->DriverFlags
.NewTransformFeedback
= BRW_NEW_TRANSFORM_FEEDBACK
;
482 ctx
->DriverFlags
.NewTransformFeedbackProg
= BRW_NEW_TRANSFORM_FEEDBACK
;
483 ctx
->DriverFlags
.NewRasterizerDiscard
= BRW_NEW_RASTERIZER_DISCARD
;
484 ctx
->DriverFlags
.NewUniformBuffer
= BRW_NEW_UNIFORM_BUFFER
;
485 ctx
->DriverFlags
.NewTextureBuffer
= BRW_NEW_TEXTURE_BUFFER
;
486 ctx
->DriverFlags
.NewAtomicBuffer
= BRW_NEW_ATOMIC_BUFFER
;
487 ctx
->DriverFlags
.NewImageUnits
= BRW_NEW_IMAGE_UNITS
;
491 void brw_destroy_state( struct brw_context
*brw
)
493 brw_destroy_caches(brw
);
496 /***********************************************************************
500 check_state(const struct brw_state_flags
*a
, const struct brw_state_flags
*b
)
502 return ((a
->mesa
& b
->mesa
) | (a
->brw
& b
->brw
)) != 0;
505 static void accumulate_state( struct brw_state_flags
*a
,
506 const struct brw_state_flags
*b
)
513 static void xor_states( struct brw_state_flags
*result
,
514 const struct brw_state_flags
*a
,
515 const struct brw_state_flags
*b
)
517 result
->mesa
= a
->mesa
^ b
->mesa
;
518 result
->brw
= a
->brw
^ b
->brw
;
521 struct dirty_bit_map
{
527 #define DEFINE_BIT(name) {name, #name, 0}
529 static struct dirty_bit_map mesa_bits
[] = {
530 DEFINE_BIT(_NEW_MODELVIEW
),
531 DEFINE_BIT(_NEW_PROJECTION
),
532 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
533 DEFINE_BIT(_NEW_COLOR
),
534 DEFINE_BIT(_NEW_DEPTH
),
535 DEFINE_BIT(_NEW_EVAL
),
536 DEFINE_BIT(_NEW_FOG
),
537 DEFINE_BIT(_NEW_HINT
),
538 DEFINE_BIT(_NEW_LIGHT
),
539 DEFINE_BIT(_NEW_LINE
),
540 DEFINE_BIT(_NEW_PIXEL
),
541 DEFINE_BIT(_NEW_POINT
),
542 DEFINE_BIT(_NEW_POLYGON
),
543 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
544 DEFINE_BIT(_NEW_SCISSOR
),
545 DEFINE_BIT(_NEW_STENCIL
),
546 DEFINE_BIT(_NEW_TEXTURE
),
547 DEFINE_BIT(_NEW_TRANSFORM
),
548 DEFINE_BIT(_NEW_VIEWPORT
),
549 DEFINE_BIT(_NEW_ARRAY
),
550 DEFINE_BIT(_NEW_RENDERMODE
),
551 DEFINE_BIT(_NEW_BUFFERS
),
552 DEFINE_BIT(_NEW_CURRENT_ATTRIB
),
553 DEFINE_BIT(_NEW_MULTISAMPLE
),
554 DEFINE_BIT(_NEW_TRACK_MATRIX
),
555 DEFINE_BIT(_NEW_PROGRAM
),
556 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
557 DEFINE_BIT(_NEW_BUFFER_OBJECT
),
558 DEFINE_BIT(_NEW_FRAG_CLAMP
),
559 /* Avoid sign extension problems. */
560 {(unsigned) _NEW_VARYING_VP_INPUTS
, "_NEW_VARYING_VP_INPUTS", 0},
564 static struct dirty_bit_map brw_bits
[] = {
565 DEFINE_BIT(BRW_NEW_FS_PROG_DATA
),
566 DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA
),
567 DEFINE_BIT(BRW_NEW_SF_PROG_DATA
),
568 DEFINE_BIT(BRW_NEW_VS_PROG_DATA
),
569 DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA
),
570 DEFINE_BIT(BRW_NEW_GS_PROG_DATA
),
571 DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA
),
572 DEFINE_BIT(BRW_NEW_CS_PROG_DATA
),
573 DEFINE_BIT(BRW_NEW_URB_FENCE
),
574 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
575 DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM
),
576 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
577 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS
),
578 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
579 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
580 DEFINE_BIT(BRW_NEW_CONTEXT
),
581 DEFINE_BIT(BRW_NEW_PSP
),
582 DEFINE_BIT(BRW_NEW_SURFACES
),
583 DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE
),
584 DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE
),
585 DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE
),
586 DEFINE_BIT(BRW_NEW_INDICES
),
587 DEFINE_BIT(BRW_NEW_VERTICES
),
588 DEFINE_BIT(BRW_NEW_BATCH
),
589 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
590 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
591 DEFINE_BIT(BRW_NEW_GS_CONSTBUF
),
592 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
593 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
594 DEFINE_BIT(BRW_NEW_VUE_MAP_VS
),
595 DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT
),
596 DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK
),
597 DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD
),
598 DEFINE_BIT(BRW_NEW_STATS_WM
),
599 DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER
),
600 DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER
),
601 DEFINE_BIT(BRW_NEW_IMAGE_UNITS
),
602 DEFINE_BIT(BRW_NEW_META_IN_PROGRESS
),
603 DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP
),
604 DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
605 DEFINE_BIT(BRW_NEW_NUM_SAMPLES
),
606 DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER
),
607 DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE
),
608 DEFINE_BIT(BRW_NEW_CC_VP
),
609 DEFINE_BIT(BRW_NEW_SF_VP
),
610 DEFINE_BIT(BRW_NEW_CLIP_VP
),
611 DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE
),
612 DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS
),
613 DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM
),
618 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, uint64_t bits
)
620 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
621 if (bit_map
[i
].bit
& bits
)
627 brw_print_dirty_count(struct dirty_bit_map
*bit_map
)
629 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
630 if (bit_map
[i
].count
> 1) {
631 fprintf(stderr
, "0x%016lx: %12d (%s)\n",
632 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
638 brw_upload_programs(struct brw_context
*brw
,
639 enum brw_pipeline pipeline
)
641 if (pipeline
== BRW_RENDER_PIPELINE
) {
642 brw_upload_vs_prog(brw
);
645 brw_upload_ff_gs_prog(brw
);
647 brw_upload_gs_prog(brw
);
649 brw_upload_wm_prog(brw
);
650 } else if (pipeline
== BRW_COMPUTE_PIPELINE
) {
651 brw_upload_cs_prog(brw
);
656 merge_ctx_state(struct brw_context
*brw
,
657 struct brw_state_flags
*state
)
659 state
->mesa
|= brw
->NewGLState
;
660 state
->brw
|= brw
->ctx
.NewDriverState
;
664 check_and_emit_atom(struct brw_context
*brw
,
665 struct brw_state_flags
*state
,
666 const struct brw_tracked_state
*atom
)
668 if (check_state(state
, &atom
->dirty
)) {
670 merge_ctx_state(brw
, state
);
675 brw_upload_pipeline_state(struct brw_context
*brw
,
676 enum brw_pipeline pipeline
)
678 struct gl_context
*ctx
= &brw
->ctx
;
680 static int dirty_count
= 0;
681 struct brw_state_flags state
= brw
->state
.pipelines
[pipeline
];
682 unsigned int fb_samples
= _mesa_geometric_samples(ctx
->DrawBuffer
);
684 brw_select_pipeline(brw
, pipeline
);
687 /* Always re-emit all state. */
688 brw
->NewGLState
= ~0;
689 ctx
->NewDriverState
= ~0ull;
692 if (pipeline
== BRW_RENDER_PIPELINE
) {
693 if (brw
->fragment_program
!= ctx
->FragmentProgram
._Current
) {
694 brw
->fragment_program
= ctx
->FragmentProgram
._Current
;
695 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
698 if (brw
->geometry_program
!= ctx
->GeometryProgram
._Current
) {
699 brw
->geometry_program
= ctx
->GeometryProgram
._Current
;
700 brw
->ctx
.NewDriverState
|= BRW_NEW_GEOMETRY_PROGRAM
;
703 if (brw
->vertex_program
!= ctx
->VertexProgram
._Current
) {
704 brw
->vertex_program
= ctx
->VertexProgram
._Current
;
705 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
709 if (brw
->compute_program
!= ctx
->ComputeProgram
._Current
) {
710 brw
->compute_program
= ctx
->ComputeProgram
._Current
;
711 brw
->ctx
.NewDriverState
|= BRW_NEW_COMPUTE_PROGRAM
;
714 if (brw
->meta_in_progress
!= _mesa_meta_in_progress(ctx
)) {
715 brw
->meta_in_progress
= _mesa_meta_in_progress(ctx
);
716 brw
->ctx
.NewDriverState
|= BRW_NEW_META_IN_PROGRESS
;
719 if (brw
->num_samples
!= fb_samples
) {
720 brw
->num_samples
= fb_samples
;
721 brw
->ctx
.NewDriverState
|= BRW_NEW_NUM_SAMPLES
;
724 /* Exit early if no state is flagged as dirty */
725 merge_ctx_state(brw
, &state
);
726 if ((state
.mesa
| state
.brw
) == 0)
729 /* Emit Sandybridge workaround flushes on every primitive, for safety. */
731 brw_emit_post_sync_nonzero_flush(brw
);
733 brw_upload_programs(brw
, pipeline
);
734 merge_ctx_state(brw
, &state
);
736 const struct brw_tracked_state
*atoms
=
737 brw_get_pipeline_atoms(brw
, pipeline
);
738 const int num_atoms
= brw
->num_atoms
[pipeline
];
740 if (unlikely(INTEL_DEBUG
)) {
741 /* Debug version which enforces various sanity checks on the
742 * state flags which are generated and checked to help ensure
743 * state atoms are ordered correctly in the list.
745 struct brw_state_flags examined
, prev
;
746 memset(&examined
, 0, sizeof(examined
));
749 for (i
= 0; i
< num_atoms
; i
++) {
750 const struct brw_tracked_state
*atom
= &atoms
[i
];
751 struct brw_state_flags generated
;
753 check_and_emit_atom(brw
, &state
, atom
);
755 accumulate_state(&examined
, &atom
->dirty
);
757 /* generated = (prev ^ state)
758 * if (examined & generated)
761 xor_states(&generated
, &prev
, &state
);
762 assert(!check_state(&examined
, &generated
));
767 for (i
= 0; i
< num_atoms
; i
++) {
768 const struct brw_tracked_state
*atom
= &atoms
[i
];
770 check_and_emit_atom(brw
, &state
, atom
);
774 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
775 STATIC_ASSERT(ARRAY_SIZE(brw_bits
) == BRW_NUM_STATE_BITS
+ 1);
777 brw_update_dirty_count(mesa_bits
, state
.mesa
);
778 brw_update_dirty_count(brw_bits
, state
.brw
);
779 if (dirty_count
++ % 1000 == 0) {
780 brw_print_dirty_count(mesa_bits
);
781 brw_print_dirty_count(brw_bits
);
782 fprintf(stderr
, "\n");
787 /***********************************************************************
790 void brw_upload_render_state(struct brw_context
*brw
)
792 brw_upload_pipeline_state(brw
, BRW_RENDER_PIPELINE
);
796 brw_pipeline_state_finished(struct brw_context
*brw
,
797 enum brw_pipeline pipeline
)
799 /* Save all dirty state into the other pipelines */
800 for (int i
= 0; i
< BRW_NUM_PIPELINES
; i
++) {
802 brw
->state
.pipelines
[i
].mesa
|= brw
->NewGLState
;
803 brw
->state
.pipelines
[i
].brw
|= brw
->ctx
.NewDriverState
;
805 memset(&brw
->state
.pipelines
[i
], 0, sizeof(struct brw_state_flags
));
810 brw
->ctx
.NewDriverState
= 0ull;
814 * Clear dirty bits to account for the fact that the state emitted by
815 * brw_upload_render_state() has been committed to the hardware. This is a
816 * separate call from brw_upload_render_state() because it's possible that
817 * after the call to brw_upload_render_state(), we will discover that we've
818 * run out of aperture space, and need to rewind the batch buffer to the state
819 * it had before the brw_upload_render_state() call.
822 brw_render_state_finished(struct brw_context
*brw
)
824 brw_pipeline_state_finished(brw
, BRW_RENDER_PIPELINE
);
828 brw_upload_compute_state(struct brw_context
*brw
)
830 brw_upload_pipeline_state(brw
, BRW_COMPUTE_PIPELINE
);
834 brw_compute_state_finished(struct brw_context
*brw
)
836 brw_pipeline_state_finished(brw
, BRW_COMPUTE_PIPELINE
);