src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_ff_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_wm_push_constants, /* Before wm_state */
 132
 133    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 134     * table upload must be last.
 135     */
 136    &brw_vs_pull_constants,
 137    &brw_vs_ubo_surfaces,
 138    &brw_wm_pull_constants,
 139    &brw_wm_ubo_surfaces,
 140    &gen6_renderbuffer_surfaces,
 141    &brw_texture_surfaces,
 142    &gen6_sol_surface,
 143    &brw_vs_binding_table,
 144    &gen6_gs_binding_table,
 145    &brw_wm_binding_table,
 146
 147    &brw_fs_samplers,
 148    &brw_vs_samplers,
 149    &gen6_sampler_state,
 150    &gen6_multisample_state,
 151
 152    &gen6_vs_state,
 153    &gen6_gs_state,
 154    &gen6_clip_state,
 155    &gen6_sf_state,
 156    &gen6_wm_state,
 157
 158    &gen6_scissor_state,
 159
 160    &gen6_binding_table_pointers,
 161
 162    &brw_depthbuffer,
 163
 164    &brw_polygon_stipple,
 165    &brw_polygon_stipple_offset,
 166
 167    &brw_line_stipple,
 168    &brw_aa_line_parameters,
 169
 170    &brw_drawing_rect,
 171
 172    &brw_indices,
 173    &brw_index_buffer,
 174    &brw_vertices,
 175 };
 176
 177 static const struct brw_tracked_state *gen7_atoms[] =
 178 {
 179    &brw_vs_prog,
 180    &brw_gs_prog,
 181    &brw_wm_prog,
 182
 183    /* Command packets: */
 184
 185    /* must do before binding table pointers, cc state ptrs */
 186    &brw_state_base_address,
 187
 188    &brw_cc_vp,
 189    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 190    &gen7_sf_clip_viewport,
 191
 192    &gen7_push_constant_space,
 193    &gen7_urb,
 194    &gen6_blend_state,           /* must do before cc unit */
 195    &gen6_color_calc_state,      /* must do before cc unit */
 196    &gen6_depth_stencil_state,   /* must do before cc unit */
 197
 198    &gen6_vs_push_constants, /* Before vs_state */
 199    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 200
 201    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 202     * table upload must be last.
 203     */
 204    &brw_vs_pull_constants,
 205    &brw_vs_ubo_surfaces,
 206    &brw_gs_pull_constants,
 207    &brw_gs_ubo_surfaces,
 208    &brw_wm_pull_constants,
 209    &brw_wm_ubo_surfaces,
 210    &gen6_renderbuffer_surfaces,
 211    &brw_texture_surfaces,
 212    &brw_vs_binding_table,
 213    &brw_gs_binding_table,
 214    &brw_wm_binding_table,
 215
 216    &brw_fs_samplers,
 217    &brw_vs_samplers,
 218    &brw_gs_samplers,
 219    &gen6_multisample_state,
 220
 221    &gen7_disable_stages,
 222    &gen7_vs_state,
 223    &gen7_sol_state,
 224    &gen7_clip_state,
 225    &gen7_sbe_state,
 226    &gen7_sf_state,
 227    &gen7_wm_state,
 228    &gen7_ps_state,
 229
 230    &gen6_scissor_state,
 231
 232    &gen7_depthbuffer,
 233
 234    &brw_polygon_stipple,
 235    &brw_polygon_stipple_offset,
 236
 237    &brw_line_stipple,
 238    &brw_aa_line_parameters,
 239
 240    &brw_drawing_rect,
 241
 242    &brw_indices,
 243    &brw_index_buffer,
 244    &brw_vertices,
 245
 246    &haswell_cut_index,
 247 };
 248
 249 static void
 250 brw_upload_initial_gpu_state(struct brw_context *brw)
 251 {
 252    /* On platforms with hardware contexts, we can set our initial GPU state
 253     * right away rather than doing it via state atoms.  This saves a small
 254     * amount of overhead on every draw call.
 255     */
 256    if (!brw->hw_ctx)
 257       return;
 258
 259    brw_upload_invariant_state(brw);
 260 }
 261
 262 void brw_init_state( struct brw_context *brw )
 263 {
 264    const struct brw_tracked_state **atoms;
 265    int num_atoms;
 266
 267    brw_init_caches(brw);
 268
 269    if (brw->gen >= 7) {
 270       atoms = gen7_atoms;
 271       num_atoms = ARRAY_SIZE(gen7_atoms);
 272    } else if (brw->gen == 6) {
 273       atoms = gen6_atoms;
 274       num_atoms = ARRAY_SIZE(gen6_atoms);
 275    } else {
 276       atoms = gen4_atoms;
 277       num_atoms = ARRAY_SIZE(gen4_atoms);
 278    }
 279
 280    brw->atoms = atoms;
 281    brw->num_atoms = num_atoms;
 282
 283    while (num_atoms--) {
 284       assert((*atoms)->dirty.mesa |
 285              (*atoms)->dirty.brw |
 286              (*atoms)->dirty.cache);
 287       assert((*atoms)->emit);
 288       atoms++;
 289    }
 290
 291    brw_upload_initial_gpu_state(brw);
 292 }
 293
 294
 295 void brw_destroy_state( struct brw_context *brw )
 296 {
 297    brw_destroy_caches(brw);
 298 }
 299
 300 /***********************************************************************
 301  */
 302
 303 static bool
 304 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 305 {
 306    return ((a->mesa & b->mesa) |
 307            (a->brw & b->brw) |
 308            (a->cache & b->cache)) != 0;
 309 }
 310
 311 static void accumulate_state( struct brw_state_flags *a,
 312                               const struct brw_state_flags *b )
 313 {
 314    a->mesa |= b->mesa;
 315    a->brw |= b->brw;
 316    a->cache |= b->cache;
 317 }
 318
 319
 320 static void xor_states( struct brw_state_flags *result,
 321                              const struct brw_state_flags *a,
 322                               const struct brw_state_flags *b )
 323 {
 324    result->mesa = a->mesa ^ b->mesa;
 325    result->brw = a->brw ^ b->brw;
 326    result->cache = a->cache ^ b->cache;
 327 }
 328
 329 struct dirty_bit_map {
 330    uint32_t bit;
 331    char *name;
 332    uint32_t count;
 333 };
 334
 335 #define DEFINE_BIT(name) {name, #name, 0}
 336
 337 static struct dirty_bit_map mesa_bits[] = {
 338    DEFINE_BIT(_NEW_MODELVIEW),
 339    DEFINE_BIT(_NEW_PROJECTION),
 340    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 341    DEFINE_BIT(_NEW_COLOR),
 342    DEFINE_BIT(_NEW_DEPTH),
 343    DEFINE_BIT(_NEW_EVAL),
 344    DEFINE_BIT(_NEW_FOG),
 345    DEFINE_BIT(_NEW_HINT),
 346    DEFINE_BIT(_NEW_LIGHT),
 347    DEFINE_BIT(_NEW_LINE),
 348    DEFINE_BIT(_NEW_PIXEL),
 349    DEFINE_BIT(_NEW_POINT),
 350    DEFINE_BIT(_NEW_POLYGON),
 351    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 352    DEFINE_BIT(_NEW_SCISSOR),
 353    DEFINE_BIT(_NEW_STENCIL),
 354    DEFINE_BIT(_NEW_TEXTURE),
 355    DEFINE_BIT(_NEW_TRANSFORM),
 356    DEFINE_BIT(_NEW_VIEWPORT),
 357    DEFINE_BIT(_NEW_ARRAY),
 358    DEFINE_BIT(_NEW_RENDERMODE),
 359    DEFINE_BIT(_NEW_BUFFERS),
 360    DEFINE_BIT(_NEW_MULTISAMPLE),
 361    DEFINE_BIT(_NEW_TRACK_MATRIX),
 362    DEFINE_BIT(_NEW_PROGRAM),
 363    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 364    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 365    DEFINE_BIT(_NEW_FRAG_CLAMP),
 366    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 367    {0, 0, 0}
 368 };
 369
 370 static struct dirty_bit_map brw_bits[] = {
 371    DEFINE_BIT(BRW_NEW_URB_FENCE),
 372    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 373    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 374    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 375    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 376    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 377    DEFINE_BIT(BRW_NEW_CONTEXT),
 378    DEFINE_BIT(BRW_NEW_PSP),
 379    DEFINE_BIT(BRW_NEW_SURFACES),
 380    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 381    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 382    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 383    DEFINE_BIT(BRW_NEW_INDICES),
 384    DEFINE_BIT(BRW_NEW_VERTICES),
 385    DEFINE_BIT(BRW_NEW_BATCH),
 386    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 387    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 388    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 389    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 390    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 391    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 392    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 393    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 394    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 395    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 396    {0, 0, 0}
 397 };
 398
 399 static struct dirty_bit_map cache_bits[] = {
 400    DEFINE_BIT(CACHE_NEW_CC_VP),
 401    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 402    DEFINE_BIT(CACHE_NEW_WM_PROG),
 403    DEFINE_BIT(CACHE_NEW_SAMPLER),
 404    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 405    DEFINE_BIT(CACHE_NEW_SF_PROG),
 406    DEFINE_BIT(CACHE_NEW_SF_VP),
 407    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 408    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 409    DEFINE_BIT(CACHE_NEW_VS_PROG),
 410    DEFINE_BIT(CACHE_NEW_FF_GS_UNIT),
 411    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 412    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 413    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 414    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 415    {0, 0, 0}
 416 };
 417
 418
 419 static void
 420 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 421 {
 422    int i;
 423
 424    for (i = 0; i < 32; i++) {
 425       if (bit_map[i].bit == 0)
 426          return;
 427
 428       if (bit_map[i].bit & bits)
 429          bit_map[i].count++;
 430    }
 431 }
 432
 433 static void
 434 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 435 {
 436    int i;
 437
 438    for (i = 0; i < 32; i++) {
 439       if (bit_map[i].bit == 0)
 440          return;
 441
 442       fprintf(stderr, "0x%08x: %12d (%s)\n",
 443               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 444    }
 445 }
 446
 447 /***********************************************************************
 448  * Emit all state:
 449  */
 450 void brw_upload_state(struct brw_context *brw)
 451 {
 452    struct gl_context *ctx = &brw->ctx;
 453    struct brw_state_flags *state = &brw->state.dirty;
 454    int i;
 455    static int dirty_count = 0;
 456
 457    state->mesa |= brw->NewGLState;
 458    brw->NewGLState = 0;
 459
 460    state->brw |= ctx->NewDriverState;
 461    ctx->NewDriverState = 0;
 462
 463    if (brw->emit_state_always) {
 464       state->mesa |= ~0;
 465       state->brw |= ~0;
 466       state->cache |= ~0;
 467    }
 468
 469    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 470       brw->fragment_program = ctx->FragmentProgram._Current;
 471       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 472    }
 473
 474    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 475       brw->geometry_program = ctx->GeometryProgram._Current;
 476       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 477    }
 478
 479    if (brw->vertex_program != ctx->VertexProgram._Current) {
 480       brw->vertex_program = ctx->VertexProgram._Current;
 481       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 482    }
 483
 484    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 485       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 486       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 487    }
 488
 489    if ((state->mesa | state->cache | state->brw) == 0)
 490       return;
 491
 492    intel_check_front_buffer_rendering(brw);
 493
 494    if (unlikely(INTEL_DEBUG)) {
 495       /* Debug version which enforces various sanity checks on the
 496        * state flags which are generated and checked to help ensure
 497        * state atoms are ordered correctly in the list.
 498        */
 499       struct brw_state_flags examined, prev;
 500       memset(&examined, 0, sizeof(examined));
 501       prev = *state;
 502
 503       for (i = 0; i < brw->num_atoms; i++) {
 504          const struct brw_tracked_state *atom = brw->atoms[i];
 505          struct brw_state_flags generated;
 506
 507          if (check_state(state, &atom->dirty)) {
 508             atom->emit(brw);
 509          }
 510
 511          accumulate_state(&examined, &atom->dirty);
 512
 513          /* generated = (prev ^ state)
 514           * if (examined & generated)
 515           *     fail;
 516           */
 517          xor_states(&generated, &prev, state);
 518          assert(!check_state(&examined, &generated));
 519          prev = *state;
 520       }
 521    }
 522    else {
 523       for (i = 0; i < brw->num_atoms; i++) {
 524          const struct brw_tracked_state *atom = brw->atoms[i];
 525
 526          if (check_state(state, &atom->dirty)) {
 527             atom->emit(brw);
 528          }
 529       }
 530    }
 531
 532    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 533       brw_update_dirty_count(mesa_bits, state->mesa);
 534       brw_update_dirty_count(brw_bits, state->brw);
 535       brw_update_dirty_count(cache_bits, state->cache);
 536       if (dirty_count++ % 1000 == 0) {
 537          brw_print_dirty_count(mesa_bits);
 538          brw_print_dirty_count(brw_bits);
 539          brw_print_dirty_count(cache_bits);
 540          fprintf(stderr, "\n");
 541       }
 542    }
 543
 544    memset(state, 0, sizeof(*state));
 545 }