src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  67     * table upload must be last.
  68     */
  69    &brw_vs_pull_constants,
  70    &brw_wm_pull_constants,
  71    &brw_renderbuffer_surfaces,
  72    &brw_texture_surfaces,
  73    &brw_binding_table,
  74
  75    &brw_samplers,
  76
  77    /* These set up state for brw_psp_urb_cbs */
  78    &brw_wm_unit,
  79    &brw_sf_vp,
  80    &brw_sf_unit,
  81    &brw_vs_unit,                /* always required, enabled or not */
  82    &brw_clip_unit,
  83    &brw_gs_unit,
  84
  85    /* Command packets:
  86     */
  87    &brw_invarient_state,
  88    &brw_state_base_address,
  89
  90    &brw_binding_table_pointers,
  91    &brw_blend_constant_color,
  92
  93    &brw_depthbuffer,
  94
  95    &brw_polygon_stipple,
  96    &brw_polygon_stipple_offset,
  97
  98    &brw_line_stipple,
  99    &brw_aa_line_parameters,
 100
 101    &brw_psp_urb_cbs,
 102
 103    &brw_drawing_rect,
 104    &brw_indices,
 105    &brw_index_buffer,
 106    &brw_vertices,
 107
 108    &brw_constant_buffer
 109 };
 110
 111 static const struct brw_tracked_state *gen6_atoms[] =
 112 {
 113    &brw_check_fallback,
 114
 115    &brw_wm_input_sizes,
 116    &brw_vs_prog, /* must do before state base address */
 117    &brw_gs_prog, /* must do before state base address */
 118    &brw_wm_prog, /* must do before state base address */
 119
 120    &gen6_clip_vp,
 121    &gen6_sf_vp,
 122
 123    /* Command packets: */
 124    &brw_invarient_state,
 125
 126    /* must do before binding table pointers, cc state ptrs */
 127    &brw_state_base_address,
 128
 129    &brw_cc_vp,
 130    &gen6_viewport_state,        /* must do after *_vp stages */
 131
 132    &gen6_urb,
 133    &gen6_blend_state,           /* must do before cc unit */
 134    &gen6_color_calc_state,      /* must do before cc unit */
 135    &gen6_depth_stencil_state,   /* must do before cc unit */
 136    &gen6_cc_state_pointers,
 137
 138    &gen6_vs_push_constants, /* Before vs_state */
 139    &gen6_wm_push_constants, /* Before wm_state */
 140
 141    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 142     * table upload must be last.
 143     */
 144    &brw_vs_pull_constants,
 145    &brw_wm_pull_constants,
 146    &gen6_renderbuffer_surfaces,
 147    &brw_texture_surfaces,
 148    &brw_binding_table,
 149
 150    &brw_samplers,
 151    &gen6_sampler_state,
 152
 153    &gen6_vs_state,
 154    &gen6_gs_state,
 155    &gen6_clip_state,
 156    &gen6_sf_state,
 157    &gen6_wm_state,
 158
 159    &gen6_scissor_state,
 160
 161    &gen6_binding_table_pointers,
 162
 163    &brw_depthbuffer,
 164
 165    &brw_polygon_stipple,
 166    &brw_polygon_stipple_offset,
 167
 168    &brw_line_stipple,
 169    &brw_aa_line_parameters,
 170
 171    &brw_drawing_rect,
 172
 173    &brw_indices,
 174    &brw_index_buffer,
 175    &brw_vertices,
 176 };
 177
 178 const struct brw_tracked_state *gen7_atoms[] =
 179 {
 180    &brw_check_fallback,
 181
 182    &brw_wm_input_sizes,
 183    &brw_vs_prog,
 184    &brw_gs_prog,
 185    &brw_wm_prog,
 186
 187    /* Command packets: */
 188    &brw_invarient_state,
 189
 190    /* must do before binding table pointers, cc state ptrs */
 191    &brw_state_base_address,
 192
 193    &brw_cc_vp,
 194    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 195    &gen7_sf_clip_viewport,
 196
 197    &gen7_urb,
 198    &gen6_blend_state,           /* must do before cc unit */
 199    &gen6_color_calc_state,      /* must do before cc unit */
 200    &gen6_depth_stencil_state,   /* must do before cc unit */
 201    &gen7_blend_state_pointer,
 202    &gen7_cc_state_pointer,
 203    &gen7_depth_stencil_state_pointer,
 204
 205    &gen6_vs_push_constants, /* Before vs_state */
 206    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 207
 208    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 209     * table upload must be last.
 210     */
 211    &brw_vs_pull_constants,
 212    &brw_wm_pull_constants,
 213    &gen6_renderbuffer_surfaces,
 214    &brw_texture_surfaces,
 215    &brw_binding_table,
 216
 217    &gen7_samplers,
 218
 219    &gen7_disable_stages,
 220    &gen7_vs_state,
 221    &gen7_clip_state,
 222    &gen7_sbe_state,
 223    &gen7_sf_state,
 224    &gen7_wm_state,
 225    &gen7_ps_state,
 226
 227    &gen6_scissor_state,
 228
 229    &gen7_depthbuffer,
 230
 231    &brw_polygon_stipple,
 232    &brw_polygon_stipple_offset,
 233
 234    &brw_line_stipple,
 235    &brw_aa_line_parameters,
 236
 237    &brw_drawing_rect,
 238
 239    &brw_indices,
 240    &brw_index_buffer,
 241    &brw_vertices,
 242 };
 243
 244
 245 void brw_init_state( struct brw_context *brw )
 246 {
 247    const struct brw_tracked_state **atoms;
 248    int num_atoms;
 249
 250    brw_init_caches(brw);
 251
 252    if (brw->intel.gen >= 7) {
 253       atoms = gen7_atoms;
 254       num_atoms = ARRAY_SIZE(gen7_atoms);
 255    } else if (brw->intel.gen == 6) {
 256       atoms = gen6_atoms;
 257       num_atoms = ARRAY_SIZE(gen6_atoms);
 258    } else {
 259       atoms = gen4_atoms;
 260       num_atoms = ARRAY_SIZE(gen4_atoms);
 261    }
 262
 263    brw->atoms = atoms;
 264    brw->num_atoms = num_atoms;
 265
 266    while (num_atoms--) {
 267       assert((*atoms)->dirty.mesa |
 268              (*atoms)->dirty.brw |
 269              (*atoms)->dirty.cache);
 270       assert((*atoms)->emit);
 271       atoms++;
 272    }
 273 }
 274
 275
 276 void brw_destroy_state( struct brw_context *brw )
 277 {
 278    brw_destroy_caches(brw);
 279 }
 280
 281 /***********************************************************************
 282  */
 283
 284 static GLuint check_state( const struct brw_state_flags *a,
 285                            const struct brw_state_flags *b )
 286 {
 287    return ((a->mesa & b->mesa) |
 288            (a->brw & b->brw) |
 289            (a->cache & b->cache)) != 0;
 290 }
 291
 292 static void accumulate_state( struct brw_state_flags *a,
 293                               const struct brw_state_flags *b )
 294 {
 295    a->mesa |= b->mesa;
 296    a->brw |= b->brw;
 297    a->cache |= b->cache;
 298 }
 299
 300
 301 static void xor_states( struct brw_state_flags *result,
 302                              const struct brw_state_flags *a,
 303                               const struct brw_state_flags *b )
 304 {
 305    result->mesa = a->mesa ^ b->mesa;
 306    result->brw = a->brw ^ b->brw;
 307    result->cache = a->cache ^ b->cache;
 308 }
 309
 310 struct dirty_bit_map {
 311    uint32_t bit;
 312    char *name;
 313    uint32_t count;
 314 };
 315
 316 #define DEFINE_BIT(name) {name, #name, 0}
 317
 318 static struct dirty_bit_map mesa_bits[] = {
 319    DEFINE_BIT(_NEW_MODELVIEW),
 320    DEFINE_BIT(_NEW_PROJECTION),
 321    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 322    DEFINE_BIT(_NEW_COLOR),
 323    DEFINE_BIT(_NEW_DEPTH),
 324    DEFINE_BIT(_NEW_EVAL),
 325    DEFINE_BIT(_NEW_FOG),
 326    DEFINE_BIT(_NEW_HINT),
 327    DEFINE_BIT(_NEW_LIGHT),
 328    DEFINE_BIT(_NEW_LINE),
 329    DEFINE_BIT(_NEW_PIXEL),
 330    DEFINE_BIT(_NEW_POINT),
 331    DEFINE_BIT(_NEW_POLYGON),
 332    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 333    DEFINE_BIT(_NEW_SCISSOR),
 334    DEFINE_BIT(_NEW_STENCIL),
 335    DEFINE_BIT(_NEW_TEXTURE),
 336    DEFINE_BIT(_NEW_TRANSFORM),
 337    DEFINE_BIT(_NEW_VIEWPORT),
 338    DEFINE_BIT(_NEW_PACKUNPACK),
 339    DEFINE_BIT(_NEW_ARRAY),
 340    DEFINE_BIT(_NEW_RENDERMODE),
 341    DEFINE_BIT(_NEW_BUFFERS),
 342    DEFINE_BIT(_NEW_MULTISAMPLE),
 343    DEFINE_BIT(_NEW_TRACK_MATRIX),
 344    DEFINE_BIT(_NEW_PROGRAM),
 345    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 346    {0, 0, 0}
 347 };
 348
 349 static struct dirty_bit_map brw_bits[] = {
 350    DEFINE_BIT(BRW_NEW_URB_FENCE),
 351    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 352    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 353    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 354    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 355    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 356    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 357    DEFINE_BIT(BRW_NEW_CONTEXT),
 358    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 359    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 360    DEFINE_BIT(BRW_NEW_PSP),
 361    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 362    DEFINE_BIT(BRW_NEW_INDICES),
 363    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 364    DEFINE_BIT(BRW_NEW_VERTICES),
 365    DEFINE_BIT(BRW_NEW_BATCH),
 366    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 367    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 368    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 369    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 370    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 371    DEFINE_BIT(BRW_NEW_HIZ),
 372    {0, 0, 0}
 373 };
 374
 375 static struct dirty_bit_map cache_bits[] = {
 376    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 377    DEFINE_BIT(CACHE_NEW_CC_VP),
 378    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 379    DEFINE_BIT(CACHE_NEW_WM_PROG),
 380    DEFINE_BIT(CACHE_NEW_SAMPLER),
 381    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 382    DEFINE_BIT(CACHE_NEW_SF_PROG),
 383    DEFINE_BIT(CACHE_NEW_SF_VP),
 384    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 385    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 386    DEFINE_BIT(CACHE_NEW_VS_PROG),
 387    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 388    DEFINE_BIT(CACHE_NEW_GS_PROG),
 389    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 390    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 391    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 392    {0, 0, 0}
 393 };
 394
 395
 396 static void
 397 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 398 {
 399    int i;
 400
 401    for (i = 0; i < 32; i++) {
 402       if (bit_map[i].bit == 0)
 403          return;
 404
 405       if (bit_map[i].bit & bits)
 406          bit_map[i].count++;
 407    }
 408 }
 409
 410 static void
 411 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 412 {
 413    int i;
 414
 415    for (i = 0; i < 32; i++) {
 416       if (bit_map[i].bit == 0)
 417          return;
 418
 419       fprintf(stderr, "0x%08x: %12d (%s)\n",
 420               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 421    }
 422 }
 423
 424 /***********************************************************************
 425  * Emit all state:
 426  */
 427 void brw_upload_state(struct brw_context *brw)
 428 {
 429    struct gl_context *ctx = &brw->intel.ctx;
 430    struct intel_context *intel = &brw->intel;
 431    struct brw_state_flags *state = &brw->state.dirty;
 432    int i;
 433    static int dirty_count = 0;
 434
 435    state->mesa |= brw->intel.NewGLState;
 436    brw->intel.NewGLState = 0;
 437
 438    if (brw->emit_state_always) {
 439       state->mesa |= ~0;
 440       state->brw |= ~0;
 441       state->cache |= ~0;
 442    }
 443
 444    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 445       brw->fragment_program = ctx->FragmentProgram._Current;
 446       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 447    }
 448
 449    if (brw->vertex_program != ctx->VertexProgram._Current) {
 450       brw->vertex_program = ctx->VertexProgram._Current;
 451       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 452    }
 453
 454    if ((state->mesa | state->cache | state->brw) == 0)
 455       return;
 456
 457    brw->intel.Fallback = false; /* boolean, not bitfield */
 458
 459    intel_check_front_buffer_rendering(intel);
 460
 461    if (unlikely(INTEL_DEBUG)) {
 462       /* Debug version which enforces various sanity checks on the
 463        * state flags which are generated and checked to help ensure
 464        * state atoms are ordered correctly in the list.
 465        */
 466       struct brw_state_flags examined, prev;
 467       memset(&examined, 0, sizeof(examined));
 468       prev = *state;
 469
 470       for (i = 0; i < brw->num_atoms; i++) {
 471          const struct brw_tracked_state *atom = brw->atoms[i];
 472          struct brw_state_flags generated;
 473
 474          if (brw->intel.Fallback)
 475             break;
 476
 477          if (check_state(state, &atom->dirty)) {
 478             atom->emit(brw);
 479          }
 480
 481          accumulate_state(&examined, &atom->dirty);
 482
 483          /* generated = (prev ^ state)
 484           * if (examined & generated)
 485           *     fail;
 486           */
 487          xor_states(&generated, &prev, state);
 488          assert(!check_state(&examined, &generated));
 489          prev = *state;
 490       }
 491    }
 492    else {
 493       for (i = 0; i < brw->num_atoms; i++) {
 494          const struct brw_tracked_state *atom = brw->atoms[i];
 495
 496          if (brw->intel.Fallback)
 497             break;
 498
 499          if (check_state(state, &atom->dirty)) {
 500             atom->emit(brw);
 501          }
 502       }
 503    }
 504
 505    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 506       brw_update_dirty_count(mesa_bits, state->mesa);
 507       brw_update_dirty_count(brw_bits, state->brw);
 508       brw_update_dirty_count(cache_bits, state->cache);
 509       if (dirty_count++ % 1000 == 0) {
 510          brw_print_dirty_count(mesa_bits, state->mesa);
 511          brw_print_dirty_count(brw_bits, state->brw);
 512          brw_print_dirty_count(cache_bits, state->cache);
 513          fprintf(stderr, "\n");
 514       }
 515    }
 516
 517    if (!brw->intel.Fallback)
 518       memset(state, 0, sizeof(*state));
 519 }