src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_ff_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_wm_push_constants, /* Before wm_state */
 132
 133    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 134     * table upload must be last.
 135     */
 136    &brw_vs_pull_constants,
 137    &brw_vs_ubo_surfaces,
 138    &brw_wm_pull_constants,
 139    &brw_wm_ubo_surfaces,
 140    &gen6_renderbuffer_surfaces,
 141    &brw_texture_surfaces,
 142    &gen6_sol_surface,
 143    &brw_vs_binding_table,
 144    &gen6_gs_binding_table,
 145    &brw_wm_binding_table,
 146
 147    &brw_fs_samplers,
 148    &brw_vs_samplers,
 149    &gen6_sampler_state,
 150    &gen6_multisample_state,
 151
 152    &gen6_vs_state,
 153    &gen6_gs_state,
 154    &gen6_clip_state,
 155    &gen6_sf_state,
 156    &gen6_wm_state,
 157
 158    &gen6_scissor_state,
 159
 160    &gen6_binding_table_pointers,
 161
 162    &brw_depthbuffer,
 163
 164    &brw_polygon_stipple,
 165    &brw_polygon_stipple_offset,
 166
 167    &brw_line_stipple,
 168    &brw_aa_line_parameters,
 169
 170    &brw_drawing_rect,
 171
 172    &brw_indices,
 173    &brw_index_buffer,
 174    &brw_vertices,
 175 };
 176
 177 static const struct brw_tracked_state *gen7_atoms[] =
 178 {
 179    &brw_vs_prog,
 180    &brw_gs_prog,
 181    &brw_wm_prog,
 182
 183    /* Command packets: */
 184
 185    /* must do before binding table pointers, cc state ptrs */
 186    &brw_state_base_address,
 187
 188    &brw_cc_vp,
 189    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 190    &gen7_sf_clip_viewport,
 191
 192    &gen7_push_constant_space,
 193    &gen7_urb,
 194    &gen6_blend_state,           /* must do before cc unit */
 195    &gen6_color_calc_state,      /* must do before cc unit */
 196    &gen6_depth_stencil_state,   /* must do before cc unit */
 197
 198    &gen6_vs_push_constants, /* Before vs_state */
 199    &gen7_gs_push_constants, /* Before gs_state */
 200    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 201
 202    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 203     * table upload must be last.
 204     */
 205    &brw_vs_pull_constants,
 206    &brw_vs_ubo_surfaces,
 207    &brw_gs_pull_constants,
 208    &brw_gs_ubo_surfaces,
 209    &brw_wm_pull_constants,
 210    &brw_wm_ubo_surfaces,
 211    &gen6_renderbuffer_surfaces,
 212    &brw_texture_surfaces,
 213    &brw_vs_binding_table,
 214    &brw_gs_binding_table,
 215    &brw_wm_binding_table,
 216
 217    &brw_fs_samplers,
 218    &brw_vs_samplers,
 219    &brw_gs_samplers,
 220    &gen6_multisample_state,
 221
 222    &gen7_disable_stages,
 223    &gen7_vs_state,
 224    &gen7_gs_state,
 225    &gen7_sol_state,
 226    &gen7_clip_state,
 227    &gen7_sbe_state,
 228    &gen7_sf_state,
 229    &gen7_wm_state,
 230    &gen7_ps_state,
 231
 232    &gen6_scissor_state,
 233
 234    &gen7_depthbuffer,
 235
 236    &brw_polygon_stipple,
 237    &brw_polygon_stipple_offset,
 238
 239    &brw_line_stipple,
 240    &brw_aa_line_parameters,
 241
 242    &brw_drawing_rect,
 243
 244    &brw_indices,
 245    &brw_index_buffer,
 246    &brw_vertices,
 247
 248    &haswell_cut_index,
 249 };
 250
 251 static void
 252 brw_upload_initial_gpu_state(struct brw_context *brw)
 253 {
 254    /* On platforms with hardware contexts, we can set our initial GPU state
 255     * right away rather than doing it via state atoms.  This saves a small
 256     * amount of overhead on every draw call.
 257     */
 258    if (!brw->hw_ctx)
 259       return;
 260
 261    brw_upload_invariant_state(brw);
 262 }
 263
 264 void brw_init_state( struct brw_context *brw )
 265 {
 266    const struct brw_tracked_state **atoms;
 267    int num_atoms;
 268
 269    brw_init_caches(brw);
 270
 271    if (brw->gen >= 7) {
 272       atoms = gen7_atoms;
 273       num_atoms = ARRAY_SIZE(gen7_atoms);
 274    } else if (brw->gen == 6) {
 275       atoms = gen6_atoms;
 276       num_atoms = ARRAY_SIZE(gen6_atoms);
 277    } else {
 278       atoms = gen4_atoms;
 279       num_atoms = ARRAY_SIZE(gen4_atoms);
 280    }
 281
 282    brw->atoms = atoms;
 283    brw->num_atoms = num_atoms;
 284
 285    while (num_atoms--) {
 286       assert((*atoms)->dirty.mesa |
 287              (*atoms)->dirty.brw |
 288              (*atoms)->dirty.cache);
 289       assert((*atoms)->emit);
 290       atoms++;
 291    }
 292
 293    brw_upload_initial_gpu_state(brw);
 294 }
 295
 296
 297 void brw_destroy_state( struct brw_context *brw )
 298 {
 299    brw_destroy_caches(brw);
 300 }
 301
 302 /***********************************************************************
 303  */
 304
 305 static bool
 306 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 307 {
 308    return ((a->mesa & b->mesa) |
 309            (a->brw & b->brw) |
 310            (a->cache & b->cache)) != 0;
 311 }
 312
 313 static void accumulate_state( struct brw_state_flags *a,
 314                               const struct brw_state_flags *b )
 315 {
 316    a->mesa |= b->mesa;
 317    a->brw |= b->brw;
 318    a->cache |= b->cache;
 319 }
 320
 321
 322 static void xor_states( struct brw_state_flags *result,
 323                              const struct brw_state_flags *a,
 324                               const struct brw_state_flags *b )
 325 {
 326    result->mesa = a->mesa ^ b->mesa;
 327    result->brw = a->brw ^ b->brw;
 328    result->cache = a->cache ^ b->cache;
 329 }
 330
 331 struct dirty_bit_map {
 332    uint32_t bit;
 333    char *name;
 334    uint32_t count;
 335 };
 336
 337 #define DEFINE_BIT(name) {name, #name, 0}
 338
 339 static struct dirty_bit_map mesa_bits[] = {
 340    DEFINE_BIT(_NEW_MODELVIEW),
 341    DEFINE_BIT(_NEW_PROJECTION),
 342    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 343    DEFINE_BIT(_NEW_COLOR),
 344    DEFINE_BIT(_NEW_DEPTH),
 345    DEFINE_BIT(_NEW_EVAL),
 346    DEFINE_BIT(_NEW_FOG),
 347    DEFINE_BIT(_NEW_HINT),
 348    DEFINE_BIT(_NEW_LIGHT),
 349    DEFINE_BIT(_NEW_LINE),
 350    DEFINE_BIT(_NEW_PIXEL),
 351    DEFINE_BIT(_NEW_POINT),
 352    DEFINE_BIT(_NEW_POLYGON),
 353    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 354    DEFINE_BIT(_NEW_SCISSOR),
 355    DEFINE_BIT(_NEW_STENCIL),
 356    DEFINE_BIT(_NEW_TEXTURE),
 357    DEFINE_BIT(_NEW_TRANSFORM),
 358    DEFINE_BIT(_NEW_VIEWPORT),
 359    DEFINE_BIT(_NEW_ARRAY),
 360    DEFINE_BIT(_NEW_RENDERMODE),
 361    DEFINE_BIT(_NEW_BUFFERS),
 362    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 363    DEFINE_BIT(_NEW_MULTISAMPLE),
 364    DEFINE_BIT(_NEW_TRACK_MATRIX),
 365    DEFINE_BIT(_NEW_PROGRAM),
 366    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 367    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 368    DEFINE_BIT(_NEW_FRAG_CLAMP),
 369    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 370    {0, 0, 0}
 371 };
 372
 373 static struct dirty_bit_map brw_bits[] = {
 374    DEFINE_BIT(BRW_NEW_URB_FENCE),
 375    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 376    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 377    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 378    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 379    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 380    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 381    DEFINE_BIT(BRW_NEW_CONTEXT),
 382    DEFINE_BIT(BRW_NEW_PSP),
 383    DEFINE_BIT(BRW_NEW_SURFACES),
 384    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 385    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 386    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 387    DEFINE_BIT(BRW_NEW_INDICES),
 388    DEFINE_BIT(BRW_NEW_VERTICES),
 389    DEFINE_BIT(BRW_NEW_BATCH),
 390    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 391    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 392    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 393    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 394    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 395    DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
 396    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 397    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 398    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 399    DEFINE_BIT(BRW_NEW_STATS_WM),
 400    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 401    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 402    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 403    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 404    {0, 0, 0}
 405 };
 406
 407 static struct dirty_bit_map cache_bits[] = {
 408    DEFINE_BIT(CACHE_NEW_CC_VP),
 409    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 410    DEFINE_BIT(CACHE_NEW_WM_PROG),
 411    DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG),
 412    DEFINE_BIT(CACHE_NEW_BLORP_CONST_COLOR_PROG),
 413    DEFINE_BIT(CACHE_NEW_SAMPLER),
 414    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 415    DEFINE_BIT(CACHE_NEW_SF_PROG),
 416    DEFINE_BIT(CACHE_NEW_SF_VP),
 417    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 418    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 419    DEFINE_BIT(CACHE_NEW_VS_PROG),
 420    DEFINE_BIT(CACHE_NEW_FF_GS_UNIT),
 421    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 422    DEFINE_BIT(CACHE_NEW_GS_PROG),
 423    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 424    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 425    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 426    {0, 0, 0}
 427 };
 428
 429
 430 static void
 431 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 432 {
 433    int i;
 434
 435    for (i = 0; i < 32; i++) {
 436       if (bit_map[i].bit == 0)
 437          return;
 438
 439       if (bit_map[i].bit & bits)
 440          bit_map[i].count++;
 441    }
 442 }
 443
 444 static void
 445 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 446 {
 447    int i;
 448
 449    for (i = 0; i < 32; i++) {
 450       if (bit_map[i].bit == 0)
 451          return;
 452
 453       fprintf(stderr, "0x%08x: %12d (%s)\n",
 454               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 455    }
 456 }
 457
 458 /***********************************************************************
 459  * Emit all state:
 460  */
 461 void brw_upload_state(struct brw_context *brw)
 462 {
 463    struct gl_context *ctx = &brw->ctx;
 464    struct brw_state_flags *state = &brw->state.dirty;
 465    int i;
 466    static int dirty_count = 0;
 467
 468    state->mesa |= brw->NewGLState;
 469    brw->NewGLState = 0;
 470
 471    state->brw |= ctx->NewDriverState;
 472    ctx->NewDriverState = 0;
 473
 474    if (brw->emit_state_always) {
 475       state->mesa |= ~0;
 476       state->brw |= ~0;
 477       state->cache |= ~0;
 478    }
 479
 480    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 481       brw->fragment_program = ctx->FragmentProgram._Current;
 482       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 483    }
 484
 485    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 486       brw->geometry_program = ctx->GeometryProgram._Current;
 487       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 488    }
 489
 490    if (brw->vertex_program != ctx->VertexProgram._Current) {
 491       brw->vertex_program = ctx->VertexProgram._Current;
 492       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 493    }
 494
 495    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 496       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 497       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 498    }
 499
 500    if ((state->mesa | state->cache | state->brw) == 0)
 501       return;
 502
 503    intel_check_front_buffer_rendering(brw);
 504
 505    if (unlikely(INTEL_DEBUG)) {
 506       /* Debug version which enforces various sanity checks on the
 507        * state flags which are generated and checked to help ensure
 508        * state atoms are ordered correctly in the list.
 509        */
 510       struct brw_state_flags examined, prev;
 511       memset(&examined, 0, sizeof(examined));
 512       prev = *state;
 513
 514       for (i = 0; i < brw->num_atoms; i++) {
 515          const struct brw_tracked_state *atom = brw->atoms[i];
 516          struct brw_state_flags generated;
 517
 518          if (check_state(state, &atom->dirty)) {
 519             atom->emit(brw);
 520          }
 521
 522          accumulate_state(&examined, &atom->dirty);
 523
 524          /* generated = (prev ^ state)
 525           * if (examined & generated)
 526           *     fail;
 527           */
 528          xor_states(&generated, &prev, state);
 529          assert(!check_state(&examined, &generated));
 530          prev = *state;
 531       }
 532    }
 533    else {
 534       for (i = 0; i < brw->num_atoms; i++) {
 535          const struct brw_tracked_state *atom = brw->atoms[i];
 536
 537          if (check_state(state, &atom->dirty)) {
 538             atom->emit(brw);
 539          }
 540       }
 541    }
 542
 543    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 544       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 545       STATIC_ASSERT(ARRAY_SIZE(cache_bits) == BRW_MAX_CACHE + 1);
 546
 547       brw_update_dirty_count(mesa_bits, state->mesa);
 548       brw_update_dirty_count(brw_bits, state->brw);
 549       brw_update_dirty_count(cache_bits, state->cache);
 550       if (dirty_count++ % 1000 == 0) {
 551          brw_print_dirty_count(mesa_bits);
 552          brw_print_dirty_count(brw_bits);
 553          brw_print_dirty_count(cache_bits);
 554          fprintf(stderr, "\n");
 555       }
 556    }
 557
 558    memset(state, 0, sizeof(*state));
 559 }