2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "brw_context.h"
35 #include "brw_defines.h"
36 #include "brw_state.h"
37 #include "brw_program.h"
38 #include "drivers/common/meta.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_buffers.h"
42 #include "brw_ff_gs.h"
46 #include "genxml/genX_bits.h"
47 #include "main/framebuffer.h"
50 brw_enable_obj_preemption(struct brw_context
*brw
, bool enable
)
52 ASSERTED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
53 assert(devinfo
->gen
>= 9);
55 if (enable
== brw
->object_preemption
)
58 /* A fixed function pipe flush is required before modifying this field */
59 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
61 bool replay_mode
= enable
?
62 GEN9_REPLAY_MODE_MIDOBJECT
: GEN9_REPLAY_MODE_MIDBUFFER
;
64 /* enable object level preemption */
65 brw_load_register_imm32(brw
, CS_CHICKEN1
,
66 replay_mode
| GEN9_REPLAY_MODE_MASK
);
68 brw
->object_preemption
= enable
;
72 brw_upload_gen11_slice_hashing_state(struct brw_context
*brw
)
74 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
76 devinfo
->ppipe_subslices
[0] - devinfo
->ppipe_subslices
[1];
77 if (subslices_delta
== 0)
80 unsigned size
= GEN11_SLICE_HASH_TABLE_length
* 4;
81 uint32_t hash_address
;
83 uint32_t *map
= brw_state_batch(brw
, size
, 64, &hash_address
);
87 unsigned sl_small
= 0;
89 if (subslices_delta
> 0) {
95 * Create a 16x16 slice hashing table like the following one:
97 * [ 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 ]
98 * [ 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 ]
99 * [ 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 ]
100 * [ 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 ]
101 * [ 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 ]
102 * [ 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 ]
103 * [ 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 ]
104 * [ 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 ]
105 * [ 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 ]
106 * [ 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 ]
107 * [ 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 ]
108 * [ 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 ]
109 * [ 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 ]
110 * [ 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1 ]
111 * [ 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0 ]
112 * [ 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1 ]
114 * The table above is used when the pixel pipe 0 has less subslices than
115 * pixel pipe 1. When pixel pipe 0 has more subslices, then a similar table
116 * with 0's and 1's inverted is used.
118 for (int i
= 0; i
< GEN11_SLICE_HASH_TABLE_length
; i
++) {
121 for (int j
= 0; j
< 8; j
++) {
122 unsigned slice
= idx
++ % 3 ? sl_big
: sl_small
;
123 dw
|= slice
<< (j
* 4);
129 OUT_BATCH(_3DSTATE_SLICE_TABLE_STATE_POINTERS
<< 16 | (2 - 2));
130 OUT_RELOC(brw
->batch
.state
.bo
, 0, hash_address
| 1);
133 /* From gen10/gen11 workaround table in h/w specs:
135 * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
138 * This means that whenever we update a field with this instruction, we need
139 * to update all the others.
141 * Since this is the first time we emit this
142 * instruction, we are only setting the fSLICE_HASHING_TABLE_ENABLE flag,
143 * and leaving everything else at their default state (0).
146 OUT_BATCH(_3DSTATE_3D_MODE
<< 16 | (2 - 2));
147 OUT_BATCH(0xffff | SLICE_HASHING_TABLE_ENABLE
);
152 brw_upload_initial_gpu_state(struct brw_context
*brw
)
154 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
155 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
157 /* On platforms with hardware contexts, we can set our initial GPU state
158 * right away rather than doing it via state atoms. This saves a small
159 * amount of overhead on every draw call.
164 if (devinfo
->gen
== 6)
165 brw_emit_post_sync_nonzero_flush(brw
);
167 brw_upload_invariant_state(brw
);
169 if (devinfo
->gen
== 11) {
170 /* The default behavior of bit 5 "Headerless Message for Pre-emptable
171 * Contexts" in SAMPLER MODE register is set to 0, which means
172 * headerless sampler messages are not allowed for pre-emptable
173 * contexts. Set the bit 5 to 1 to allow them.
175 brw_load_register_imm32(brw
, GEN11_SAMPLER_MODE
,
176 HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK
|
177 HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS
);
179 /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
180 * HALF_SLICE_CHICKEN7 register.
182 brw_load_register_imm32(brw
, HALF_SLICE_CHICKEN7
,
183 TEXEL_OFFSET_FIX_MASK
|
184 TEXEL_OFFSET_FIX_ENABLE
);
186 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
187 * in L3CNTLREG register. The default setting of the bit is not the
188 * desirable behavior.
190 brw_load_register_imm32(brw
, GEN8_L3CNTLREG
,
191 GEN8_L3CNTLREG_EDBC_NO_HANG
);
193 /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM */
194 brw_load_register_imm32(brw
, COMMON_SLICE_CHICKEN4
,
195 GEN11_ENABLE_HARDWARE_FILTERING_IN_WM
|
196 REG_MASK(GEN11_ENABLE_HARDWARE_FILTERING_IN_WM
));
199 /* hardware specification recommends disabling repacking for
200 * the compatibility with decompression mechanism in display controller.
202 if (devinfo
->disable_ccs_repack
) {
203 brw_load_register_imm32(brw
, GEN7_CACHE_MODE_0
,
204 GEN11_DISABLE_REPACKING_FOR_COMPRESSION
|
205 REG_MASK(GEN11_DISABLE_REPACKING_FOR_COMPRESSION
));
208 if (devinfo
->gen
== 9) {
209 /* Recommended optimizations for Victim Cache eviction and floating
212 brw_load_register_imm32(brw
, GEN7_CACHE_MODE_1
,
213 REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
) |
214 REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
) |
215 GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
|
216 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
);
219 if (devinfo
->gen
>= 8) {
220 gen8_emit_3dstate_sample_pattern(brw
);
223 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
231 OUT_BATCH(_3DSTATE_WM_CHROMAKEY
<< 16 | (2 - 2));
236 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
237 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
239 * This is only safe on kernels with context isolation support.
241 if (!compiler
->constant_buffer_0_is_relative
) {
242 if (devinfo
->gen
>= 9) {
244 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
245 OUT_BATCH(CS_DEBUG_MODE2
);
246 OUT_BATCH(REG_MASK(CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
) |
247 CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
);
249 } else if (devinfo
->gen
== 8) {
251 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
253 OUT_BATCH(REG_MASK(INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
) |
254 INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
);
259 brw
->object_preemption
= false;
261 if (devinfo
->gen
>= 10)
262 brw_enable_obj_preemption(brw
, true);
264 if (devinfo
->gen
== 11)
265 brw_upload_gen11_slice_hashing_state(brw
);
268 static inline const struct brw_tracked_state
*
269 brw_get_pipeline_atoms(struct brw_context
*brw
,
270 enum brw_pipeline pipeline
)
273 case BRW_RENDER_PIPELINE
:
274 return brw
->render_atoms
;
275 case BRW_COMPUTE_PIPELINE
:
276 return brw
->compute_atoms
;
278 STATIC_ASSERT(BRW_NUM_PIPELINES
== 2);
279 unreachable("Unsupported pipeline");
285 brw_copy_pipeline_atoms(struct brw_context
*brw
,
286 enum brw_pipeline pipeline
,
287 const struct brw_tracked_state
**atoms
,
290 /* This is to work around brw_context::atoms being declared const. We want
291 * it to be const, but it needs to be initialized somehow!
293 struct brw_tracked_state
*context_atoms
=
294 (struct brw_tracked_state
*) brw_get_pipeline_atoms(brw
, pipeline
);
296 for (int i
= 0; i
< num_atoms
; i
++) {
297 context_atoms
[i
] = *atoms
[i
];
298 assert(context_atoms
[i
].dirty
.mesa
| context_atoms
[i
].dirty
.brw
);
299 assert(context_atoms
[i
].emit
);
302 brw
->num_atoms
[pipeline
] = num_atoms
;
305 void brw_init_state( struct brw_context
*brw
)
307 struct gl_context
*ctx
= &brw
->ctx
;
308 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
310 /* Force the first brw_select_pipeline to emit pipeline select */
311 brw
->last_pipeline
= BRW_NUM_PIPELINES
;
313 brw_init_caches(brw
);
315 if (devinfo
->gen
>= 11)
316 gen11_init_atoms(brw
);
317 else if (devinfo
->gen
>= 10)
318 gen10_init_atoms(brw
);
319 else if (devinfo
->gen
>= 9)
320 gen9_init_atoms(brw
);
321 else if (devinfo
->gen
>= 8)
322 gen8_init_atoms(brw
);
323 else if (devinfo
->is_haswell
)
324 gen75_init_atoms(brw
);
325 else if (devinfo
->gen
>= 7)
326 gen7_init_atoms(brw
);
327 else if (devinfo
->gen
>= 6)
328 gen6_init_atoms(brw
);
329 else if (devinfo
->gen
>= 5)
330 gen5_init_atoms(brw
);
331 else if (devinfo
->is_g4x
)
332 gen45_init_atoms(brw
);
334 gen4_init_atoms(brw
);
336 brw_upload_initial_gpu_state(brw
);
338 brw
->NewGLState
= ~0;
339 brw
->ctx
.NewDriverState
= ~0ull;
341 /* ~0 is a nonsensical value which won't match anything we program, so
342 * the programming will take effect on the first time around.
344 brw
->pma_stall_bits
= ~0;
346 /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
349 STATIC_ASSERT(BRW_NUM_STATE_BITS
<= 8 * sizeof(brw
->ctx
.NewDriverState
));
351 ctx
->DriverFlags
.NewTransformFeedback
= BRW_NEW_TRANSFORM_FEEDBACK
;
352 ctx
->DriverFlags
.NewTransformFeedbackProg
= BRW_NEW_TRANSFORM_FEEDBACK
;
353 ctx
->DriverFlags
.NewRasterizerDiscard
= BRW_NEW_RASTERIZER_DISCARD
;
354 ctx
->DriverFlags
.NewUniformBuffer
= BRW_NEW_UNIFORM_BUFFER
;
355 ctx
->DriverFlags
.NewShaderStorageBuffer
= BRW_NEW_UNIFORM_BUFFER
;
356 ctx
->DriverFlags
.NewTextureBuffer
= BRW_NEW_TEXTURE_BUFFER
;
357 ctx
->DriverFlags
.NewAtomicBuffer
= BRW_NEW_UNIFORM_BUFFER
;
358 ctx
->DriverFlags
.NewImageUnits
= BRW_NEW_IMAGE_UNITS
;
359 ctx
->DriverFlags
.NewDefaultTessLevels
= BRW_NEW_DEFAULT_TESS_LEVELS
;
360 ctx
->DriverFlags
.NewIntelConservativeRasterization
= BRW_NEW_CONSERVATIVE_RASTERIZATION
;
364 void brw_destroy_state( struct brw_context
*brw
)
366 brw_destroy_caches(brw
);
369 /***********************************************************************
373 check_state(const struct brw_state_flags
*a
, const struct brw_state_flags
*b
)
375 return ((a
->mesa
& b
->mesa
) | (a
->brw
& b
->brw
)) != 0;
378 static void accumulate_state( struct brw_state_flags
*a
,
379 const struct brw_state_flags
*b
)
386 static void xor_states( struct brw_state_flags
*result
,
387 const struct brw_state_flags
*a
,
388 const struct brw_state_flags
*b
)
390 result
->mesa
= a
->mesa
^ b
->mesa
;
391 result
->brw
= a
->brw
^ b
->brw
;
394 struct dirty_bit_map
{
400 #define DEFINE_BIT(name) {name, #name, 0}
402 static struct dirty_bit_map mesa_bits
[] = {
403 DEFINE_BIT(_NEW_MODELVIEW
),
404 DEFINE_BIT(_NEW_PROJECTION
),
405 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
406 DEFINE_BIT(_NEW_COLOR
),
407 DEFINE_BIT(_NEW_DEPTH
),
408 DEFINE_BIT(_NEW_EVAL
),
409 DEFINE_BIT(_NEW_FOG
),
410 DEFINE_BIT(_NEW_HINT
),
411 DEFINE_BIT(_NEW_LIGHT
),
412 DEFINE_BIT(_NEW_LINE
),
413 DEFINE_BIT(_NEW_PIXEL
),
414 DEFINE_BIT(_NEW_POINT
),
415 DEFINE_BIT(_NEW_POLYGON
),
416 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
417 DEFINE_BIT(_NEW_SCISSOR
),
418 DEFINE_BIT(_NEW_STENCIL
),
419 DEFINE_BIT(_NEW_TEXTURE_OBJECT
),
420 DEFINE_BIT(_NEW_TRANSFORM
),
421 DEFINE_BIT(_NEW_VIEWPORT
),
422 DEFINE_BIT(_NEW_TEXTURE_STATE
),
423 DEFINE_BIT(_NEW_RENDERMODE
),
424 DEFINE_BIT(_NEW_BUFFERS
),
425 DEFINE_BIT(_NEW_CURRENT_ATTRIB
),
426 DEFINE_BIT(_NEW_MULTISAMPLE
),
427 DEFINE_BIT(_NEW_TRACK_MATRIX
),
428 DEFINE_BIT(_NEW_PROGRAM
),
429 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
430 DEFINE_BIT(_NEW_FRAG_CLAMP
),
431 /* Avoid sign extension problems. */
432 {(unsigned) _NEW_VARYING_VP_INPUTS
, "_NEW_VARYING_VP_INPUTS", 0},
436 static struct dirty_bit_map brw_bits
[] = {
437 DEFINE_BIT(BRW_NEW_FS_PROG_DATA
),
438 DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA
),
439 DEFINE_BIT(BRW_NEW_SF_PROG_DATA
),
440 DEFINE_BIT(BRW_NEW_VS_PROG_DATA
),
441 DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA
),
442 DEFINE_BIT(BRW_NEW_GS_PROG_DATA
),
443 DEFINE_BIT(BRW_NEW_TCS_PROG_DATA
),
444 DEFINE_BIT(BRW_NEW_TES_PROG_DATA
),
445 DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA
),
446 DEFINE_BIT(BRW_NEW_CS_PROG_DATA
),
447 DEFINE_BIT(BRW_NEW_URB_FENCE
),
448 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
449 DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM
),
450 DEFINE_BIT(BRW_NEW_TESS_PROGRAMS
),
451 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
452 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
453 DEFINE_BIT(BRW_NEW_PATCH_PRIMITIVE
),
454 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
455 DEFINE_BIT(BRW_NEW_CONTEXT
),
456 DEFINE_BIT(BRW_NEW_PSP
),
457 DEFINE_BIT(BRW_NEW_SURFACES
),
458 DEFINE_BIT(BRW_NEW_BINDING_TABLE_POINTERS
),
459 DEFINE_BIT(BRW_NEW_INDICES
),
460 DEFINE_BIT(BRW_NEW_VERTICES
),
461 DEFINE_BIT(BRW_NEW_DEFAULT_TESS_LEVELS
),
462 DEFINE_BIT(BRW_NEW_BATCH
),
463 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
464 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
465 DEFINE_BIT(BRW_NEW_TCS_CONSTBUF
),
466 DEFINE_BIT(BRW_NEW_TES_CONSTBUF
),
467 DEFINE_BIT(BRW_NEW_GS_CONSTBUF
),
468 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
469 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
470 DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT
),
471 DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK
),
472 DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD
),
473 DEFINE_BIT(BRW_NEW_STATS_WM
),
474 DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER
),
475 DEFINE_BIT(BRW_NEW_IMAGE_UNITS
),
476 DEFINE_BIT(BRW_NEW_META_IN_PROGRESS
),
477 DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
478 DEFINE_BIT(BRW_NEW_NUM_SAMPLES
),
479 DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER
),
480 DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE
),
481 DEFINE_BIT(BRW_NEW_CC_VP
),
482 DEFINE_BIT(BRW_NEW_SF_VP
),
483 DEFINE_BIT(BRW_NEW_CLIP_VP
),
484 DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE
),
485 DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS
),
486 DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM
),
487 DEFINE_BIT(BRW_NEW_CS_WORK_GROUPS
),
488 DEFINE_BIT(BRW_NEW_URB_SIZE
),
489 DEFINE_BIT(BRW_NEW_CC_STATE
),
490 DEFINE_BIT(BRW_NEW_BLORP
),
491 DEFINE_BIT(BRW_NEW_VIEWPORT_COUNT
),
492 DEFINE_BIT(BRW_NEW_CONSERVATIVE_RASTERIZATION
),
493 DEFINE_BIT(BRW_NEW_DRAW_CALL
),
494 DEFINE_BIT(BRW_NEW_AUX_STATE
),
499 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, uint64_t bits
)
501 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
502 if (bit_map
[i
].bit
& bits
)
508 brw_print_dirty_count(struct dirty_bit_map
*bit_map
)
510 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
511 if (bit_map
[i
].count
> 1) {
512 fprintf(stderr
, "0x%016"PRIx64
": %12d (%s)\n",
513 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
519 brw_upload_tess_programs(struct brw_context
*brw
)
521 if (brw
->programs
[MESA_SHADER_TESS_EVAL
]) {
522 brw_upload_tcs_prog(brw
);
523 brw_upload_tes_prog(brw
);
525 brw
->tcs
.base
.prog_data
= NULL
;
526 brw
->tes
.base
.prog_data
= NULL
;
531 brw_upload_programs(struct brw_context
*brw
,
532 enum brw_pipeline pipeline
)
534 struct gl_context
*ctx
= &brw
->ctx
;
535 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
537 if (pipeline
== BRW_RENDER_PIPELINE
) {
538 brw_upload_vs_prog(brw
);
539 brw_upload_tess_programs(brw
);
541 if (brw
->programs
[MESA_SHADER_GEOMETRY
]) {
542 brw_upload_gs_prog(brw
);
544 brw
->gs
.base
.prog_data
= NULL
;
545 if (devinfo
->gen
< 7)
546 brw_upload_ff_gs_prog(brw
);
549 /* Update the VUE map for data exiting the GS stage of the pipeline.
550 * This comes from the last enabled shader stage.
552 GLbitfield64 old_slots
= brw
->vue_map_geom_out
.slots_valid
;
553 bool old_separate
= brw
->vue_map_geom_out
.separate
;
554 struct brw_vue_prog_data
*vue_prog_data
;
555 if (brw
->programs
[MESA_SHADER_GEOMETRY
])
556 vue_prog_data
= brw_vue_prog_data(brw
->gs
.base
.prog_data
);
557 else if (brw
->programs
[MESA_SHADER_TESS_EVAL
])
558 vue_prog_data
= brw_vue_prog_data(brw
->tes
.base
.prog_data
);
560 vue_prog_data
= brw_vue_prog_data(brw
->vs
.base
.prog_data
);
562 brw
->vue_map_geom_out
= vue_prog_data
->vue_map
;
564 /* If the layout has changed, signal BRW_NEW_VUE_MAP_GEOM_OUT. */
565 if (old_slots
!= brw
->vue_map_geom_out
.slots_valid
||
566 old_separate
!= brw
->vue_map_geom_out
.separate
)
567 brw
->ctx
.NewDriverState
|= BRW_NEW_VUE_MAP_GEOM_OUT
;
569 if ((old_slots
^ brw
->vue_map_geom_out
.slots_valid
) &
570 VARYING_BIT_VIEWPORT
) {
571 ctx
->NewDriverState
|= BRW_NEW_VIEWPORT_COUNT
;
572 brw
->clip
.viewport_count
=
573 (brw
->vue_map_geom_out
.slots_valid
& VARYING_BIT_VIEWPORT
) ?
574 ctx
->Const
.MaxViewports
: 1;
577 brw_upload_wm_prog(brw
);
579 if (devinfo
->gen
< 6) {
580 brw_upload_clip_prog(brw
);
581 brw_upload_sf_prog(brw
);
584 brw_disk_cache_write_render_programs(brw
);
585 } else if (pipeline
== BRW_COMPUTE_PIPELINE
) {
586 brw_upload_cs_prog(brw
);
587 brw_disk_cache_write_compute_program(brw
);
592 merge_ctx_state(struct brw_context
*brw
,
593 struct brw_state_flags
*state
)
595 state
->mesa
|= brw
->NewGLState
;
596 state
->brw
|= brw
->ctx
.NewDriverState
;
599 static ALWAYS_INLINE
void
600 check_and_emit_atom(struct brw_context
*brw
,
601 struct brw_state_flags
*state
,
602 const struct brw_tracked_state
*atom
)
604 if (check_state(state
, &atom
->dirty
)) {
606 merge_ctx_state(brw
, state
);
611 brw_upload_pipeline_state(struct brw_context
*brw
,
612 enum brw_pipeline pipeline
)
614 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
615 struct gl_context
*ctx
= &brw
->ctx
;
617 static int dirty_count
= 0;
618 struct brw_state_flags state
= brw
->state
.pipelines
[pipeline
];
619 const unsigned fb_samples
=
620 MAX2(_mesa_geometric_samples(ctx
->DrawBuffer
), 1);
622 brw_select_pipeline(brw
, pipeline
);
624 if (pipeline
== BRW_RENDER_PIPELINE
&& brw
->current_hash_scale
!= 1)
625 brw_emit_hashing_mode(brw
, UINT_MAX
, UINT_MAX
, 1);
627 if (unlikely(INTEL_DEBUG
& DEBUG_REEMIT
)) {
628 /* Always re-emit all state. */
629 brw
->NewGLState
= ~0;
630 ctx
->NewDriverState
= ~0ull;
633 if (pipeline
== BRW_RENDER_PIPELINE
) {
634 if (brw
->programs
[MESA_SHADER_FRAGMENT
] !=
635 ctx
->FragmentProgram
._Current
) {
636 brw
->programs
[MESA_SHADER_FRAGMENT
] = ctx
->FragmentProgram
._Current
;
637 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
640 if (brw
->programs
[MESA_SHADER_TESS_EVAL
] !=
641 ctx
->TessEvalProgram
._Current
) {
642 brw
->programs
[MESA_SHADER_TESS_EVAL
] = ctx
->TessEvalProgram
._Current
;
643 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
646 if (brw
->programs
[MESA_SHADER_TESS_CTRL
] !=
647 ctx
->TessCtrlProgram
._Current
) {
648 brw
->programs
[MESA_SHADER_TESS_CTRL
] = ctx
->TessCtrlProgram
._Current
;
649 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
652 if (brw
->programs
[MESA_SHADER_GEOMETRY
] !=
653 ctx
->GeometryProgram
._Current
) {
654 brw
->programs
[MESA_SHADER_GEOMETRY
] = ctx
->GeometryProgram
._Current
;
655 brw
->ctx
.NewDriverState
|= BRW_NEW_GEOMETRY_PROGRAM
;
658 if (brw
->programs
[MESA_SHADER_VERTEX
] != ctx
->VertexProgram
._Current
) {
659 brw
->programs
[MESA_SHADER_VERTEX
] = ctx
->VertexProgram
._Current
;
660 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
664 if (brw
->programs
[MESA_SHADER_COMPUTE
] != ctx
->ComputeProgram
._Current
) {
665 brw
->programs
[MESA_SHADER_COMPUTE
] = ctx
->ComputeProgram
._Current
;
666 brw
->ctx
.NewDriverState
|= BRW_NEW_COMPUTE_PROGRAM
;
669 if (brw
->meta_in_progress
!= _mesa_meta_in_progress(ctx
)) {
670 brw
->meta_in_progress
= _mesa_meta_in_progress(ctx
);
671 brw
->ctx
.NewDriverState
|= BRW_NEW_META_IN_PROGRESS
;
674 if (brw
->num_samples
!= fb_samples
) {
675 brw
->num_samples
= fb_samples
;
676 brw
->ctx
.NewDriverState
|= BRW_NEW_NUM_SAMPLES
;
679 /* Exit early if no state is flagged as dirty */
680 merge_ctx_state(brw
, &state
);
681 if ((state
.mesa
| state
.brw
) == 0)
684 /* Emit Sandybridge workaround flushes on every primitive, for safety. */
685 if (devinfo
->gen
== 6)
686 brw_emit_post_sync_nonzero_flush(brw
);
688 brw_upload_programs(brw
, pipeline
);
689 merge_ctx_state(brw
, &state
);
691 brw_upload_state_base_address(brw
);
693 const struct brw_tracked_state
*atoms
=
694 brw_get_pipeline_atoms(brw
, pipeline
);
695 const int num_atoms
= brw
->num_atoms
[pipeline
];
697 if (unlikely(INTEL_DEBUG
)) {
698 /* Debug version which enforces various sanity checks on the
699 * state flags which are generated and checked to help ensure
700 * state atoms are ordered correctly in the list.
702 struct brw_state_flags examined
, prev
;
703 memset(&examined
, 0, sizeof(examined
));
706 for (i
= 0; i
< num_atoms
; i
++) {
707 const struct brw_tracked_state
*atom
= &atoms
[i
];
708 struct brw_state_flags generated
;
710 check_and_emit_atom(brw
, &state
, atom
);
712 accumulate_state(&examined
, &atom
->dirty
);
714 /* generated = (prev ^ state)
715 * if (examined & generated)
718 xor_states(&generated
, &prev
, &state
);
719 assert(!check_state(&examined
, &generated
));
724 for (i
= 0; i
< num_atoms
; i
++) {
725 const struct brw_tracked_state
*atom
= &atoms
[i
];
727 check_and_emit_atom(brw
, &state
, atom
);
731 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
732 STATIC_ASSERT(ARRAY_SIZE(brw_bits
) == BRW_NUM_STATE_BITS
+ 1);
734 brw_update_dirty_count(mesa_bits
, state
.mesa
);
735 brw_update_dirty_count(brw_bits
, state
.brw
);
736 if (dirty_count
++ % 1000 == 0) {
737 brw_print_dirty_count(mesa_bits
);
738 brw_print_dirty_count(brw_bits
);
739 fprintf(stderr
, "\n");
744 /***********************************************************************
747 void brw_upload_render_state(struct brw_context
*brw
)
749 brw_upload_pipeline_state(brw
, BRW_RENDER_PIPELINE
);
753 brw_pipeline_state_finished(struct brw_context
*brw
,
754 enum brw_pipeline pipeline
)
756 /* Save all dirty state into the other pipelines */
757 for (unsigned i
= 0; i
< BRW_NUM_PIPELINES
; i
++) {
759 brw
->state
.pipelines
[i
].mesa
|= brw
->NewGLState
;
760 brw
->state
.pipelines
[i
].brw
|= brw
->ctx
.NewDriverState
;
762 memset(&brw
->state
.pipelines
[i
], 0, sizeof(struct brw_state_flags
));
767 brw
->ctx
.NewDriverState
= 0ull;
771 * Clear dirty bits to account for the fact that the state emitted by
772 * brw_upload_render_state() has been committed to the hardware. This is a
773 * separate call from brw_upload_render_state() because it's possible that
774 * after the call to brw_upload_render_state(), we will discover that we've
775 * run out of aperture space, and need to rewind the batch buffer to the state
776 * it had before the brw_upload_render_state() call.
779 brw_render_state_finished(struct brw_context
*brw
)
781 brw_pipeline_state_finished(brw
, BRW_RENDER_PIPELINE
);
785 brw_upload_compute_state(struct brw_context
*brw
)
787 brw_upload_pipeline_state(brw
, BRW_COMPUTE_PIPELINE
);
791 brw_compute_state_finished(struct brw_context
*brw
)
793 brw_pipeline_state_finished(brw
, BRW_COMPUTE_PIPELINE
);