src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_defines.h"
  36 #include "brw_state.h"
  37 #include "brw_program.h"
  38 #include "drivers/common/meta.h"
  39 #include "intel_batchbuffer.h"
  40 #include "intel_buffers.h"
  41 #include "brw_vs.h"
  42 #include "brw_ff_gs.h"
  43 #include "brw_gs.h"
  44 #include "brw_wm.h"
  45 #include "brw_cs.h"
  46 #include "main/framebuffer.h"
  47
  48 static void
  49 brw_upload_initial_gpu_state(struct brw_context *brw)
  50 {
  51    /* On platforms with hardware contexts, we can set our initial GPU state
  52     * right away rather than doing it via state atoms.  This saves a small
  53     * amount of overhead on every draw call.
  54     */
  55    if (!brw->hw_ctx)
  56       return;
  57
  58    if (brw->gen == 6)
  59       brw_emit_post_sync_nonzero_flush(brw);
  60
  61    brw_upload_invariant_state(brw);
  62
  63    if (brw->gen == 9) {
  64       /* Recommended optimizations for Victim Cache eviction and floating
  65        * point blending.
  66        */
  67       BEGIN_BATCH(3);
  68       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
  69       OUT_BATCH(GEN7_CACHE_MODE_1);
  70       OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
  71                 REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
  72                 GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
  73                 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
  74       ADVANCE_BATCH();
  75    }
  76
  77    if (brw->gen >= 8) {
  78       gen8_emit_3dstate_sample_pattern(brw);
  79
  80       BEGIN_BATCH(5);
  81       OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
  82       OUT_BATCH(0);
  83       OUT_BATCH(0);
  84       OUT_BATCH(0);
  85       OUT_BATCH(0);
  86       ADVANCE_BATCH();
  87
  88       BEGIN_BATCH(2);
  89       OUT_BATCH(_3DSTATE_WM_CHROMAKEY << 16 | (2 - 2));
  90       OUT_BATCH(0);
  91       ADVANCE_BATCH();
  92    }
  93
  94    /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
  95     * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
  96     *
  97     * On Gen6-7.5, we use an execbuf parameter to do this for us.
  98     * However, the kernel ignores that when execlists are in use.
  99     * Fortunately, we can just write the registers from userspace
 100     * on Gen8+, and they're context saved/restored.
 101     */
 102    if (brw->gen >= 9) {
 103       BEGIN_BATCH(3);
 104       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 105       OUT_BATCH(CS_DEBUG_MODE2);
 106       OUT_BATCH(REG_MASK(CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE) |
 107                 CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE);
 108       ADVANCE_BATCH();
 109    } else if (brw->gen == 8) {
 110       BEGIN_BATCH(3);
 111       OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 112       OUT_BATCH(INSTPM);
 113       OUT_BATCH(REG_MASK(INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE) |
 114                 INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE);
 115       ADVANCE_BATCH();
 116    }
 117 }
 118
 119 static inline const struct brw_tracked_state *
 120 brw_get_pipeline_atoms(struct brw_context *brw,
 121                        enum brw_pipeline pipeline)
 122 {
 123    switch (pipeline) {
 124    case BRW_RENDER_PIPELINE:
 125       return brw->render_atoms;
 126    case BRW_COMPUTE_PIPELINE:
 127       return brw->compute_atoms;
 128    default:
 129       STATIC_ASSERT(BRW_NUM_PIPELINES == 2);
 130       unreachable("Unsupported pipeline");
 131       return NULL;
 132    }
 133 }
 134
 135 void
 136 brw_copy_pipeline_atoms(struct brw_context *brw,
 137                         enum brw_pipeline pipeline,
 138                         const struct brw_tracked_state **atoms,
 139                         int num_atoms)
 140 {
 141    /* This is to work around brw_context::atoms being declared const.  We want
 142     * it to be const, but it needs to be initialized somehow!
 143     */
 144    struct brw_tracked_state *context_atoms =
 145       (struct brw_tracked_state *) brw_get_pipeline_atoms(brw, pipeline);
 146
 147    for (int i = 0; i < num_atoms; i++) {
 148       context_atoms[i] = *atoms[i];
 149       assert(context_atoms[i].dirty.mesa | context_atoms[i].dirty.brw);
 150       assert(context_atoms[i].emit);
 151    }
 152
 153    brw->num_atoms[pipeline] = num_atoms;
 154 }
 155
 156 void brw_init_state( struct brw_context *brw )
 157 {
 158    struct gl_context *ctx = &brw->ctx;
 159
 160    /* Force the first brw_select_pipeline to emit pipeline select */
 161    brw->last_pipeline = BRW_NUM_PIPELINES;
 162
 163    brw_init_caches(brw);
 164
 165    if (brw->gen >= 10)
 166       gen10_init_atoms(brw);
 167    else if (brw->gen >= 9)
 168       gen9_init_atoms(brw);
 169    else if (brw->gen >= 8)
 170       gen8_init_atoms(brw);
 171    else if (brw->is_haswell)
 172       gen75_init_atoms(brw);
 173    else if (brw->gen >= 7)
 174       gen7_init_atoms(brw);
 175    else if (brw->gen >= 6)
 176       gen6_init_atoms(brw);
 177    else if (brw->gen >= 5)
 178       gen5_init_atoms(brw);
 179    else if (brw->is_g4x)
 180       gen45_init_atoms(brw);
 181    else
 182       gen4_init_atoms(brw);
 183
 184    brw_upload_initial_gpu_state(brw);
 185
 186    brw->NewGLState = ~0;
 187    brw->ctx.NewDriverState = ~0ull;
 188
 189    /* ~0 is a nonsensical value which won't match anything we program, so
 190     * the programming will take effect on the first time around.
 191     */
 192    brw->pma_stall_bits = ~0;
 193
 194    /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
 195     * dirty flags.
 196     */
 197    STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->ctx.NewDriverState));
 198
 199    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 200    ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
 201    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 202    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 203    ctx->DriverFlags.NewShaderStorageBuffer = BRW_NEW_UNIFORM_BUFFER;
 204    ctx->DriverFlags.NewTextureBuffer = BRW_NEW_TEXTURE_BUFFER;
 205    ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 206    ctx->DriverFlags.NewImageUnits = BRW_NEW_IMAGE_UNITS;
 207    ctx->DriverFlags.NewDefaultTessLevels = BRW_NEW_DEFAULT_TESS_LEVELS;
 208    ctx->DriverFlags.NewIntelConservativeRasterization = BRW_NEW_CONSERVATIVE_RASTERIZATION;
 209 }
 210
 211
 212 void brw_destroy_state( struct brw_context *brw )
 213 {
 214    brw_destroy_caches(brw);
 215 }
 216
 217 /***********************************************************************
 218  */
 219
 220 static bool
 221 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 222 {
 223    return ((a->mesa & b->mesa) | (a->brw & b->brw)) != 0;
 224 }
 225
 226 static void accumulate_state( struct brw_state_flags *a,
 227                               const struct brw_state_flags *b )
 228 {
 229    a->mesa |= b->mesa;
 230    a->brw |= b->brw;
 231 }
 232
 233
 234 static void xor_states( struct brw_state_flags *result,
 235                              const struct brw_state_flags *a,
 236                               const struct brw_state_flags *b )
 237 {
 238    result->mesa = a->mesa ^ b->mesa;
 239    result->brw = a->brw ^ b->brw;
 240 }
 241
 242 struct dirty_bit_map {
 243    uint64_t bit;
 244    char *name;
 245    uint32_t count;
 246 };
 247
 248 #define DEFINE_BIT(name) {name, #name, 0}
 249
 250 static struct dirty_bit_map mesa_bits[] = {
 251    DEFINE_BIT(_NEW_MODELVIEW),
 252    DEFINE_BIT(_NEW_PROJECTION),
 253    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 254    DEFINE_BIT(_NEW_COLOR),
 255    DEFINE_BIT(_NEW_DEPTH),
 256    DEFINE_BIT(_NEW_EVAL),
 257    DEFINE_BIT(_NEW_FOG),
 258    DEFINE_BIT(_NEW_HINT),
 259    DEFINE_BIT(_NEW_LIGHT),
 260    DEFINE_BIT(_NEW_LINE),
 261    DEFINE_BIT(_NEW_PIXEL),
 262    DEFINE_BIT(_NEW_POINT),
 263    DEFINE_BIT(_NEW_POLYGON),
 264    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 265    DEFINE_BIT(_NEW_SCISSOR),
 266    DEFINE_BIT(_NEW_STENCIL),
 267    DEFINE_BIT(_NEW_TEXTURE_OBJECT),
 268    DEFINE_BIT(_NEW_TRANSFORM),
 269    DEFINE_BIT(_NEW_VIEWPORT),
 270    DEFINE_BIT(_NEW_TEXTURE_STATE),
 271    DEFINE_BIT(_NEW_ARRAY),
 272    DEFINE_BIT(_NEW_RENDERMODE),
 273    DEFINE_BIT(_NEW_BUFFERS),
 274    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 275    DEFINE_BIT(_NEW_MULTISAMPLE),
 276    DEFINE_BIT(_NEW_TRACK_MATRIX),
 277    DEFINE_BIT(_NEW_PROGRAM),
 278    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 279    DEFINE_BIT(_NEW_FRAG_CLAMP),
 280    /* Avoid sign extension problems. */
 281    {(unsigned) _NEW_VARYING_VP_INPUTS, "_NEW_VARYING_VP_INPUTS", 0},
 282    {0, 0, 0}
 283 };
 284
 285 static struct dirty_bit_map brw_bits[] = {
 286    DEFINE_BIT(BRW_NEW_FS_PROG_DATA),
 287    DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA),
 288    DEFINE_BIT(BRW_NEW_SF_PROG_DATA),
 289    DEFINE_BIT(BRW_NEW_VS_PROG_DATA),
 290    DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA),
 291    DEFINE_BIT(BRW_NEW_GS_PROG_DATA),
 292    DEFINE_BIT(BRW_NEW_TCS_PROG_DATA),
 293    DEFINE_BIT(BRW_NEW_TES_PROG_DATA),
 294    DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA),
 295    DEFINE_BIT(BRW_NEW_CS_PROG_DATA),
 296    DEFINE_BIT(BRW_NEW_URB_FENCE),
 297    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 298    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 299    DEFINE_BIT(BRW_NEW_TESS_PROGRAMS),
 300    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 301    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 302    DEFINE_BIT(BRW_NEW_PATCH_PRIMITIVE),
 303    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 304    DEFINE_BIT(BRW_NEW_CONTEXT),
 305    DEFINE_BIT(BRW_NEW_PSP),
 306    DEFINE_BIT(BRW_NEW_SURFACES),
 307    DEFINE_BIT(BRW_NEW_BINDING_TABLE_POINTERS),
 308    DEFINE_BIT(BRW_NEW_INDICES),
 309    DEFINE_BIT(BRW_NEW_VERTICES),
 310    DEFINE_BIT(BRW_NEW_DEFAULT_TESS_LEVELS),
 311    DEFINE_BIT(BRW_NEW_BATCH),
 312    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 313    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 314    DEFINE_BIT(BRW_NEW_TCS_CONSTBUF),
 315    DEFINE_BIT(BRW_NEW_TES_CONSTBUF),
 316    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 317    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 318    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 319    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 320    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 321    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 322    DEFINE_BIT(BRW_NEW_STATS_WM),
 323    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 324    DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
 325    DEFINE_BIT(BRW_NEW_IMAGE_UNITS),
 326    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 327    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 328    DEFINE_BIT(BRW_NEW_NUM_SAMPLES),
 329    DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER),
 330    DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE),
 331    DEFINE_BIT(BRW_NEW_CC_VP),
 332    DEFINE_BIT(BRW_NEW_SF_VP),
 333    DEFINE_BIT(BRW_NEW_CLIP_VP),
 334    DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE),
 335    DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS),
 336    DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM),
 337    DEFINE_BIT(BRW_NEW_CS_WORK_GROUPS),
 338    DEFINE_BIT(BRW_NEW_URB_SIZE),
 339    DEFINE_BIT(BRW_NEW_CC_STATE),
 340    DEFINE_BIT(BRW_NEW_BLORP),
 341    DEFINE_BIT(BRW_NEW_VIEWPORT_COUNT),
 342    DEFINE_BIT(BRW_NEW_CONSERVATIVE_RASTERIZATION),
 343    {0, 0, 0}
 344 };
 345
 346 static void
 347 brw_update_dirty_count(struct dirty_bit_map *bit_map, uint64_t bits)
 348 {
 349    for (int i = 0; bit_map[i].bit != 0; i++) {
 350       if (bit_map[i].bit & bits)
 351          bit_map[i].count++;
 352    }
 353 }
 354
 355 static void
 356 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 357 {
 358    for (int i = 0; bit_map[i].bit != 0; i++) {
 359       if (bit_map[i].count > 1) {
 360          fprintf(stderr, "0x%016"PRIx64": %12d (%s)\n",
 361                  bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 362       }
 363    }
 364 }
 365
 366 static inline void
 367 brw_upload_tess_programs(struct brw_context *brw)
 368 {
 369    if (brw->tess_eval_program) {
 370       brw_upload_tcs_prog(brw);
 371       brw_upload_tes_prog(brw);
 372    } else {
 373       brw->tcs.base.prog_data = NULL;
 374       brw->tes.base.prog_data = NULL;
 375    }
 376 }
 377
 378 static inline void
 379 brw_upload_programs(struct brw_context *brw,
 380                     enum brw_pipeline pipeline)
 381 {
 382    struct gl_context *ctx = &brw->ctx;
 383
 384    if (pipeline == BRW_RENDER_PIPELINE) {
 385       brw_upload_vs_prog(brw);
 386       brw_upload_tess_programs(brw);
 387
 388       if (brw->gen < 6)
 389          brw_upload_ff_gs_prog(brw);
 390       else
 391          brw_upload_gs_prog(brw);
 392
 393       /* Update the VUE map for data exiting the GS stage of the pipeline.
 394        * This comes from the last enabled shader stage.
 395        */
 396       GLbitfield64 old_slots = brw->vue_map_geom_out.slots_valid;
 397       bool old_separate = brw->vue_map_geom_out.separate;
 398       struct brw_vue_prog_data *vue_prog_data;
 399       if (brw->geometry_program)
 400          vue_prog_data = brw_vue_prog_data(brw->gs.base.prog_data);
 401       else if (brw->tess_eval_program)
 402          vue_prog_data = brw_vue_prog_data(brw->tes.base.prog_data);
 403       else
 404          vue_prog_data = brw_vue_prog_data(brw->vs.base.prog_data);
 405
 406       brw->vue_map_geom_out = vue_prog_data->vue_map;
 407
 408       /* If the layout has changed, signal BRW_NEW_VUE_MAP_GEOM_OUT. */
 409       if (old_slots != brw->vue_map_geom_out.slots_valid ||
 410           old_separate != brw->vue_map_geom_out.separate)
 411          brw->ctx.NewDriverState |= BRW_NEW_VUE_MAP_GEOM_OUT;
 412
 413       if ((old_slots ^ brw->vue_map_geom_out.slots_valid) &
 414           VARYING_BIT_VIEWPORT) {
 415          ctx->NewDriverState |= BRW_NEW_VIEWPORT_COUNT;
 416          brw->clip.viewport_count =
 417             (brw->vue_map_geom_out.slots_valid & VARYING_BIT_VIEWPORT) ?
 418             ctx->Const.MaxViewports : 1;
 419       }
 420
 421       brw_upload_wm_prog(brw);
 422
 423       if (brw->gen < 6) {
 424          brw_upload_clip_prog(brw);
 425          brw_upload_sf_prog(brw);
 426       }
 427    } else if (pipeline == BRW_COMPUTE_PIPELINE) {
 428       brw_upload_cs_prog(brw);
 429    }
 430 }
 431
 432 static inline void
 433 merge_ctx_state(struct brw_context *brw,
 434                 struct brw_state_flags *state)
 435 {
 436    state->mesa |= brw->NewGLState;
 437    state->brw |= brw->ctx.NewDriverState;
 438 }
 439
 440 static inline void
 441 check_and_emit_atom(struct brw_context *brw,
 442                     struct brw_state_flags *state,
 443                     const struct brw_tracked_state *atom)
 444 {
 445    if (check_state(state, &atom->dirty)) {
 446       atom->emit(brw);
 447       merge_ctx_state(brw, state);
 448    }
 449 }
 450
 451 static inline void
 452 brw_upload_pipeline_state(struct brw_context *brw,
 453                           enum brw_pipeline pipeline)
 454 {
 455    struct gl_context *ctx = &brw->ctx;
 456    int i;
 457    static int dirty_count = 0;
 458    struct brw_state_flags state = brw->state.pipelines[pipeline];
 459    unsigned int fb_samples = _mesa_geometric_samples(ctx->DrawBuffer);
 460
 461    brw_select_pipeline(brw, pipeline);
 462
 463    if (0) {
 464       /* Always re-emit all state. */
 465       brw->NewGLState = ~0;
 466       ctx->NewDriverState = ~0ull;
 467    }
 468
 469    if (pipeline == BRW_RENDER_PIPELINE) {
 470       if (brw->fragment_program != ctx->FragmentProgram._Current) {
 471          brw->fragment_program = ctx->FragmentProgram._Current;
 472          brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
 473       }
 474
 475       if (brw->tess_eval_program != ctx->TessEvalProgram._Current) {
 476          brw->tess_eval_program = ctx->TessEvalProgram._Current;
 477          brw->ctx.NewDriverState |= BRW_NEW_TESS_PROGRAMS;
 478       }
 479
 480       if (brw->tess_ctrl_program != ctx->TessCtrlProgram._Current) {
 481          brw->tess_ctrl_program = ctx->TessCtrlProgram._Current;
 482          brw->ctx.NewDriverState |= BRW_NEW_TESS_PROGRAMS;
 483       }
 484
 485       if (brw->geometry_program != ctx->GeometryProgram._Current) {
 486          brw->geometry_program = ctx->GeometryProgram._Current;
 487          brw->ctx.NewDriverState |= BRW_NEW_GEOMETRY_PROGRAM;
 488       }
 489
 490       if (brw->vertex_program != ctx->VertexProgram._Current) {
 491          brw->vertex_program = ctx->VertexProgram._Current;
 492          brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM;
 493       }
 494    }
 495
 496    if (brw->compute_program != ctx->ComputeProgram._Current) {
 497       brw->compute_program = ctx->ComputeProgram._Current;
 498       brw->ctx.NewDriverState |= BRW_NEW_COMPUTE_PROGRAM;
 499    }
 500
 501    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 502       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 503       brw->ctx.NewDriverState |= BRW_NEW_META_IN_PROGRESS;
 504    }
 505
 506    if (brw->num_samples != fb_samples) {
 507       brw->num_samples = fb_samples;
 508       brw->ctx.NewDriverState |= BRW_NEW_NUM_SAMPLES;
 509    }
 510
 511    /* Exit early if no state is flagged as dirty */
 512    merge_ctx_state(brw, &state);
 513    if ((state.mesa | state.brw) == 0)
 514       return;
 515
 516    /* Emit Sandybridge workaround flushes on every primitive, for safety. */
 517    if (brw->gen == 6)
 518       brw_emit_post_sync_nonzero_flush(brw);
 519
 520    brw_upload_programs(brw, pipeline);
 521    merge_ctx_state(brw, &state);
 522
 523    brw_upload_state_base_address(brw);
 524
 525    const struct brw_tracked_state *atoms =
 526       brw_get_pipeline_atoms(brw, pipeline);
 527    const int num_atoms = brw->num_atoms[pipeline];
 528
 529    if (unlikely(INTEL_DEBUG)) {
 530       /* Debug version which enforces various sanity checks on the
 531        * state flags which are generated and checked to help ensure
 532        * state atoms are ordered correctly in the list.
 533        */
 534       struct brw_state_flags examined, prev;
 535       memset(&examined, 0, sizeof(examined));
 536       prev = state;
 537
 538       for (i = 0; i < num_atoms; i++) {
 539          const struct brw_tracked_state *atom = &atoms[i];
 540          struct brw_state_flags generated;
 541
 542          check_and_emit_atom(brw, &state, atom);
 543
 544          accumulate_state(&examined, &atom->dirty);
 545
 546          /* generated = (prev ^ state)
 547           * if (examined & generated)
 548           *     fail;
 549           */
 550          xor_states(&generated, &prev, &state);
 551          assert(!check_state(&examined, &generated));
 552          prev = state;
 553       }
 554    }
 555    else {
 556       for (i = 0; i < num_atoms; i++) {
 557          const struct brw_tracked_state *atom = &atoms[i];
 558
 559          check_and_emit_atom(brw, &state, atom);
 560       }
 561    }
 562
 563    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 564       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 565
 566       brw_update_dirty_count(mesa_bits, state.mesa);
 567       brw_update_dirty_count(brw_bits, state.brw);
 568       if (dirty_count++ % 1000 == 0) {
 569          brw_print_dirty_count(mesa_bits);
 570          brw_print_dirty_count(brw_bits);
 571          fprintf(stderr, "\n");
 572       }
 573    }
 574 }
 575
 576 /***********************************************************************
 577  * Emit all state:
 578  */
 579 void brw_upload_render_state(struct brw_context *brw)
 580 {
 581    brw_upload_pipeline_state(brw, BRW_RENDER_PIPELINE);
 582 }
 583
 584 static inline void
 585 brw_pipeline_state_finished(struct brw_context *brw,
 586                             enum brw_pipeline pipeline)
 587 {
 588    /* Save all dirty state into the other pipelines */
 589    for (unsigned i = 0; i < BRW_NUM_PIPELINES; i++) {
 590       if (i != pipeline) {
 591          brw->state.pipelines[i].mesa |= brw->NewGLState;
 592          brw->state.pipelines[i].brw |= brw->ctx.NewDriverState;
 593       } else {
 594          memset(&brw->state.pipelines[i], 0, sizeof(struct brw_state_flags));
 595       }
 596    }
 597
 598    brw->NewGLState = 0;
 599    brw->ctx.NewDriverState = 0ull;
 600 }
 601
 602 /**
 603  * Clear dirty bits to account for the fact that the state emitted by
 604  * brw_upload_render_state() has been committed to the hardware. This is a
 605  * separate call from brw_upload_render_state() because it's possible that
 606  * after the call to brw_upload_render_state(), we will discover that we've
 607  * run out of aperture space, and need to rewind the batch buffer to the state
 608  * it had before the brw_upload_render_state() call.
 609  */
 610 void
 611 brw_render_state_finished(struct brw_context *brw)
 612 {
 613    brw_pipeline_state_finished(brw, BRW_RENDER_PIPELINE);
 614 }
 615
 616 void
 617 brw_upload_compute_state(struct brw_context *brw)
 618 {
 619    brw_upload_pipeline_state(brw, BRW_COMPUTE_PIPELINE);
 620 }
 621
 622 void
 623 brw_compute_state_finished(struct brw_context *brw)
 624 {
 625    brw_pipeline_state_finished(brw, BRW_COMPUTE_PIPELINE);
 626 }