src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_ff_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_wm_push_constants, /* Before wm_state */
 132
 133    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 134     * table upload must be last.
 135     */
 136    &brw_vs_pull_constants,
 137    &brw_vs_ubo_surfaces,
 138    &brw_wm_pull_constants,
 139    &brw_wm_ubo_surfaces,
 140    &gen6_renderbuffer_surfaces,
 141    &brw_texture_surfaces,
 142    &gen6_sol_surface,
 143    &brw_vs_binding_table,
 144    &gen6_gs_binding_table,
 145    &brw_wm_binding_table,
 146
 147    &brw_fs_samplers,
 148    &brw_vs_samplers,
 149    &gen6_sampler_state,
 150    &gen6_multisample_state,
 151
 152    &gen6_vs_state,
 153    &gen6_gs_state,
 154    &gen6_clip_state,
 155    &gen6_sf_state,
 156    &gen6_wm_state,
 157
 158    &gen6_scissor_state,
 159
 160    &gen6_binding_table_pointers,
 161
 162    &brw_depthbuffer,
 163
 164    &brw_polygon_stipple,
 165    &brw_polygon_stipple_offset,
 166
 167    &brw_line_stipple,
 168    &brw_aa_line_parameters,
 169
 170    &brw_drawing_rect,
 171
 172    &brw_indices,
 173    &brw_index_buffer,
 174    &brw_vertices,
 175 };
 176
 177 static const struct brw_tracked_state *gen7_atoms[] =
 178 {
 179    &brw_vs_prog,
 180    &brw_gs_prog,
 181    &brw_wm_prog,
 182
 183    /* Command packets: */
 184
 185    /* must do before binding table pointers, cc state ptrs */
 186    &brw_state_base_address,
 187
 188    &brw_cc_vp,
 189    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 190    &gen7_sf_clip_viewport,
 191
 192    &gen7_push_constant_space,
 193    &gen7_urb,
 194    &gen6_blend_state,           /* must do before cc unit */
 195    &gen6_color_calc_state,      /* must do before cc unit */
 196    &gen6_depth_stencil_state,   /* must do before cc unit */
 197
 198    &gen6_vs_push_constants, /* Before vs_state */
 199    &gen7_gs_push_constants, /* Before gs_state */
 200    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 201
 202    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 203     * table upload must be last.
 204     */
 205    &brw_vs_pull_constants,
 206    &brw_vs_ubo_surfaces,
 207    &brw_vs_abo_surfaces,
 208    &brw_gs_pull_constants,
 209    &brw_gs_ubo_surfaces,
 210    &brw_gs_abo_surfaces,
 211    &brw_wm_pull_constants,
 212    &brw_wm_ubo_surfaces,
 213    &brw_wm_abo_surfaces,
 214    &gen6_renderbuffer_surfaces,
 215    &brw_texture_surfaces,
 216    &brw_vs_binding_table,
 217    &brw_gs_binding_table,
 218    &brw_wm_binding_table,
 219
 220    &brw_fs_samplers,
 221    &brw_vs_samplers,
 222    &brw_gs_samplers,
 223    &gen6_multisample_state,
 224
 225    &gen7_disable_stages,
 226    &gen7_vs_state,
 227    &gen7_gs_state,
 228    &gen7_sol_state,
 229    &gen7_clip_state,
 230    &gen7_sbe_state,
 231    &gen7_sf_state,
 232    &gen7_wm_state,
 233    &gen7_ps_state,
 234
 235    &gen6_scissor_state,
 236
 237    &gen7_depthbuffer,
 238
 239    &brw_polygon_stipple,
 240    &brw_polygon_stipple_offset,
 241
 242    &brw_line_stipple,
 243    &brw_aa_line_parameters,
 244
 245    &brw_drawing_rect,
 246
 247    &brw_indices,
 248    &brw_index_buffer,
 249    &brw_vertices,
 250
 251    &haswell_cut_index,
 252 };
 253
 254 static const struct brw_tracked_state *gen8_atoms[] =
 255 {
 256    &brw_vs_prog,
 257    &brw_gs_prog,
 258    &brw_wm_prog,
 259
 260    /* Command packets: */
 261    &brw_state_base_address,
 262
 263    &brw_cc_vp,
 264    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 265    &gen7_sf_clip_viewport,
 266
 267    &gen7_push_constant_space,
 268    &gen7_urb,
 269    &gen6_blend_state,
 270    &gen6_color_calc_state,
 271
 272    &gen6_vs_push_constants, /* Before vs_state */
 273    &gen7_gs_push_constants, /* Before gs_state */
 274    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 275
 276    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 277     * table upload must be last.
 278     */
 279    &brw_vs_pull_constants,
 280    &brw_vs_ubo_surfaces,
 281    &brw_vs_abo_surfaces,
 282    &brw_gs_pull_constants,
 283    &brw_gs_ubo_surfaces,
 284    &brw_gs_abo_surfaces,
 285    &brw_wm_pull_constants,
 286    &brw_wm_ubo_surfaces,
 287    &brw_wm_abo_surfaces,
 288    &gen6_renderbuffer_surfaces,
 289    &brw_texture_surfaces,
 290    &brw_vs_binding_table,
 291    &brw_gs_binding_table,
 292    &brw_wm_binding_table,
 293
 294    &brw_fs_samplers,
 295    &brw_vs_samplers,
 296    &brw_gs_samplers,
 297    &gen6_multisample_state,
 298
 299    &gen7_disable_stages,
 300    &gen8_vs_state,
 301    &gen7_gs_state,
 302    &gen7_sol_state,
 303    &gen7_clip_state,
 304    &gen8_raster_state,
 305    &gen8_sbe_state,
 306    &gen8_sf_state,
 307    &gen8_ps_blend,
 308    &gen8_wm_depth_stencil,
 309    &gen7_wm_state,
 310    &gen7_ps_state,
 311
 312    &gen6_scissor_state,
 313
 314    &gen7_depthbuffer,
 315
 316    &brw_polygon_stipple,
 317    &brw_polygon_stipple_offset,
 318
 319    &brw_line_stipple,
 320    &brw_aa_line_parameters,
 321
 322    &brw_drawing_rect,
 323
 324    &brw_indices,
 325    &brw_index_buffer,
 326    &brw_vertices,
 327
 328    &haswell_cut_index,
 329 };
 330
 331 static void
 332 brw_upload_initial_gpu_state(struct brw_context *brw)
 333 {
 334    /* On platforms with hardware contexts, we can set our initial GPU state
 335     * right away rather than doing it via state atoms.  This saves a small
 336     * amount of overhead on every draw call.
 337     */
 338    if (!brw->hw_ctx)
 339       return;
 340
 341    brw_upload_invariant_state(brw);
 342 }
 343
 344 void brw_init_state( struct brw_context *brw )
 345 {
 346    struct gl_context *ctx = &brw->ctx;
 347    const struct brw_tracked_state **atoms;
 348    int num_atoms;
 349
 350    brw_init_caches(brw);
 351
 352    if (brw->gen >= 8) {
 353       atoms = gen8_atoms;
 354       num_atoms = ARRAY_SIZE(gen8_atoms);
 355    } else if (brw->gen == 7) {
 356       atoms = gen7_atoms;
 357       num_atoms = ARRAY_SIZE(gen7_atoms);
 358    } else if (brw->gen == 6) {
 359       atoms = gen6_atoms;
 360       num_atoms = ARRAY_SIZE(gen6_atoms);
 361    } else {
 362       atoms = gen4_atoms;
 363       num_atoms = ARRAY_SIZE(gen4_atoms);
 364    }
 365
 366    brw->atoms = atoms;
 367    brw->num_atoms = num_atoms;
 368
 369    while (num_atoms--) {
 370       assert((*atoms)->dirty.mesa |
 371              (*atoms)->dirty.brw |
 372              (*atoms)->dirty.cache);
 373       assert((*atoms)->emit);
 374       atoms++;
 375    }
 376
 377    brw_upload_initial_gpu_state(brw);
 378
 379    brw->state.dirty.mesa = ~0;
 380    brw->state.dirty.brw = ~0;
 381
 382    /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
 383     * dirty flags.
 384     */
 385    STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->state.dirty.brw));
 386
 387    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 388    ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
 389    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 390    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 391    ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 392 }
 393
 394
 395 void brw_destroy_state( struct brw_context *brw )
 396 {
 397    brw_destroy_caches(brw);
 398 }
 399
 400 /***********************************************************************
 401  */
 402
 403 static bool
 404 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 405 {
 406    return ((a->mesa & b->mesa) |
 407            (a->brw & b->brw) |
 408            (a->cache & b->cache)) != 0;
 409 }
 410
 411 static void accumulate_state( struct brw_state_flags *a,
 412                               const struct brw_state_flags *b )
 413 {
 414    a->mesa |= b->mesa;
 415    a->brw |= b->brw;
 416    a->cache |= b->cache;
 417 }
 418
 419
 420 static void xor_states( struct brw_state_flags *result,
 421                              const struct brw_state_flags *a,
 422                               const struct brw_state_flags *b )
 423 {
 424    result->mesa = a->mesa ^ b->mesa;
 425    result->brw = a->brw ^ b->brw;
 426    result->cache = a->cache ^ b->cache;
 427 }
 428
 429 struct dirty_bit_map {
 430    uint32_t bit;
 431    char *name;
 432    uint32_t count;
 433 };
 434
 435 #define DEFINE_BIT(name) {name, #name, 0}
 436
 437 static struct dirty_bit_map mesa_bits[] = {
 438    DEFINE_BIT(_NEW_MODELVIEW),
 439    DEFINE_BIT(_NEW_PROJECTION),
 440    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 441    DEFINE_BIT(_NEW_COLOR),
 442    DEFINE_BIT(_NEW_DEPTH),
 443    DEFINE_BIT(_NEW_EVAL),
 444    DEFINE_BIT(_NEW_FOG),
 445    DEFINE_BIT(_NEW_HINT),
 446    DEFINE_BIT(_NEW_LIGHT),
 447    DEFINE_BIT(_NEW_LINE),
 448    DEFINE_BIT(_NEW_PIXEL),
 449    DEFINE_BIT(_NEW_POINT),
 450    DEFINE_BIT(_NEW_POLYGON),
 451    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 452    DEFINE_BIT(_NEW_SCISSOR),
 453    DEFINE_BIT(_NEW_STENCIL),
 454    DEFINE_BIT(_NEW_TEXTURE),
 455    DEFINE_BIT(_NEW_TRANSFORM),
 456    DEFINE_BIT(_NEW_VIEWPORT),
 457    DEFINE_BIT(_NEW_ARRAY),
 458    DEFINE_BIT(_NEW_RENDERMODE),
 459    DEFINE_BIT(_NEW_BUFFERS),
 460    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 461    DEFINE_BIT(_NEW_MULTISAMPLE),
 462    DEFINE_BIT(_NEW_TRACK_MATRIX),
 463    DEFINE_BIT(_NEW_PROGRAM),
 464    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 465    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 466    DEFINE_BIT(_NEW_FRAG_CLAMP),
 467    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 468    {0, 0, 0}
 469 };
 470
 471 static struct dirty_bit_map brw_bits[] = {
 472    DEFINE_BIT(BRW_NEW_URB_FENCE),
 473    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 474    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 475    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 476    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 477    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 478    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 479    DEFINE_BIT(BRW_NEW_CONTEXT),
 480    DEFINE_BIT(BRW_NEW_PSP),
 481    DEFINE_BIT(BRW_NEW_SURFACES),
 482    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 483    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 484    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 485    DEFINE_BIT(BRW_NEW_INDICES),
 486    DEFINE_BIT(BRW_NEW_VERTICES),
 487    DEFINE_BIT(BRW_NEW_BATCH),
 488    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 489    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 490    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 491    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 492    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 493    DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
 494    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 495    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 496    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 497    DEFINE_BIT(BRW_NEW_STATS_WM),
 498    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 499    DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
 500    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 501    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 502    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 503    {0, 0, 0}
 504 };
 505
 506 static struct dirty_bit_map cache_bits[] = {
 507    DEFINE_BIT(CACHE_NEW_CC_VP),
 508    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 509    DEFINE_BIT(CACHE_NEW_WM_PROG),
 510    DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG),
 511    DEFINE_BIT(CACHE_NEW_BLORP_CONST_COLOR_PROG),
 512    DEFINE_BIT(CACHE_NEW_SAMPLER),
 513    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 514    DEFINE_BIT(CACHE_NEW_SF_PROG),
 515    DEFINE_BIT(CACHE_NEW_SF_VP),
 516    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 517    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 518    DEFINE_BIT(CACHE_NEW_VS_PROG),
 519    DEFINE_BIT(CACHE_NEW_FF_GS_UNIT),
 520    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 521    DEFINE_BIT(CACHE_NEW_GS_PROG),
 522    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 523    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 524    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 525    {0, 0, 0}
 526 };
 527
 528
 529 static void
 530 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 531 {
 532    int i;
 533
 534    for (i = 0; i < 32; i++) {
 535       if (bit_map[i].bit == 0)
 536          return;
 537
 538       if (bit_map[i].bit & bits)
 539          bit_map[i].count++;
 540    }
 541 }
 542
 543 static void
 544 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 545 {
 546    int i;
 547
 548    for (i = 0; i < 32; i++) {
 549       if (bit_map[i].bit == 0)
 550          return;
 551
 552       fprintf(stderr, "0x%08x: %12d (%s)\n",
 553               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 554    }
 555 }
 556
 557 /***********************************************************************
 558  * Emit all state:
 559  */
 560 void brw_upload_state(struct brw_context *brw)
 561 {
 562    struct gl_context *ctx = &brw->ctx;
 563    struct brw_state_flags *state = &brw->state.dirty;
 564    int i;
 565    static int dirty_count = 0;
 566
 567    state->mesa |= brw->NewGLState;
 568    brw->NewGLState = 0;
 569
 570    state->brw |= ctx->NewDriverState;
 571    ctx->NewDriverState = 0;
 572
 573    if (0) {
 574       /* Always re-emit all state. */
 575       state->mesa |= ~0;
 576       state->brw |= ~0;
 577       state->cache |= ~0;
 578    }
 579
 580    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 581       brw->fragment_program = ctx->FragmentProgram._Current;
 582       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 583    }
 584
 585    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 586       brw->geometry_program = ctx->GeometryProgram._Current;
 587       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 588    }
 589
 590    if (brw->vertex_program != ctx->VertexProgram._Current) {
 591       brw->vertex_program = ctx->VertexProgram._Current;
 592       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 593    }
 594
 595    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 596       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 597       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 598    }
 599
 600    if ((state->mesa | state->cache | state->brw) == 0)
 601       return;
 602
 603    intel_check_front_buffer_rendering(brw);
 604
 605    if (unlikely(INTEL_DEBUG)) {
 606       /* Debug version which enforces various sanity checks on the
 607        * state flags which are generated and checked to help ensure
 608        * state atoms are ordered correctly in the list.
 609        */
 610       struct brw_state_flags examined, prev;
 611       memset(&examined, 0, sizeof(examined));
 612       prev = *state;
 613
 614       for (i = 0; i < brw->num_atoms; i++) {
 615          const struct brw_tracked_state *atom = brw->atoms[i];
 616          struct brw_state_flags generated;
 617
 618          if (check_state(state, &atom->dirty)) {
 619             atom->emit(brw);
 620          }
 621
 622          accumulate_state(&examined, &atom->dirty);
 623
 624          /* generated = (prev ^ state)
 625           * if (examined & generated)
 626           *     fail;
 627           */
 628          xor_states(&generated, &prev, state);
 629          assert(!check_state(&examined, &generated));
 630          prev = *state;
 631       }
 632    }
 633    else {
 634       for (i = 0; i < brw->num_atoms; i++) {
 635          const struct brw_tracked_state *atom = brw->atoms[i];
 636
 637          if (check_state(state, &atom->dirty)) {
 638             atom->emit(brw);
 639          }
 640       }
 641    }
 642
 643    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 644       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 645       STATIC_ASSERT(ARRAY_SIZE(cache_bits) == BRW_MAX_CACHE + 1);
 646
 647       brw_update_dirty_count(mesa_bits, state->mesa);
 648       brw_update_dirty_count(brw_bits, state->brw);
 649       brw_update_dirty_count(cache_bits, state->cache);
 650       if (dirty_count++ % 1000 == 0) {
 651          brw_print_dirty_count(mesa_bits);
 652          brw_print_dirty_count(brw_bits);
 653          brw_print_dirty_count(cache_bits);
 654          fprintf(stderr, "\n");
 655       }
 656    }
 657 }
 658
 659
 660 /**
 661  * Clear dirty bits to account for the fact that the state emitted by
 662  * brw_upload_state() has been committed to the hardware.  This is a separate
 663  * call from brw_upload_state() because it's possible that after the call to
 664  * brw_upload_state(), we will discover that we've run out of aperture space,
 665  * and need to rewind the batch buffer to the state it had before the
 666  * brw_upload_state() call.
 667  */
 668 void
 669 brw_clear_dirty_bits(struct brw_context *brw)
 670 {
 671    struct brw_state_flags *state = &brw->state.dirty;
 672    memset(state, 0, sizeof(*state));
 673 }