src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    /* Must be before brw_binding_table */
  67    &brw_vs_pull_constants,
  68    &brw_wm_pull_constants,
  69
  70    &brw_renderbuffer_surfaces,  /* must do before unit */
  71    &brw_texture_surfaces,       /* must do before unit */
  72    &brw_binding_table,
  73    &brw_wm_samplers,
  74
  75    /* These set up state for brw_psp_urb_cbs */
  76    &brw_wm_unit,
  77    &brw_sf_vp,
  78    &brw_sf_unit,
  79    &brw_vs_unit,                /* always required, enabled or not */
  80    &brw_clip_unit,
  81    &brw_gs_unit,
  82
  83    /* Command packets:
  84     */
  85    &brw_invarient_state,
  86    &brw_state_base_address,
  87
  88    &brw_binding_table_pointers,
  89    &brw_blend_constant_color,
  90
  91    &brw_depthbuffer,
  92
  93    &brw_polygon_stipple,
  94    &brw_polygon_stipple_offset,
  95
  96    &brw_line_stipple,
  97    &brw_aa_line_parameters,
  98
  99    &brw_psp_urb_cbs,
 100
 101    &brw_drawing_rect,
 102    &brw_indices,
 103    &brw_index_buffer,
 104    &brw_vertices,
 105
 106    &brw_constant_buffer
 107 };
 108
 109 static const struct brw_tracked_state *gen6_atoms[] =
 110 {
 111    &brw_check_fallback,
 112
 113    &brw_wm_input_sizes,
 114    &brw_vs_prog, /* must do before state base address */
 115    &brw_gs_prog, /* must do before state base address */
 116    &brw_wm_prog, /* must do before state base address */
 117
 118    &gen6_clip_vp,
 119    &gen6_sf_vp,
 120
 121    /* Command packets: */
 122    &brw_invarient_state,
 123
 124    /* must do before binding table pointers, cc state ptrs */
 125    &brw_state_base_address,
 126
 127    &brw_cc_vp,
 128    &gen6_viewport_state,        /* must do after *_vp stages */
 129
 130    &gen6_urb,
 131    &gen6_blend_state,           /* must do before cc unit */
 132    &gen6_color_calc_state,      /* must do before cc unit */
 133    &gen6_depth_stencil_state,   /* must do before cc unit */
 134    &gen6_cc_state_pointers,
 135
 136    /* Pull constants must be before brw_binding_table */
 137    &brw_vs_pull_constants,
 138    &brw_wm_pull_constants,
 139
 140    &gen6_vs_push_constants, /* Before vs_state */
 141    &gen6_wm_push_constants, /* Before wm_state */
 142
 143    &brw_renderbuffer_surfaces,  /* must do before unit */
 144    &brw_texture_surfaces,       /* must do before unit */
 145    &brw_binding_table,
 146
 147    &brw_wm_samplers,
 148    &gen6_sampler_state,
 149
 150    &gen6_vs_state,
 151    &gen6_gs_state,
 152    &gen6_clip_state,
 153    &gen6_sf_state,
 154    &gen6_wm_state,
 155
 156    &gen6_scissor_state,
 157
 158    &gen6_binding_table_pointers,
 159
 160    &brw_depthbuffer,
 161
 162    &brw_polygon_stipple,
 163    &brw_polygon_stipple_offset,
 164
 165    &brw_line_stipple,
 166    &brw_aa_line_parameters,
 167
 168    &brw_drawing_rect,
 169
 170    &brw_indices,
 171    &brw_index_buffer,
 172    &brw_vertices,
 173 };
 174
 175 const struct brw_tracked_state *gen7_atoms[] =
 176 {
 177    &brw_check_fallback,
 178
 179    &brw_wm_input_sizes,
 180    &brw_vs_prog,
 181    &brw_gs_prog,
 182    &brw_wm_prog,
 183
 184    /* Command packets: */
 185    &brw_invarient_state,
 186
 187    /* must do before binding table pointers, cc state ptrs */
 188    &brw_state_base_address,
 189
 190    &brw_cc_vp,
 191    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 192    &gen7_sf_clip_viewport,
 193
 194    &gen7_urb,
 195    &gen6_blend_state,           /* must do before cc unit */
 196    &gen6_color_calc_state,      /* must do before cc unit */
 197    &gen6_depth_stencil_state,   /* must do before cc unit */
 198    &gen7_blend_state_pointer,
 199    &gen7_cc_state_pointer,
 200    &gen7_depth_stencil_state_pointer,
 201
 202    /* Pull constants must be before brw_binding_table */
 203    &brw_vs_pull_constants,
 204    &brw_wm_pull_constants,
 205
 206    &gen6_vs_push_constants, /* Before vs_state */
 207    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 208
 209    &brw_renderbuffer_surfaces,  /* must do before unit */
 210    &brw_texture_surfaces,       /* must do before unit */
 211    &brw_binding_table,
 212
 213    &gen7_samplers,
 214
 215    &gen7_disable_stages,
 216    &gen7_vs_state,
 217    &gen7_clip_state,
 218    &gen7_sbe_state,
 219    &gen7_sf_state,
 220    &gen7_wm_state,
 221    &gen7_ps_state,
 222
 223    &gen6_scissor_state,
 224
 225    &gen7_depthbuffer,
 226
 227    &brw_polygon_stipple,
 228    &brw_polygon_stipple_offset,
 229
 230    &brw_line_stipple,
 231    &brw_aa_line_parameters,
 232
 233    &brw_drawing_rect,
 234
 235    &brw_indices,
 236    &brw_index_buffer,
 237    &brw_vertices,
 238 };
 239
 240
 241 void brw_init_state( struct brw_context *brw )
 242 {
 243    const struct brw_tracked_state **atoms;
 244    int num_atoms;
 245
 246    brw_init_caches(brw);
 247
 248    if (brw->intel.gen >= 7) {
 249       atoms = gen7_atoms;
 250       num_atoms = ARRAY_SIZE(gen7_atoms);
 251    } else if (brw->intel.gen == 6) {
 252       atoms = gen6_atoms;
 253       num_atoms = ARRAY_SIZE(gen6_atoms);
 254    } else {
 255       atoms = gen4_atoms;
 256       num_atoms = ARRAY_SIZE(gen4_atoms);
 257    }
 258
 259    brw->atoms = atoms;
 260    brw->num_atoms = num_atoms;
 261
 262    while (num_atoms--) {
 263       assert((*atoms)->dirty.mesa |
 264              (*atoms)->dirty.brw |
 265              (*atoms)->dirty.cache);
 266       assert((*atoms)->emit);
 267       atoms++;
 268    }
 269 }
 270
 271
 272 void brw_destroy_state( struct brw_context *brw )
 273 {
 274    brw_destroy_caches(brw);
 275 }
 276
 277 /***********************************************************************
 278  */
 279
 280 static GLuint check_state( const struct brw_state_flags *a,
 281                            const struct brw_state_flags *b )
 282 {
 283    return ((a->mesa & b->mesa) |
 284            (a->brw & b->brw) |
 285            (a->cache & b->cache)) != 0;
 286 }
 287
 288 static void accumulate_state( struct brw_state_flags *a,
 289                               const struct brw_state_flags *b )
 290 {
 291    a->mesa |= b->mesa;
 292    a->brw |= b->brw;
 293    a->cache |= b->cache;
 294 }
 295
 296
 297 static void xor_states( struct brw_state_flags *result,
 298                              const struct brw_state_flags *a,
 299                               const struct brw_state_flags *b )
 300 {
 301    result->mesa = a->mesa ^ b->mesa;
 302    result->brw = a->brw ^ b->brw;
 303    result->cache = a->cache ^ b->cache;
 304 }
 305
 306 struct dirty_bit_map {
 307    uint32_t bit;
 308    char *name;
 309    uint32_t count;
 310 };
 311
 312 #define DEFINE_BIT(name) {name, #name, 0}
 313
 314 static struct dirty_bit_map mesa_bits[] = {
 315    DEFINE_BIT(_NEW_MODELVIEW),
 316    DEFINE_BIT(_NEW_PROJECTION),
 317    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 318    DEFINE_BIT(_NEW_COLOR),
 319    DEFINE_BIT(_NEW_DEPTH),
 320    DEFINE_BIT(_NEW_EVAL),
 321    DEFINE_BIT(_NEW_FOG),
 322    DEFINE_BIT(_NEW_HINT),
 323    DEFINE_BIT(_NEW_LIGHT),
 324    DEFINE_BIT(_NEW_LINE),
 325    DEFINE_BIT(_NEW_PIXEL),
 326    DEFINE_BIT(_NEW_POINT),
 327    DEFINE_BIT(_NEW_POLYGON),
 328    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 329    DEFINE_BIT(_NEW_SCISSOR),
 330    DEFINE_BIT(_NEW_STENCIL),
 331    DEFINE_BIT(_NEW_TEXTURE),
 332    DEFINE_BIT(_NEW_TRANSFORM),
 333    DEFINE_BIT(_NEW_VIEWPORT),
 334    DEFINE_BIT(_NEW_PACKUNPACK),
 335    DEFINE_BIT(_NEW_ARRAY),
 336    DEFINE_BIT(_NEW_RENDERMODE),
 337    DEFINE_BIT(_NEW_BUFFERS),
 338    DEFINE_BIT(_NEW_MULTISAMPLE),
 339    DEFINE_BIT(_NEW_TRACK_MATRIX),
 340    DEFINE_BIT(_NEW_PROGRAM),
 341    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 342    {0, 0, 0}
 343 };
 344
 345 static struct dirty_bit_map brw_bits[] = {
 346    DEFINE_BIT(BRW_NEW_URB_FENCE),
 347    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 348    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 349    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 350    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 351    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 352    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 353    DEFINE_BIT(BRW_NEW_CONTEXT),
 354    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 355    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 356    DEFINE_BIT(BRW_NEW_PSP),
 357    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 358    DEFINE_BIT(BRW_NEW_INDICES),
 359    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 360    DEFINE_BIT(BRW_NEW_VERTICES),
 361    DEFINE_BIT(BRW_NEW_BATCH),
 362    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 363    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 364    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 365    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 366    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 367    {0, 0, 0}
 368 };
 369
 370 static struct dirty_bit_map cache_bits[] = {
 371    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 372    DEFINE_BIT(CACHE_NEW_CC_VP),
 373    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 374    DEFINE_BIT(CACHE_NEW_WM_PROG),
 375    DEFINE_BIT(CACHE_NEW_SAMPLER),
 376    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 377    DEFINE_BIT(CACHE_NEW_SF_PROG),
 378    DEFINE_BIT(CACHE_NEW_SF_VP),
 379    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 380    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 381    DEFINE_BIT(CACHE_NEW_VS_PROG),
 382    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 383    DEFINE_BIT(CACHE_NEW_GS_PROG),
 384    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 385    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 386    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 387    {0, 0, 0}
 388 };
 389
 390
 391 static void
 392 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 393 {
 394    int i;
 395
 396    for (i = 0; i < 32; i++) {
 397       if (bit_map[i].bit == 0)
 398          return;
 399
 400       if (bit_map[i].bit & bits)
 401          bit_map[i].count++;
 402    }
 403 }
 404
 405 static void
 406 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 407 {
 408    int i;
 409
 410    for (i = 0; i < 32; i++) {
 411       if (bit_map[i].bit == 0)
 412          return;
 413
 414       fprintf(stderr, "0x%08x: %12d (%s)\n",
 415               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 416    }
 417 }
 418
 419 /***********************************************************************
 420  * Emit all state:
 421  */
 422 void brw_upload_state(struct brw_context *brw)
 423 {
 424    struct gl_context *ctx = &brw->intel.ctx;
 425    struct intel_context *intel = &brw->intel;
 426    struct brw_state_flags *state = &brw->state.dirty;
 427    int i;
 428    static int dirty_count = 0;
 429
 430    state->mesa |= brw->intel.NewGLState;
 431    brw->intel.NewGLState = 0;
 432
 433    if (brw->emit_state_always) {
 434       state->mesa |= ~0;
 435       state->brw |= ~0;
 436       state->cache |= ~0;
 437    }
 438
 439    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 440       brw->fragment_program = ctx->FragmentProgram._Current;
 441       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 442    }
 443
 444    if (brw->vertex_program != ctx->VertexProgram._Current) {
 445       brw->vertex_program = ctx->VertexProgram._Current;
 446       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 447    }
 448
 449    if ((state->mesa | state->cache | state->brw) == 0)
 450       return;
 451
 452    brw->intel.Fallback = false; /* boolean, not bitfield */
 453
 454    intel_check_front_buffer_rendering(intel);
 455
 456    if (unlikely(INTEL_DEBUG)) {
 457       /* Debug version which enforces various sanity checks on the
 458        * state flags which are generated and checked to help ensure
 459        * state atoms are ordered correctly in the list.
 460        */
 461       struct brw_state_flags examined, prev;
 462       memset(&examined, 0, sizeof(examined));
 463       prev = *state;
 464
 465       for (i = 0; i < brw->num_atoms; i++) {
 466          const struct brw_tracked_state *atom = brw->atoms[i];
 467          struct brw_state_flags generated;
 468
 469          if (brw->intel.Fallback)
 470             break;
 471
 472          if (check_state(state, &atom->dirty)) {
 473             atom->emit(brw);
 474          }
 475
 476          accumulate_state(&examined, &atom->dirty);
 477
 478          /* generated = (prev ^ state)
 479           * if (examined & generated)
 480           *     fail;
 481           */
 482          xor_states(&generated, &prev, state);
 483          assert(!check_state(&examined, &generated));
 484          prev = *state;
 485       }
 486    }
 487    else {
 488       for (i = 0; i < brw->num_atoms; i++) {
 489          const struct brw_tracked_state *atom = brw->atoms[i];
 490
 491          if (brw->intel.Fallback)
 492             break;
 493
 494          if (check_state(state, &atom->dirty)) {
 495             atom->emit(brw);
 496          }
 497       }
 498    }
 499
 500    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 501       brw_update_dirty_count(mesa_bits, state->mesa);
 502       brw_update_dirty_count(brw_bits, state->brw);
 503       brw_update_dirty_count(cache_bits, state->cache);
 504       if (dirty_count++ % 1000 == 0) {
 505          brw_print_dirty_count(mesa_bits, state->mesa);
 506          brw_print_dirty_count(brw_bits, state->brw);
 507          brw_print_dirty_count(cache_bits, state->cache);
 508          fprintf(stderr, "\n");
 509       }
 510    }
 511
 512    if (!brw->intel.Fallback)
 513       memset(state, 0, sizeof(*state));
 514 }