src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38 #include "intel_chipset.h"
  39
  40 /* This is used to initialize brw->state.atoms[].  We could use this
  41  * list directly except for a single atom, brw_constant_buffer, which
  42  * has a .dirty value which changes according to the parameters of the
  43  * current fragment and vertex programs, and so cannot be a static
  44  * value.
  45  */
  46 static const struct brw_tracked_state *gen4_atoms[] =
  47 {
  48    &brw_check_fallback,
  49
  50    &brw_wm_input_sizes,
  51    &brw_vs_prog,
  52    &brw_gs_prog,
  53    &brw_clip_prog,
  54    &brw_sf_prog,
  55    &brw_wm_prog,
  56
  57    /* Once all the programs are done, we know how large urb entry
  58     * sizes need to be and can decide if we need to change the urb
  59     * layout.
  60     */
  61    &brw_curbe_offsets,
  62    &brw_recalculate_urb_fence,
  63
  64    &brw_cc_unit,
  65
  66    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
  67    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
  68
  69    &brw_vs_surfaces,            /* must do before unit */
  70    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  71    &brw_wm_surfaces,            /* must do before samplers and unit */
  72    &brw_wm_binding_table,
  73    &brw_wm_samplers,
  74
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invarient_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_check_fallback,
 111
 112    &brw_wm_input_sizes,
 113    &brw_vs_prog,
 114    &brw_gs_prog,
 115    &brw_wm_prog,
 116
 117    &gen6_clip_vp,
 118    &gen6_sf_vp,
 119    &gen6_cc_vp,
 120
 121    /* Command packets: */
 122    &brw_invarient_state,
 123
 124    &gen6_viewport_state,        /* must do after *_vp stages */
 125
 126    &gen6_urb,
 127    &gen6_blend_state,           /* must do before cc unit */
 128    &gen6_color_calc_state,      /* must do before cc unit */
 129    &gen6_depth_stencil_state,   /* must do before cc unit */
 130    &gen6_cc_state_pointers,
 131
 132    &brw_vs_surfaces,            /* must do before unit */
 133    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 134    &brw_wm_surfaces,            /* must do before samplers and unit */
 135
 136    &brw_wm_samplers,
 137    &gen6_sampler_state,
 138
 139    &gen6_vs_state,
 140    &gen6_gs_state,
 141    &gen6_clip_state,
 142    &gen6_sf_state,
 143    &gen6_wm_state,
 144
 145    &gen6_scissor_state,
 146
 147    &brw_state_base_address,
 148
 149    &gen6_binding_table_pointers,
 150
 151    &brw_depthbuffer,
 152
 153    &brw_polygon_stipple,
 154    &brw_polygon_stipple_offset,
 155
 156    &brw_line_stipple,
 157    &brw_aa_line_parameters,
 158
 159    &brw_drawing_rect,
 160
 161    &brw_indices,
 162    &brw_index_buffer,
 163    &brw_vertices,
 164 };
 165
 166 void brw_init_state( struct brw_context *brw )
 167 {
 168    brw_init_caches(brw);
 169 }
 170
 171
 172 void brw_destroy_state( struct brw_context *brw )
 173 {
 174    brw_destroy_caches(brw);
 175    brw_destroy_batch_cache(brw);
 176 }
 177
 178 /***********************************************************************
 179  */
 180
 181 static GLboolean check_state( const struct brw_state_flags *a,
 182                               const struct brw_state_flags *b )
 183 {
 184    return ((a->mesa & b->mesa) ||
 185            (a->brw & b->brw) ||
 186            (a->cache & b->cache));
 187 }
 188
 189 static void accumulate_state( struct brw_state_flags *a,
 190                               const struct brw_state_flags *b )
 191 {
 192    a->mesa |= b->mesa;
 193    a->brw |= b->brw;
 194    a->cache |= b->cache;
 195 }
 196
 197
 198 static void xor_states( struct brw_state_flags *result,
 199                              const struct brw_state_flags *a,
 200                               const struct brw_state_flags *b )
 201 {
 202    result->mesa = a->mesa ^ b->mesa;
 203    result->brw = a->brw ^ b->brw;
 204    result->cache = a->cache ^ b->cache;
 205 }
 206
 207 void
 208 brw_clear_validated_bos(struct brw_context *brw)
 209 {
 210    int i;
 211
 212    /* Clear the last round of validated bos */
 213    for (i = 0; i < brw->state.validated_bo_count; i++) {
 214       drm_intel_bo_unreference(brw->state.validated_bos[i]);
 215       brw->state.validated_bos[i] = NULL;
 216    }
 217    brw->state.validated_bo_count = 0;
 218 }
 219
 220 struct dirty_bit_map {
 221    uint32_t bit;
 222    char *name;
 223    uint32_t count;
 224 };
 225
 226 #define DEFINE_BIT(name) {name, #name, 0}
 227
 228 static struct dirty_bit_map mesa_bits[] = {
 229    DEFINE_BIT(_NEW_MODELVIEW),
 230    DEFINE_BIT(_NEW_PROJECTION),
 231    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 232    DEFINE_BIT(_NEW_COLOR_MATRIX),
 233    DEFINE_BIT(_NEW_ACCUM),
 234    DEFINE_BIT(_NEW_COLOR),
 235    DEFINE_BIT(_NEW_DEPTH),
 236    DEFINE_BIT(_NEW_EVAL),
 237    DEFINE_BIT(_NEW_FOG),
 238    DEFINE_BIT(_NEW_HINT),
 239    DEFINE_BIT(_NEW_LIGHT),
 240    DEFINE_BIT(_NEW_LINE),
 241    DEFINE_BIT(_NEW_PIXEL),
 242    DEFINE_BIT(_NEW_POINT),
 243    DEFINE_BIT(_NEW_POLYGON),
 244    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 245    DEFINE_BIT(_NEW_SCISSOR),
 246    DEFINE_BIT(_NEW_STENCIL),
 247    DEFINE_BIT(_NEW_TEXTURE),
 248    DEFINE_BIT(_NEW_TRANSFORM),
 249    DEFINE_BIT(_NEW_VIEWPORT),
 250    DEFINE_BIT(_NEW_PACKUNPACK),
 251    DEFINE_BIT(_NEW_ARRAY),
 252    DEFINE_BIT(_NEW_RENDERMODE),
 253    DEFINE_BIT(_NEW_BUFFERS),
 254    DEFINE_BIT(_NEW_MULTISAMPLE),
 255    DEFINE_BIT(_NEW_TRACK_MATRIX),
 256    DEFINE_BIT(_NEW_PROGRAM),
 257    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 258    {0, 0, 0}
 259 };
 260
 261 static struct dirty_bit_map brw_bits[] = {
 262    DEFINE_BIT(BRW_NEW_URB_FENCE),
 263    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 264    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 265    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 266    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 267    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 268    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 269    DEFINE_BIT(BRW_NEW_CONTEXT),
 270    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 271    DEFINE_BIT(BRW_NEW_PSP),
 272    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 273    DEFINE_BIT(BRW_NEW_BINDING_TABLE),
 274    DEFINE_BIT(BRW_NEW_INDICES),
 275    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 276    DEFINE_BIT(BRW_NEW_VERTICES),
 277    DEFINE_BIT(BRW_NEW_BATCH),
 278    DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
 279    {0, 0, 0}
 280 };
 281
 282 static struct dirty_bit_map cache_bits[] = {
 283    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 284    DEFINE_BIT(CACHE_NEW_CC_VP),
 285    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 286    DEFINE_BIT(CACHE_NEW_WM_PROG),
 287    DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR),
 288    DEFINE_BIT(CACHE_NEW_SAMPLER),
 289    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 290    DEFINE_BIT(CACHE_NEW_SF_PROG),
 291    DEFINE_BIT(CACHE_NEW_SF_VP),
 292    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 293    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 294    DEFINE_BIT(CACHE_NEW_VS_PROG),
 295    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 296    DEFINE_BIT(CACHE_NEW_GS_PROG),
 297    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 298    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 299    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 300    {0, 0, 0}
 301 };
 302
 303
 304 static void
 305 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 306 {
 307    int i;
 308
 309    for (i = 0; i < 32; i++) {
 310       if (bit_map[i].bit == 0)
 311          return;
 312
 313       if (bit_map[i].bit & bits)
 314          bit_map[i].count++;
 315    }
 316 }
 317
 318 static void
 319 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 320 {
 321    int i;
 322
 323    for (i = 0; i < 32; i++) {
 324       if (bit_map[i].bit == 0)
 325          return;
 326
 327       fprintf(stderr, "0x%08x: %12d (%s)\n",
 328               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 329    }
 330 }
 331
 332 /***********************************************************************
 333  * Emit all state:
 334  */
 335 void brw_validate_state( struct brw_context *brw )
 336 {
 337    GLcontext *ctx = &brw->intel.ctx;
 338    struct intel_context *intel = &brw->intel;
 339    struct brw_state_flags *state = &brw->state.dirty;
 340    GLuint i;
 341    const struct brw_tracked_state **atoms;
 342    int num_atoms;
 343
 344    brw_clear_validated_bos(brw);
 345
 346    state->mesa |= brw->intel.NewGLState;
 347    brw->intel.NewGLState = 0;
 348
 349    brw_add_validated_bo(brw, intel->batch->buf);
 350
 351    if (IS_GEN6(intel->intelScreen->deviceID)) {
 352       atoms = gen6_atoms;
 353       num_atoms = ARRAY_SIZE(gen6_atoms);
 354    } else {
 355       atoms = gen4_atoms;
 356       num_atoms = ARRAY_SIZE(gen4_atoms);
 357    }
 358
 359    if (brw->emit_state_always) {
 360       state->mesa |= ~0;
 361       state->brw |= ~0;
 362       state->cache |= ~0;
 363    }
 364
 365    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 366       brw->fragment_program = ctx->FragmentProgram._Current;
 367       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 368    }
 369
 370    if (brw->vertex_program != ctx->VertexProgram._Current) {
 371       brw->vertex_program = ctx->VertexProgram._Current;
 372       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 373    }
 374
 375    if (state->mesa == 0 &&
 376        state->cache == 0 &&
 377        state->brw == 0)
 378       return;
 379
 380    if (brw->state.dirty.brw & BRW_NEW_CONTEXT)
 381       brw_clear_batch_cache(brw);
 382
 383    brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
 384
 385    /* do prepare stage for all atoms */
 386    for (i = 0; i < num_atoms; i++) {
 387       const struct brw_tracked_state *atom = atoms[i];
 388
 389       if (brw->intel.Fallback)
 390          break;
 391
 392       if (check_state(state, &atom->dirty)) {
 393          if (atom->prepare) {
 394             atom->prepare(brw);
 395         }
 396       }
 397    }
 398
 399    intel_check_front_buffer_rendering(intel);
 400
 401    /* Make sure that the textures which are referenced by the current
 402     * brw fragment program are actually present/valid.
 403     * If this fails, we can experience GPU lock-ups.
 404     */
 405    {
 406       const struct brw_fragment_program *fp;
 407       fp = brw_fragment_program_const(brw->fragment_program);
 408       if (fp) {
 409          assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
 410                 == fp->tex_units_used);
 411       }
 412    }
 413 }
 414
 415
 416 void brw_upload_state(struct brw_context *brw)
 417 {
 418    struct intel_context *intel = &brw->intel;
 419    struct brw_state_flags *state = &brw->state.dirty;
 420    int i;
 421    static int dirty_count = 0;
 422    const struct brw_tracked_state **atoms;
 423    int num_atoms;
 424
 425    if (IS_GEN6(intel->intelScreen->deviceID)) {
 426       atoms = gen6_atoms;
 427       num_atoms = ARRAY_SIZE(gen6_atoms);
 428    } else {
 429       atoms = gen4_atoms;
 430       num_atoms = ARRAY_SIZE(gen4_atoms);
 431    }
 432
 433    brw_clear_validated_bos(brw);
 434
 435    if (INTEL_DEBUG) {
 436       /* Debug version which enforces various sanity checks on the
 437        * state flags which are generated and checked to help ensure
 438        * state atoms are ordered correctly in the list.
 439        */
 440       struct brw_state_flags examined, prev;
 441       memset(&examined, 0, sizeof(examined));
 442       prev = *state;
 443
 444       for (i = 0; i < num_atoms; i++) {
 445          const struct brw_tracked_state *atom = atoms[i];
 446          struct brw_state_flags generated;
 447
 448          assert(atom->dirty.mesa ||
 449                 atom->dirty.brw ||
 450                 atom->dirty.cache);
 451
 452          if (brw->intel.Fallback)
 453             break;
 454
 455          if (check_state(state, &atom->dirty)) {
 456             if (atom->emit) {
 457                atom->emit( brw );
 458             }
 459          }
 460
 461          accumulate_state(&examined, &atom->dirty);
 462
 463          /* generated = (prev ^ state)
 464           * if (examined & generated)
 465           *     fail;
 466           */
 467          xor_states(&generated, &prev, state);
 468          assert(!check_state(&examined, &generated));
 469          prev = *state;
 470       }
 471    }
 472    else {
 473       for (i = 0; i < num_atoms; i++) {
 474          const struct brw_tracked_state *atom = atoms[i];
 475
 476          if (brw->intel.Fallback)
 477             break;
 478
 479          if (check_state(state, &atom->dirty)) {
 480             if (atom->emit) {
 481                atom->emit( brw );
 482             }
 483          }
 484       }
 485    }
 486
 487    if (INTEL_DEBUG & DEBUG_STATE) {
 488       brw_update_dirty_count(mesa_bits, state->mesa);
 489       brw_update_dirty_count(brw_bits, state->brw);
 490       brw_update_dirty_count(cache_bits, state->cache);
 491       if (dirty_count++ % 1000 == 0) {
 492          brw_print_dirty_count(mesa_bits, state->mesa);
 493          brw_print_dirty_count(brw_bits, state->brw);
 494          brw_print_dirty_count(cache_bits, state->cache);
 495          fprintf(stderr, "\n");
 496       }
 497    }
 498
 499    if (!brw->intel.Fallback)
 500       memset(state, 0, sizeof(*state));
 501 }