src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog,
  51    &brw_gs_prog,
  52    &brw_clip_prog,
  53    &brw_sf_prog,
  54    &brw_wm_prog,
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
  67    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
  68
  69    &brw_vs_surfaces,            /* must do before unit */
  70    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  71    &brw_wm_surfaces,            /* must do before samplers and unit */
  72    &brw_wm_binding_table,
  73    &brw_wm_samplers,
  74
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invarient_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_check_fallback,
 111
 112    &brw_wm_input_sizes,
 113    &brw_vs_prog,
 114    &brw_gs_prog,
 115    &brw_wm_prog,
 116
 117    &gen6_clip_vp,
 118    &gen6_sf_vp,
 119
 120    /* Command packets: */
 121    &brw_invarient_state,
 122
 123    /* must do before binding table pointers, cc state ptrs */
 124    &brw_state_base_address,
 125
 126    &brw_cc_vp,
 127    &gen6_viewport_state,        /* must do after *_vp stages */
 128
 129    &gen6_urb,
 130    &gen6_blend_state,           /* must do before cc unit */
 131    &gen6_color_calc_state,      /* must do before cc unit */
 132    &gen6_depth_stencil_state,   /* must do before cc unit */
 133    &gen6_cc_state_pointers,
 134
 135    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 136    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 137    &gen6_vs_constants, /* Before vs_state */
 138    &gen6_wm_constants, /* Before wm_state */
 139
 140    &brw_vs_surfaces,            /* must do before unit */
 141    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 142    &brw_wm_surfaces,            /* must do before samplers and unit */
 143    &brw_wm_binding_table,
 144
 145    &brw_wm_samplers,
 146    &gen6_sampler_state,
 147
 148    &gen6_vs_state,
 149    &gen6_gs_state,
 150    &gen6_clip_state,
 151    &gen6_sf_state,
 152    &gen6_wm_state,
 153
 154    &gen6_scissor_state,
 155
 156    &gen6_binding_table_pointers,
 157
 158    &brw_depthbuffer,
 159
 160    &brw_polygon_stipple,
 161    &brw_polygon_stipple_offset,
 162
 163    &brw_line_stipple,
 164    &brw_aa_line_parameters,
 165
 166    &brw_drawing_rect,
 167
 168    &brw_indices,
 169    &brw_index_buffer,
 170    &brw_vertices,
 171 };
 172
 173 void brw_init_state( struct brw_context *brw )
 174 {
 175    const struct brw_tracked_state **atoms;
 176    int num_atoms;
 177
 178    brw_init_caches(brw);
 179
 180    if (brw->intel.gen >= 6) {
 181       atoms = gen6_atoms;
 182       num_atoms = ARRAY_SIZE(gen6_atoms);
 183    } else {
 184       atoms = gen4_atoms;
 185       num_atoms = ARRAY_SIZE(gen4_atoms);
 186    }
 187
 188    while (num_atoms--) {
 189       assert((*atoms)->dirty.mesa |
 190              (*atoms)->dirty.brw |
 191              (*atoms)->dirty.cache);
 192
 193       if ((*atoms)->prepare)
 194          brw->prepare_atoms[brw->num_prepare_atoms++] = **atoms;
 195       if ((*atoms)->emit)
 196          brw->emit_atoms[brw->num_emit_atoms++] = **atoms;
 197       atoms++;
 198    }
 199    assert(brw->num_emit_atoms <= ARRAY_SIZE(brw->emit_atoms));
 200    assert(brw->num_prepare_atoms <= ARRAY_SIZE(brw->prepare_atoms));
 201 }
 202
 203
 204 void brw_destroy_state( struct brw_context *brw )
 205 {
 206    brw_destroy_caches(brw);
 207 }
 208
 209 /***********************************************************************
 210  */
 211
 212 static GLuint check_state( const struct brw_state_flags *a,
 213                            const struct brw_state_flags *b )
 214 {
 215    return ((a->mesa & b->mesa) |
 216            (a->brw & b->brw) |
 217            (a->cache & b->cache)) != 0;
 218 }
 219
 220 static void accumulate_state( struct brw_state_flags *a,
 221                               const struct brw_state_flags *b )
 222 {
 223    a->mesa |= b->mesa;
 224    a->brw |= b->brw;
 225    a->cache |= b->cache;
 226 }
 227
 228
 229 static void xor_states( struct brw_state_flags *result,
 230                              const struct brw_state_flags *a,
 231                               const struct brw_state_flags *b )
 232 {
 233    result->mesa = a->mesa ^ b->mesa;
 234    result->brw = a->brw ^ b->brw;
 235    result->cache = a->cache ^ b->cache;
 236 }
 237
 238 void
 239 brw_clear_validated_bos(struct brw_context *brw)
 240 {
 241    int i;
 242
 243    /* Clear the last round of validated bos */
 244    for (i = 0; i < brw->state.validated_bo_count; i++) {
 245       drm_intel_bo_unreference(brw->state.validated_bos[i]);
 246       brw->state.validated_bos[i] = NULL;
 247    }
 248    brw->state.validated_bo_count = 0;
 249 }
 250
 251 struct dirty_bit_map {
 252    uint32_t bit;
 253    char *name;
 254    uint32_t count;
 255 };
 256
 257 #define DEFINE_BIT(name) {name, #name, 0}
 258
 259 static struct dirty_bit_map mesa_bits[] = {
 260    DEFINE_BIT(_NEW_MODELVIEW),
 261    DEFINE_BIT(_NEW_PROJECTION),
 262    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 263    DEFINE_BIT(_NEW_COLOR),
 264    DEFINE_BIT(_NEW_DEPTH),
 265    DEFINE_BIT(_NEW_EVAL),
 266    DEFINE_BIT(_NEW_FOG),
 267    DEFINE_BIT(_NEW_HINT),
 268    DEFINE_BIT(_NEW_LIGHT),
 269    DEFINE_BIT(_NEW_LINE),
 270    DEFINE_BIT(_NEW_PIXEL),
 271    DEFINE_BIT(_NEW_POINT),
 272    DEFINE_BIT(_NEW_POLYGON),
 273    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 274    DEFINE_BIT(_NEW_SCISSOR),
 275    DEFINE_BIT(_NEW_STENCIL),
 276    DEFINE_BIT(_NEW_TEXTURE),
 277    DEFINE_BIT(_NEW_TRANSFORM),
 278    DEFINE_BIT(_NEW_VIEWPORT),
 279    DEFINE_BIT(_NEW_PACKUNPACK),
 280    DEFINE_BIT(_NEW_ARRAY),
 281    DEFINE_BIT(_NEW_RENDERMODE),
 282    DEFINE_BIT(_NEW_BUFFERS),
 283    DEFINE_BIT(_NEW_MULTISAMPLE),
 284    DEFINE_BIT(_NEW_TRACK_MATRIX),
 285    DEFINE_BIT(_NEW_PROGRAM),
 286    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 287    {0, 0, 0}
 288 };
 289
 290 static struct dirty_bit_map brw_bits[] = {
 291    DEFINE_BIT(BRW_NEW_URB_FENCE),
 292    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 293    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 294    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 295    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 296    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 297    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 298    DEFINE_BIT(BRW_NEW_CONTEXT),
 299    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 300    DEFINE_BIT(BRW_NEW_PSP),
 301    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 302    DEFINE_BIT(BRW_NEW_BINDING_TABLE),
 303    DEFINE_BIT(BRW_NEW_INDICES),
 304    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 305    DEFINE_BIT(BRW_NEW_VERTICES),
 306    DEFINE_BIT(BRW_NEW_BATCH),
 307    DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
 308    DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
 309    DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
 310    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 311    DEFINE_BIT(BRW_NEW_WM_CONSTBUF),
 312    {0, 0, 0}
 313 };
 314
 315 static struct dirty_bit_map cache_bits[] = {
 316    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 317    DEFINE_BIT(CACHE_NEW_CC_VP),
 318    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 319    DEFINE_BIT(CACHE_NEW_WM_PROG),
 320    DEFINE_BIT(CACHE_NEW_SAMPLER),
 321    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 322    DEFINE_BIT(CACHE_NEW_SF_PROG),
 323    DEFINE_BIT(CACHE_NEW_SF_VP),
 324    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 325    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 326    DEFINE_BIT(CACHE_NEW_VS_PROG),
 327    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 328    DEFINE_BIT(CACHE_NEW_GS_PROG),
 329    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 330    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 331    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 332    {0, 0, 0}
 333 };
 334
 335
 336 static void
 337 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 338 {
 339    int i;
 340
 341    for (i = 0; i < 32; i++) {
 342       if (bit_map[i].bit == 0)
 343          return;
 344
 345       if (bit_map[i].bit & bits)
 346          bit_map[i].count++;
 347    }
 348 }
 349
 350 static void
 351 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 352 {
 353    int i;
 354
 355    for (i = 0; i < 32; i++) {
 356       if (bit_map[i].bit == 0)
 357          return;
 358
 359       fprintf(stderr, "0x%08x: %12d (%s)\n",
 360               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 361    }
 362 }
 363
 364 /***********************************************************************
 365  * Emit all state:
 366  */
 367 void brw_validate_state( struct brw_context *brw )
 368 {
 369    struct gl_context *ctx = &brw->intel.ctx;
 370    struct intel_context *intel = &brw->intel;
 371    struct brw_state_flags *state = &brw->state.dirty;
 372    const struct brw_tracked_state *atoms = brw->prepare_atoms;
 373    int num_atoms = brw->num_prepare_atoms;
 374    GLuint i;
 375
 376    brw_clear_validated_bos(brw);
 377
 378    state->mesa |= brw->intel.NewGLState;
 379    brw->intel.NewGLState = 0;
 380
 381    brw_add_validated_bo(brw, intel->batch.bo);
 382
 383    if (brw->emit_state_always) {
 384       state->mesa |= ~0;
 385       state->brw |= ~0;
 386       state->cache |= ~0;
 387    }
 388
 389    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 390       brw->fragment_program = ctx->FragmentProgram._Current;
 391       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 392    }
 393
 394    if (brw->vertex_program != ctx->VertexProgram._Current) {
 395       brw->vertex_program = ctx->VertexProgram._Current;
 396       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 397    }
 398
 399    if ((state->mesa | state->cache | state->brw) == 0)
 400       return;
 401
 402    brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
 403
 404    /* do prepare stage for all atoms */
 405    for (i = 0; i < num_atoms; i++) {
 406       const struct brw_tracked_state *atom = &atoms[i];
 407
 408       if (check_state(state, &atom->dirty)) {
 409          atom->prepare(brw);
 410
 411          if (brw->intel.Fallback)
 412             break;
 413       }
 414    }
 415
 416    intel_check_front_buffer_rendering(intel);
 417
 418    /* Make sure that the textures which are referenced by the current
 419     * brw fragment program are actually present/valid.
 420     * If this fails, we can experience GPU lock-ups.
 421     */
 422    {
 423       const struct brw_fragment_program *fp;
 424       fp = brw_fragment_program_const(brw->fragment_program);
 425       if (fp) {
 426          assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
 427                 == fp->tex_units_used);
 428       }
 429    }
 430 }
 431
 432
 433 void brw_upload_state(struct brw_context *brw)
 434 {
 435    struct brw_state_flags *state = &brw->state.dirty;
 436    const struct brw_tracked_state *atoms = brw->emit_atoms;
 437    int num_atoms = brw->num_emit_atoms;
 438    int i;
 439    static int dirty_count = 0;
 440
 441    brw_clear_validated_bos(brw);
 442
 443    if (unlikely(INTEL_DEBUG)) {
 444       /* Debug version which enforces various sanity checks on the
 445        * state flags which are generated and checked to help ensure
 446        * state atoms are ordered correctly in the list.
 447        */
 448       struct brw_state_flags examined, prev;
 449       memset(&examined, 0, sizeof(examined));
 450       prev = *state;
 451
 452       for (i = 0; i < num_atoms; i++) {
 453          const struct brw_tracked_state *atom = &atoms[i];
 454          struct brw_state_flags generated;
 455
 456          if (brw->intel.Fallback)
 457             break;
 458
 459          if (check_state(state, &atom->dirty)) {
 460             atom->emit(brw);
 461          }
 462
 463          accumulate_state(&examined, &atom->dirty);
 464
 465          /* generated = (prev ^ state)
 466           * if (examined & generated)
 467           *     fail;
 468           */
 469          xor_states(&generated, &prev, state);
 470          assert(!check_state(&examined, &generated));
 471          prev = *state;
 472       }
 473    }
 474    else {
 475       for (i = 0; i < num_atoms; i++) {
 476          const struct brw_tracked_state *atom = &atoms[i];
 477
 478          if (brw->intel.Fallback)
 479             break;
 480
 481          if (check_state(state, &atom->dirty)) {
 482             atom->emit(brw);
 483          }
 484       }
 485    }
 486
 487    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 488       brw_update_dirty_count(mesa_bits, state->mesa);
 489       brw_update_dirty_count(brw_bits, state->brw);
 490       brw_update_dirty_count(cache_bits, state->cache);
 491       if (dirty_count++ % 1000 == 0) {
 492          brw_print_dirty_count(mesa_bits, state->mesa);
 493          brw_print_dirty_count(brw_bits, state->brw);
 494          brw_print_dirty_count(cache_bits, state->cache);
 495          fprintf(stderr, "\n");
 496       }
 497    }
 498
 499    if (!brw->intel.Fallback)
 500       memset(state, 0, sizeof(*state));
 501 }