src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_ff_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_fs_samplers,
  72    &brw_vs_samplers,
  73
  74    /* These set up state for brw_psp_urb_cbs */
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invariant_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices, /* must come before brw_vertices */
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_vs_prog, /* must do before state base address */
 111    &brw_gs_prog, /* must do before state base address */
 112    &brw_wm_prog, /* must do before state base address */
 113
 114    &gen6_clip_vp,
 115    &gen6_sf_vp,
 116
 117    /* Command packets: */
 118
 119    /* must do before binding table pointers, cc state ptrs */
 120    &brw_state_base_address,
 121
 122    &brw_cc_vp,
 123    &gen6_viewport_state,        /* must do after *_vp stages */
 124
 125    &gen6_urb,
 126    &gen6_blend_state,           /* must do before cc unit */
 127    &gen6_color_calc_state,      /* must do before cc unit */
 128    &gen6_depth_stencil_state,   /* must do before cc unit */
 129
 130    &gen6_vs_push_constants, /* Before vs_state */
 131    &gen6_gs_push_constants, /* Before gs_state */
 132    &gen6_wm_push_constants, /* Before wm_state */
 133
 134    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 135     * table upload must be last.
 136     */
 137    &brw_vs_pull_constants,
 138    &brw_vs_ubo_surfaces,
 139    &brw_gs_pull_constants,
 140    &brw_gs_ubo_surfaces,
 141    &brw_wm_pull_constants,
 142    &brw_wm_ubo_surfaces,
 143    &gen6_renderbuffer_surfaces,
 144    &brw_texture_surfaces,
 145    &gen6_sol_surface,
 146    &brw_vs_binding_table,
 147    &gen6_gs_binding_table,
 148    &brw_wm_binding_table,
 149
 150    &brw_fs_samplers,
 151    &brw_vs_samplers,
 152    &brw_gs_samplers,
 153    &gen6_sampler_state,
 154    &gen6_multisample_state,
 155
 156    &gen6_vs_state,
 157    &gen6_gs_state,
 158    &gen6_clip_state,
 159    &gen6_sf_state,
 160    &gen6_wm_state,
 161
 162    &gen6_scissor_state,
 163
 164    &gen6_binding_table_pointers,
 165
 166    &brw_depthbuffer,
 167
 168    &brw_polygon_stipple,
 169    &brw_polygon_stipple_offset,
 170
 171    &brw_line_stipple,
 172    &brw_aa_line_parameters,
 173
 174    &brw_drawing_rect,
 175
 176    &brw_indices, /* must come before brw_vertices */
 177    &brw_index_buffer,
 178    &brw_vertices,
 179 };
 180
 181 static const struct brw_tracked_state *gen7_atoms[] =
 182 {
 183    &brw_vs_prog,
 184    &brw_gs_prog,
 185    &brw_wm_prog,
 186
 187    /* Command packets: */
 188
 189    /* must do before binding table pointers, cc state ptrs */
 190    &brw_state_base_address,
 191
 192    &brw_cc_vp,
 193    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 194    &gen7_sf_clip_viewport,
 195
 196    &gen7_push_constant_space,
 197    &gen7_urb,
 198    &gen6_blend_state,           /* must do before cc unit */
 199    &gen6_color_calc_state,      /* must do before cc unit */
 200    &gen6_depth_stencil_state,   /* must do before cc unit */
 201
 202    &gen6_vs_push_constants, /* Before vs_state */
 203    &gen6_gs_push_constants, /* Before gs_state */
 204    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 205
 206    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 207     * table upload must be last.
 208     */
 209    &brw_vs_pull_constants,
 210    &brw_vs_ubo_surfaces,
 211    &brw_vs_abo_surfaces,
 212    &brw_gs_pull_constants,
 213    &brw_gs_ubo_surfaces,
 214    &brw_gs_abo_surfaces,
 215    &brw_wm_pull_constants,
 216    &brw_wm_ubo_surfaces,
 217    &brw_wm_abo_surfaces,
 218    &gen6_renderbuffer_surfaces,
 219    &brw_texture_surfaces,
 220    &brw_vs_binding_table,
 221    &brw_gs_binding_table,
 222    &brw_wm_binding_table,
 223
 224    &brw_fs_samplers,
 225    &brw_vs_samplers,
 226    &brw_gs_samplers,
 227    &gen6_multisample_state,
 228
 229    &gen7_disable_stages,
 230    &gen7_vs_state,
 231    &gen7_gs_state,
 232    &gen7_sol_state,
 233    &gen7_clip_state,
 234    &gen7_sbe_state,
 235    &gen7_sf_state,
 236    &gen7_wm_state,
 237    &gen7_ps_state,
 238
 239    &gen6_scissor_state,
 240
 241    &gen7_depthbuffer,
 242
 243    &brw_polygon_stipple,
 244    &brw_polygon_stipple_offset,
 245
 246    &brw_line_stipple,
 247    &brw_aa_line_parameters,
 248
 249    &brw_drawing_rect,
 250
 251    &brw_indices, /* must come before brw_vertices */
 252    &brw_index_buffer,
 253    &brw_vertices,
 254
 255    &haswell_cut_index,
 256 };
 257
 258 static const struct brw_tracked_state *gen8_atoms[] =
 259 {
 260    &brw_vs_prog,
 261    &brw_gs_prog,
 262    &brw_wm_prog,
 263
 264    /* Command packets: */
 265    &gen8_state_base_address,
 266
 267    &brw_cc_vp,
 268    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 269    &gen8_sf_clip_viewport,
 270
 271    &gen7_push_constant_space,
 272    &gen7_urb,
 273    &gen8_blend_state,
 274    &gen6_color_calc_state,
 275
 276    &gen6_vs_push_constants, /* Before vs_state */
 277    &gen6_gs_push_constants, /* Before gs_state */
 278    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 279
 280    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 281     * table upload must be last.
 282     */
 283    &brw_vs_pull_constants,
 284    &brw_vs_ubo_surfaces,
 285    &brw_vs_abo_surfaces,
 286    &brw_gs_pull_constants,
 287    &brw_gs_ubo_surfaces,
 288    &brw_gs_abo_surfaces,
 289    &brw_wm_pull_constants,
 290    &brw_wm_ubo_surfaces,
 291    &brw_wm_abo_surfaces,
 292    &gen6_renderbuffer_surfaces,
 293    &brw_texture_surfaces,
 294    &brw_vs_binding_table,
 295    &brw_gs_binding_table,
 296    &brw_wm_binding_table,
 297
 298    &brw_fs_samplers,
 299    &brw_vs_samplers,
 300    &brw_gs_samplers,
 301    &gen8_multisample_state,
 302
 303    &gen8_disable_stages,
 304    &gen8_vs_state,
 305    &gen8_gs_state,
 306    &gen8_sol_state,
 307    &gen6_clip_state,
 308    &gen8_raster_state,
 309    &gen8_sbe_state,
 310    &gen8_sf_state,
 311    &gen8_ps_blend,
 312    &gen8_ps_extra,
 313    &gen8_ps_state,
 314    &gen8_wm_depth_stencil,
 315    &gen8_wm_state,
 316
 317    &gen6_scissor_state,
 318
 319    &gen7_depthbuffer,
 320
 321    &brw_polygon_stipple,
 322    &brw_polygon_stipple_offset,
 323
 324    &brw_line_stipple,
 325    &brw_aa_line_parameters,
 326
 327    &brw_drawing_rect,
 328
 329    &gen8_vf_topology,
 330
 331    &brw_indices,
 332    &gen8_index_buffer,
 333    &gen8_vertices,
 334
 335    &haswell_cut_index,
 336 };
 337
 338 static void
 339 brw_upload_initial_gpu_state(struct brw_context *brw)
 340 {
 341    /* On platforms with hardware contexts, we can set our initial GPU state
 342     * right away rather than doing it via state atoms.  This saves a small
 343     * amount of overhead on every draw call.
 344     */
 345    if (!brw->hw_ctx)
 346       return;
 347
 348    brw_upload_invariant_state(brw);
 349
 350    if (brw->gen >= 8) {
 351       gen8_emit_3dstate_sample_pattern(brw);
 352    }
 353 }
 354
 355 void brw_init_state( struct brw_context *brw )
 356 {
 357    struct gl_context *ctx = &brw->ctx;
 358    const struct brw_tracked_state **atoms;
 359    int num_atoms;
 360
 361    brw_init_caches(brw);
 362
 363    if (brw->gen >= 8) {
 364       atoms = gen8_atoms;
 365       num_atoms = ARRAY_SIZE(gen8_atoms);
 366    } else if (brw->gen == 7) {
 367       atoms = gen7_atoms;
 368       num_atoms = ARRAY_SIZE(gen7_atoms);
 369    } else if (brw->gen == 6) {
 370       atoms = gen6_atoms;
 371       num_atoms = ARRAY_SIZE(gen6_atoms);
 372    } else {
 373       atoms = gen4_atoms;
 374       num_atoms = ARRAY_SIZE(gen4_atoms);
 375    }
 376
 377    brw->atoms = atoms;
 378    brw->num_atoms = num_atoms;
 379
 380    while (num_atoms--) {
 381       assert((*atoms)->dirty.mesa |
 382              (*atoms)->dirty.brw |
 383              (*atoms)->dirty.cache);
 384       assert((*atoms)->emit);
 385       atoms++;
 386    }
 387
 388    brw_upload_initial_gpu_state(brw);
 389
 390    brw->state.dirty.mesa = ~0;
 391    brw->state.dirty.brw = ~0;
 392
 393    /* Make sure that brw->state.dirty.brw has enough bits to hold all possible
 394     * dirty flags.
 395     */
 396    STATIC_ASSERT(BRW_NUM_STATE_BITS <= 8 * sizeof(brw->state.dirty.brw));
 397
 398    ctx->DriverFlags.NewTransformFeedback = BRW_NEW_TRANSFORM_FEEDBACK;
 399    ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
 400    ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
 401    ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
 402    ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 403 }
 404
 405
 406 void brw_destroy_state( struct brw_context *brw )
 407 {
 408    brw_destroy_caches(brw);
 409 }
 410
 411 /***********************************************************************
 412  */
 413
 414 static bool
 415 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 416 {
 417    return ((a->mesa & b->mesa) |
 418            (a->brw & b->brw) |
 419            (a->cache & b->cache)) != 0;
 420 }
 421
 422 static void accumulate_state( struct brw_state_flags *a,
 423                               const struct brw_state_flags *b )
 424 {
 425    a->mesa |= b->mesa;
 426    a->brw |= b->brw;
 427    a->cache |= b->cache;
 428 }
 429
 430
 431 static void xor_states( struct brw_state_flags *result,
 432                              const struct brw_state_flags *a,
 433                               const struct brw_state_flags *b )
 434 {
 435    result->mesa = a->mesa ^ b->mesa;
 436    result->brw = a->brw ^ b->brw;
 437    result->cache = a->cache ^ b->cache;
 438 }
 439
 440 struct dirty_bit_map {
 441    uint32_t bit;
 442    char *name;
 443    uint32_t count;
 444 };
 445
 446 #define DEFINE_BIT(name) {name, #name, 0}
 447
 448 static struct dirty_bit_map mesa_bits[] = {
 449    DEFINE_BIT(_NEW_MODELVIEW),
 450    DEFINE_BIT(_NEW_PROJECTION),
 451    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 452    DEFINE_BIT(_NEW_COLOR),
 453    DEFINE_BIT(_NEW_DEPTH),
 454    DEFINE_BIT(_NEW_EVAL),
 455    DEFINE_BIT(_NEW_FOG),
 456    DEFINE_BIT(_NEW_HINT),
 457    DEFINE_BIT(_NEW_LIGHT),
 458    DEFINE_BIT(_NEW_LINE),
 459    DEFINE_BIT(_NEW_PIXEL),
 460    DEFINE_BIT(_NEW_POINT),
 461    DEFINE_BIT(_NEW_POLYGON),
 462    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 463    DEFINE_BIT(_NEW_SCISSOR),
 464    DEFINE_BIT(_NEW_STENCIL),
 465    DEFINE_BIT(_NEW_TEXTURE),
 466    DEFINE_BIT(_NEW_TRANSFORM),
 467    DEFINE_BIT(_NEW_VIEWPORT),
 468    DEFINE_BIT(_NEW_ARRAY),
 469    DEFINE_BIT(_NEW_RENDERMODE),
 470    DEFINE_BIT(_NEW_BUFFERS),
 471    DEFINE_BIT(_NEW_CURRENT_ATTRIB),
 472    DEFINE_BIT(_NEW_MULTISAMPLE),
 473    DEFINE_BIT(_NEW_TRACK_MATRIX),
 474    DEFINE_BIT(_NEW_PROGRAM),
 475    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 476    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 477    DEFINE_BIT(_NEW_FRAG_CLAMP),
 478    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 479    {0, 0, 0}
 480 };
 481
 482 static struct dirty_bit_map brw_bits[] = {
 483    DEFINE_BIT(BRW_NEW_URB_FENCE),
 484    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 485    DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM),
 486    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 487    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 488    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 489    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 490    DEFINE_BIT(BRW_NEW_CONTEXT),
 491    DEFINE_BIT(BRW_NEW_PSP),
 492    DEFINE_BIT(BRW_NEW_SURFACES),
 493    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 494    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 495    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 496    DEFINE_BIT(BRW_NEW_INDICES),
 497    DEFINE_BIT(BRW_NEW_VERTICES),
 498    DEFINE_BIT(BRW_NEW_BATCH),
 499    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 500    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 501    DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
 502    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 503    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 504    DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
 505    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 506    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 507    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 508    DEFINE_BIT(BRW_NEW_STATS_WM),
 509    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 510    DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER),
 511    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 512    DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
 513    DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 514    DEFINE_BIT(BRW_NEW_NUM_SAMPLES),
 515    {0, 0, 0}
 516 };
 517
 518 static struct dirty_bit_map cache_bits[] = {
 519    DEFINE_BIT(CACHE_NEW_CC_VP),
 520    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 521    DEFINE_BIT(CACHE_NEW_WM_PROG),
 522    DEFINE_BIT(CACHE_NEW_BLORP_BLIT_PROG),
 523    DEFINE_BIT(CACHE_NEW_BLORP_CONST_COLOR_PROG),
 524    DEFINE_BIT(CACHE_NEW_SAMPLER),
 525    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 526    DEFINE_BIT(CACHE_NEW_SF_PROG),
 527    DEFINE_BIT(CACHE_NEW_SF_VP),
 528    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 529    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 530    DEFINE_BIT(CACHE_NEW_VS_PROG),
 531    DEFINE_BIT(CACHE_NEW_FF_GS_UNIT),
 532    DEFINE_BIT(CACHE_NEW_FF_GS_PROG),
 533    DEFINE_BIT(CACHE_NEW_GS_PROG),
 534    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 535    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 536    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 537    {0, 0, 0}
 538 };
 539
 540
 541 static void
 542 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 543 {
 544    int i;
 545
 546    for (i = 0; i < 32; i++) {
 547       if (bit_map[i].bit == 0)
 548          return;
 549
 550       if (bit_map[i].bit & bits)
 551          bit_map[i].count++;
 552    }
 553 }
 554
 555 static void
 556 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 557 {
 558    int i;
 559
 560    for (i = 0; i < 32; i++) {
 561       if (bit_map[i].bit == 0)
 562          return;
 563
 564       fprintf(stderr, "0x%08x: %12d (%s)\n",
 565               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 566    }
 567 }
 568
 569 /***********************************************************************
 570  * Emit all state:
 571  */
 572 void brw_upload_state(struct brw_context *brw)
 573 {
 574    struct gl_context *ctx = &brw->ctx;
 575    struct brw_state_flags *state = &brw->state.dirty;
 576    int i;
 577    static int dirty_count = 0;
 578
 579    state->mesa |= brw->NewGLState;
 580    brw->NewGLState = 0;
 581
 582    state->brw |= ctx->NewDriverState;
 583    ctx->NewDriverState = 0;
 584
 585    if (0) {
 586       /* Always re-emit all state. */
 587       state->mesa |= ~0;
 588       state->brw |= ~0;
 589       state->cache |= ~0;
 590    }
 591
 592    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 593       brw->fragment_program = ctx->FragmentProgram._Current;
 594       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 595    }
 596
 597    if (brw->geometry_program != ctx->GeometryProgram._Current) {
 598       brw->geometry_program = ctx->GeometryProgram._Current;
 599       brw->state.dirty.brw |= BRW_NEW_GEOMETRY_PROGRAM;
 600    }
 601
 602    if (brw->vertex_program != ctx->VertexProgram._Current) {
 603       brw->vertex_program = ctx->VertexProgram._Current;
 604       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 605    }
 606
 607    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 608       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 609       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 610    }
 611
 612    if (brw->num_samples != ctx->DrawBuffer->Visual.samples) {
 613       brw->num_samples = ctx->DrawBuffer->Visual.samples;
 614       brw->state.dirty.brw |= BRW_NEW_NUM_SAMPLES;
 615    }
 616
 617    if ((state->mesa | state->cache | state->brw) == 0)
 618       return;
 619
 620    if (unlikely(INTEL_DEBUG)) {
 621       /* Debug version which enforces various sanity checks on the
 622        * state flags which are generated and checked to help ensure
 623        * state atoms are ordered correctly in the list.
 624        */
 625       struct brw_state_flags examined, prev;
 626       memset(&examined, 0, sizeof(examined));
 627       prev = *state;
 628
 629       for (i = 0; i < brw->num_atoms; i++) {
 630          const struct brw_tracked_state *atom = brw->atoms[i];
 631          struct brw_state_flags generated;
 632
 633          if (check_state(state, &atom->dirty)) {
 634             atom->emit(brw);
 635          }
 636
 637          accumulate_state(&examined, &atom->dirty);
 638
 639          /* generated = (prev ^ state)
 640           * if (examined & generated)
 641           *     fail;
 642           */
 643          xor_states(&generated, &prev, state);
 644          assert(!check_state(&examined, &generated));
 645          prev = *state;
 646       }
 647    }
 648    else {
 649       for (i = 0; i < brw->num_atoms; i++) {
 650          const struct brw_tracked_state *atom = brw->atoms[i];
 651
 652          if (check_state(state, &atom->dirty)) {
 653             atom->emit(brw);
 654          }
 655       }
 656    }
 657
 658    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 659       STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
 660       STATIC_ASSERT(ARRAY_SIZE(cache_bits) == BRW_MAX_CACHE + 1);
 661
 662       brw_update_dirty_count(mesa_bits, state->mesa);
 663       brw_update_dirty_count(brw_bits, state->brw);
 664       brw_update_dirty_count(cache_bits, state->cache);
 665       if (dirty_count++ % 1000 == 0) {
 666          brw_print_dirty_count(mesa_bits);
 667          brw_print_dirty_count(brw_bits);
 668          brw_print_dirty_count(cache_bits);
 669          fprintf(stderr, "\n");
 670       }
 671    }
 672 }
 673
 674
 675 /**
 676  * Clear dirty bits to account for the fact that the state emitted by
 677  * brw_upload_state() has been committed to the hardware.  This is a separate
 678  * call from brw_upload_state() because it's possible that after the call to
 679  * brw_upload_state(), we will discover that we've run out of aperture space,
 680  * and need to rewind the batch buffer to the state it had before the
 681  * brw_upload_state() call.
 682  */
 683 void
 684 brw_clear_dirty_bits(struct brw_context *brw)
 685 {
 686    struct brw_state_flags *state = &brw->state.dirty;
 687    memset(state, 0, sizeof(*state));
 688 }