2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "drivers/common/meta.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_buffers.h"
40 #include "brw_ff_gs.h"
44 #include "main/framebuffer.h"
46 static const struct brw_tracked_state
*gen4_atoms
[] =
48 &brw_interpolation_map
,
50 &brw_clip_prog
, /* must do before state base address */
51 &brw_sf_prog
, /* must do before state base address */
53 /* Once all the programs are done, we know how large urb entry
54 * sizes need to be and can decide if we need to change the urb
58 &brw_recalculate_urb_fence
,
63 /* Surface state setup. Must come before the VS/WM unit. The binding
64 * table upload must be last.
66 &brw_vs_pull_constants
,
67 &brw_wm_pull_constants
,
68 &brw_renderbuffer_surfaces
,
69 &brw_texture_surfaces
,
70 &brw_vs_binding_table
,
71 &brw_wm_binding_table
,
76 /* These set up state for brw_psp_urb_cbs */
80 &brw_vs_unit
, /* always required, enabled or not */
87 &brw_state_base_address
,
89 &brw_binding_table_pointers
,
90 &brw_blend_constant_color
,
95 &brw_polygon_stipple_offset
,
98 &brw_aa_line_parameters
,
103 &brw_indices
, /* must come before brw_vertices */
110 static const struct brw_tracked_state
*gen6_atoms
[] =
115 /* Command packets: */
117 /* must do before binding table pointers, cc state ptrs */
118 &brw_state_base_address
,
121 &gen6_viewport_state
, /* must do after *_vp stages */
124 &gen6_blend_state
, /* must do before cc unit */
125 &gen6_color_calc_state
, /* must do before cc unit */
126 &gen6_depth_stencil_state
, /* must do before cc unit */
128 &gen6_vs_push_constants
, /* Before vs_state */
129 &gen6_gs_push_constants
, /* Before gs_state */
130 &gen6_wm_push_constants
, /* Before wm_state */
132 /* Surface state setup. Must come before the VS/WM unit. The binding
133 * table upload must be last.
135 &brw_vs_pull_constants
,
136 &brw_vs_ubo_surfaces
,
137 &brw_gs_pull_constants
,
138 &brw_gs_ubo_surfaces
,
139 &brw_wm_pull_constants
,
140 &brw_wm_ubo_surfaces
,
141 &gen6_renderbuffer_surfaces
,
142 &brw_texture_surfaces
,
144 &brw_vs_binding_table
,
145 &gen6_gs_binding_table
,
146 &brw_wm_binding_table
,
152 &gen6_multisample_state
,
162 &gen6_binding_table_pointers
,
166 &brw_polygon_stipple
,
167 &brw_polygon_stipple_offset
,
170 &brw_aa_line_parameters
,
174 &brw_indices
, /* must come before brw_vertices */
179 static const struct brw_tracked_state
*gen7_render_atoms
[] =
181 /* Command packets: */
183 /* must do before binding table pointers, cc state ptrs */
184 &brw_state_base_address
,
187 &gen7_sf_clip_viewport
,
189 &gen7_push_constant_space
,
191 &gen6_blend_state
, /* must do before cc unit */
192 &gen6_color_calc_state
, /* must do before cc unit */
193 &gen6_depth_stencil_state
, /* must do before cc unit */
195 &gen7_hw_binding_tables
, /* Enable hw-generated binding tables for Haswell */
197 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
198 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
199 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
201 &gen6_vs_push_constants
, /* Before vs_state */
202 &gen6_gs_push_constants
, /* Before gs_state */
203 &gen6_wm_push_constants
, /* Before wm_surfaces and constant_buffer */
205 /* Surface state setup. Must come before the VS/WM unit. The binding
206 * table upload must be last.
208 &brw_vs_pull_constants
,
209 &brw_vs_ubo_surfaces
,
210 &brw_vs_abo_surfaces
,
211 &brw_gs_pull_constants
,
212 &brw_gs_ubo_surfaces
,
213 &brw_gs_abo_surfaces
,
214 &brw_wm_pull_constants
,
215 &brw_wm_ubo_surfaces
,
216 &brw_wm_abo_surfaces
,
217 &gen6_renderbuffer_surfaces
,
218 &brw_texture_surfaces
,
219 &brw_vs_binding_table
,
220 &brw_gs_binding_table
,
221 &brw_wm_binding_table
,
226 &gen6_multisample_state
,
228 &gen7_disable_stages
,
242 &brw_polygon_stipple
,
243 &brw_polygon_stipple_offset
,
246 &brw_aa_line_parameters
,
250 &brw_indices
, /* must come before brw_vertices */
257 static const struct brw_tracked_state
*gen7_compute_atoms
[] =
259 &brw_state_base_address
,
260 &brw_cs_image_surfaces
,
261 &brw_cs_abo_surfaces
,
265 static const struct brw_tracked_state
*gen8_render_atoms
[] =
267 /* Command packets: */
268 &gen8_state_base_address
,
271 &gen8_sf_clip_viewport
,
273 &gen7_push_constant_space
,
276 &gen6_color_calc_state
,
278 &gen7_hw_binding_tables
, /* Enable hw-generated binding tables for Broadwell */
280 &brw_vs_image_surfaces
, /* Before vs push/pull constants and binding table */
281 &brw_gs_image_surfaces
, /* Before gs push/pull constants and binding table */
282 &brw_wm_image_surfaces
, /* Before wm push/pull constants and binding table */
284 &gen6_vs_push_constants
, /* Before vs_state */
285 &gen6_gs_push_constants
, /* Before gs_state */
286 &gen6_wm_push_constants
, /* Before wm_surfaces and constant_buffer */
288 /* Surface state setup. Must come before the VS/WM unit. The binding
289 * table upload must be last.
291 &brw_vs_pull_constants
,
292 &brw_vs_ubo_surfaces
,
293 &brw_vs_abo_surfaces
,
294 &brw_gs_pull_constants
,
295 &brw_gs_ubo_surfaces
,
296 &brw_gs_abo_surfaces
,
297 &brw_wm_pull_constants
,
298 &brw_wm_ubo_surfaces
,
299 &brw_wm_abo_surfaces
,
300 &gen6_renderbuffer_surfaces
,
301 &brw_texture_surfaces
,
302 &brw_vs_binding_table
,
303 &brw_gs_binding_table
,
304 &brw_wm_binding_table
,
309 &gen8_multisample_state
,
311 &gen8_disable_stages
,
322 &gen8_wm_depth_stencil
,
329 &brw_polygon_stipple
,
330 &brw_polygon_stipple_offset
,
333 &brw_aa_line_parameters
,
347 static const struct brw_tracked_state
*gen8_compute_atoms
[] =
349 &gen8_state_base_address
,
350 &brw_cs_image_surfaces
,
351 &brw_cs_abo_surfaces
,
356 brw_upload_initial_gpu_state(struct brw_context
*brw
)
358 /* On platforms with hardware contexts, we can set our initial GPU state
359 * right away rather than doing it via state atoms. This saves a small
360 * amount of overhead on every draw call.
366 brw_emit_post_sync_nonzero_flush(brw
);
368 brw_upload_invariant_state(brw
);
370 /* Recommended optimization for Victim Cache eviction in pixel backend. */
373 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
374 OUT_BATCH(GEN7_CACHE_MODE_1
);
375 OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
<< 16) |
376 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
);
381 gen8_emit_3dstate_sample_pattern(brw
);
385 static inline const struct brw_tracked_state
*
386 brw_get_pipeline_atoms(struct brw_context
*brw
,
387 enum brw_pipeline pipeline
)
390 case BRW_RENDER_PIPELINE
:
391 return brw
->render_atoms
;
392 case BRW_COMPUTE_PIPELINE
:
393 return brw
->compute_atoms
;
395 STATIC_ASSERT(BRW_NUM_PIPELINES
== 2);
396 unreachable("Unsupported pipeline");
402 brw_copy_pipeline_atoms(struct brw_context
*brw
,
403 enum brw_pipeline pipeline
,
404 const struct brw_tracked_state
**atoms
,
407 /* This is to work around brw_context::atoms being declared const. We want
408 * it to be const, but it needs to be initialized somehow!
410 struct brw_tracked_state
*context_atoms
=
411 (struct brw_tracked_state
*) brw_get_pipeline_atoms(brw
, pipeline
);
413 for (int i
= 0; i
< num_atoms
; i
++) {
414 context_atoms
[i
] = *atoms
[i
];
415 assert(context_atoms
[i
].dirty
.mesa
| context_atoms
[i
].dirty
.brw
);
416 assert(context_atoms
[i
].emit
);
419 brw
->num_atoms
[pipeline
] = num_atoms
;
422 void brw_init_state( struct brw_context
*brw
)
424 struct gl_context
*ctx
= &brw
->ctx
;
426 /* Force the first brw_select_pipeline to emit pipeline select */
427 brw
->last_pipeline
= BRW_NUM_PIPELINES
;
429 STATIC_ASSERT(ARRAY_SIZE(gen4_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
430 STATIC_ASSERT(ARRAY_SIZE(gen6_atoms
) <= ARRAY_SIZE(brw
->render_atoms
));
431 STATIC_ASSERT(ARRAY_SIZE(gen7_render_atoms
) <=
432 ARRAY_SIZE(brw
->render_atoms
));
433 STATIC_ASSERT(ARRAY_SIZE(gen8_render_atoms
) <=
434 ARRAY_SIZE(brw
->render_atoms
));
435 STATIC_ASSERT(ARRAY_SIZE(gen7_compute_atoms
) <=
436 ARRAY_SIZE(brw
->compute_atoms
));
437 STATIC_ASSERT(ARRAY_SIZE(gen8_compute_atoms
) <=
438 ARRAY_SIZE(brw
->compute_atoms
));
440 brw_init_caches(brw
);
443 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
445 ARRAY_SIZE(gen8_render_atoms
));
446 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
448 ARRAY_SIZE(gen8_compute_atoms
));
449 } else if (brw
->gen
== 7) {
450 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
452 ARRAY_SIZE(gen7_render_atoms
));
453 brw_copy_pipeline_atoms(brw
, BRW_COMPUTE_PIPELINE
,
455 ARRAY_SIZE(gen7_compute_atoms
));
456 } else if (brw
->gen
== 6) {
457 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
458 gen6_atoms
, ARRAY_SIZE(gen6_atoms
));
460 brw_copy_pipeline_atoms(brw
, BRW_RENDER_PIPELINE
,
461 gen4_atoms
, ARRAY_SIZE(gen4_atoms
));
464 brw_upload_initial_gpu_state(brw
);
466 brw
->NewGLState
= ~0;
467 brw
->ctx
.NewDriverState
= ~0ull;
469 /* ~0 is a nonsensical value which won't match anything we program, so
470 * the programming will take effect on the first time around.
472 brw
->pma_stall_bits
= ~0;
474 /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
477 STATIC_ASSERT(BRW_NUM_STATE_BITS
<= 8 * sizeof(brw
->ctx
.NewDriverState
));
479 ctx
->DriverFlags
.NewTransformFeedback
= BRW_NEW_TRANSFORM_FEEDBACK
;
480 ctx
->DriverFlags
.NewTransformFeedbackProg
= BRW_NEW_TRANSFORM_FEEDBACK
;
481 ctx
->DriverFlags
.NewRasterizerDiscard
= BRW_NEW_RASTERIZER_DISCARD
;
482 ctx
->DriverFlags
.NewUniformBuffer
= BRW_NEW_UNIFORM_BUFFER
;
483 ctx
->DriverFlags
.NewTextureBuffer
= BRW_NEW_TEXTURE_BUFFER
;
484 ctx
->DriverFlags
.NewAtomicBuffer
= BRW_NEW_ATOMIC_BUFFER
;
485 ctx
->DriverFlags
.NewImageUnits
= BRW_NEW_IMAGE_UNITS
;
489 void brw_destroy_state( struct brw_context
*brw
)
491 brw_destroy_caches(brw
);
494 /***********************************************************************
498 check_state(const struct brw_state_flags
*a
, const struct brw_state_flags
*b
)
500 return ((a
->mesa
& b
->mesa
) | (a
->brw
& b
->brw
)) != 0;
503 static void accumulate_state( struct brw_state_flags
*a
,
504 const struct brw_state_flags
*b
)
511 static void xor_states( struct brw_state_flags
*result
,
512 const struct brw_state_flags
*a
,
513 const struct brw_state_flags
*b
)
515 result
->mesa
= a
->mesa
^ b
->mesa
;
516 result
->brw
= a
->brw
^ b
->brw
;
519 struct dirty_bit_map
{
525 #define DEFINE_BIT(name) {name, #name, 0}
527 static struct dirty_bit_map mesa_bits
[] = {
528 DEFINE_BIT(_NEW_MODELVIEW
),
529 DEFINE_BIT(_NEW_PROJECTION
),
530 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
531 DEFINE_BIT(_NEW_COLOR
),
532 DEFINE_BIT(_NEW_DEPTH
),
533 DEFINE_BIT(_NEW_EVAL
),
534 DEFINE_BIT(_NEW_FOG
),
535 DEFINE_BIT(_NEW_HINT
),
536 DEFINE_BIT(_NEW_LIGHT
),
537 DEFINE_BIT(_NEW_LINE
),
538 DEFINE_BIT(_NEW_PIXEL
),
539 DEFINE_BIT(_NEW_POINT
),
540 DEFINE_BIT(_NEW_POLYGON
),
541 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
542 DEFINE_BIT(_NEW_SCISSOR
),
543 DEFINE_BIT(_NEW_STENCIL
),
544 DEFINE_BIT(_NEW_TEXTURE
),
545 DEFINE_BIT(_NEW_TRANSFORM
),
546 DEFINE_BIT(_NEW_VIEWPORT
),
547 DEFINE_BIT(_NEW_ARRAY
),
548 DEFINE_BIT(_NEW_RENDERMODE
),
549 DEFINE_BIT(_NEW_BUFFERS
),
550 DEFINE_BIT(_NEW_CURRENT_ATTRIB
),
551 DEFINE_BIT(_NEW_MULTISAMPLE
),
552 DEFINE_BIT(_NEW_TRACK_MATRIX
),
553 DEFINE_BIT(_NEW_PROGRAM
),
554 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
555 DEFINE_BIT(_NEW_BUFFER_OBJECT
),
556 DEFINE_BIT(_NEW_FRAG_CLAMP
),
557 /* Avoid sign extension problems. */
558 {(unsigned) _NEW_VARYING_VP_INPUTS
, "_NEW_VARYING_VP_INPUTS", 0},
562 static struct dirty_bit_map brw_bits
[] = {
563 DEFINE_BIT(BRW_NEW_FS_PROG_DATA
),
564 DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA
),
565 DEFINE_BIT(BRW_NEW_SF_PROG_DATA
),
566 DEFINE_BIT(BRW_NEW_VS_PROG_DATA
),
567 DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA
),
568 DEFINE_BIT(BRW_NEW_GS_PROG_DATA
),
569 DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA
),
570 DEFINE_BIT(BRW_NEW_CS_PROG_DATA
),
571 DEFINE_BIT(BRW_NEW_URB_FENCE
),
572 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
573 DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM
),
574 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
575 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS
),
576 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
577 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
578 DEFINE_BIT(BRW_NEW_CONTEXT
),
579 DEFINE_BIT(BRW_NEW_PSP
),
580 DEFINE_BIT(BRW_NEW_SURFACES
),
581 DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE
),
582 DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE
),
583 DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE
),
584 DEFINE_BIT(BRW_NEW_INDICES
),
585 DEFINE_BIT(BRW_NEW_VERTICES
),
586 DEFINE_BIT(BRW_NEW_BATCH
),
587 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
588 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
589 DEFINE_BIT(BRW_NEW_GS_CONSTBUF
),
590 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
591 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
592 DEFINE_BIT(BRW_NEW_VUE_MAP_VS
),
593 DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT
),
594 DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK
),
595 DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD
),
596 DEFINE_BIT(BRW_NEW_STATS_WM
),
597 DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER
),
598 DEFINE_BIT(BRW_NEW_ATOMIC_BUFFER
),
599 DEFINE_BIT(BRW_NEW_IMAGE_UNITS
),
600 DEFINE_BIT(BRW_NEW_META_IN_PROGRESS
),
601 DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP
),
602 DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
603 DEFINE_BIT(BRW_NEW_NUM_SAMPLES
),
604 DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER
),
605 DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE
),
606 DEFINE_BIT(BRW_NEW_CC_VP
),
607 DEFINE_BIT(BRW_NEW_SF_VP
),
608 DEFINE_BIT(BRW_NEW_CLIP_VP
),
609 DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE
),
610 DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS
),
611 DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM
),
616 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, uint64_t bits
)
618 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
619 if (bit_map
[i
].bit
& bits
)
625 brw_print_dirty_count(struct dirty_bit_map
*bit_map
)
627 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
628 if (bit_map
[i
].count
> 1) {
629 fprintf(stderr
, "0x%016lx: %12d (%s)\n",
630 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
636 brw_upload_programs(struct brw_context
*brw
,
637 enum brw_pipeline pipeline
)
639 if (pipeline
== BRW_RENDER_PIPELINE
) {
640 brw_upload_vs_prog(brw
);
643 brw_upload_ff_gs_prog(brw
);
645 brw_upload_gs_prog(brw
);
647 brw_upload_wm_prog(brw
);
648 } else if (pipeline
== BRW_COMPUTE_PIPELINE
) {
649 brw_upload_cs_prog(brw
);
654 merge_ctx_state(struct brw_context
*brw
,
655 struct brw_state_flags
*state
)
657 state
->mesa
|= brw
->NewGLState
;
658 state
->brw
|= brw
->ctx
.NewDriverState
;
662 check_and_emit_atom(struct brw_context
*brw
,
663 struct brw_state_flags
*state
,
664 const struct brw_tracked_state
*atom
)
666 if (check_state(state
, &atom
->dirty
)) {
668 merge_ctx_state(brw
, state
);
673 brw_upload_pipeline_state(struct brw_context
*brw
,
674 enum brw_pipeline pipeline
)
676 struct gl_context
*ctx
= &brw
->ctx
;
678 static int dirty_count
= 0;
679 struct brw_state_flags state
= brw
->state
.pipelines
[pipeline
];
680 unsigned int fb_samples
= _mesa_geometric_samples(ctx
->DrawBuffer
);
682 brw_select_pipeline(brw
, pipeline
);
685 /* Always re-emit all state. */
686 brw
->NewGLState
= ~0;
687 ctx
->NewDriverState
= ~0ull;
690 if (pipeline
== BRW_RENDER_PIPELINE
) {
691 if (brw
->fragment_program
!= ctx
->FragmentProgram
._Current
) {
692 brw
->fragment_program
= ctx
->FragmentProgram
._Current
;
693 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
696 if (brw
->geometry_program
!= ctx
->GeometryProgram
._Current
) {
697 brw
->geometry_program
= ctx
->GeometryProgram
._Current
;
698 brw
->ctx
.NewDriverState
|= BRW_NEW_GEOMETRY_PROGRAM
;
701 if (brw
->vertex_program
!= ctx
->VertexProgram
._Current
) {
702 brw
->vertex_program
= ctx
->VertexProgram
._Current
;
703 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
707 if (brw
->compute_program
!= ctx
->ComputeProgram
._Current
) {
708 brw
->compute_program
= ctx
->ComputeProgram
._Current
;
709 brw
->ctx
.NewDriverState
|= BRW_NEW_COMPUTE_PROGRAM
;
712 if (brw
->meta_in_progress
!= _mesa_meta_in_progress(ctx
)) {
713 brw
->meta_in_progress
= _mesa_meta_in_progress(ctx
);
714 brw
->ctx
.NewDriverState
|= BRW_NEW_META_IN_PROGRESS
;
717 if (brw
->num_samples
!= fb_samples
) {
718 brw
->num_samples
= fb_samples
;
719 brw
->ctx
.NewDriverState
|= BRW_NEW_NUM_SAMPLES
;
722 /* Exit early if no state is flagged as dirty */
723 merge_ctx_state(brw
, &state
);
724 if ((state
.mesa
| state
.brw
) == 0)
727 /* Emit Sandybridge workaround flushes on every primitive, for safety. */
729 brw_emit_post_sync_nonzero_flush(brw
);
731 brw_upload_programs(brw
, pipeline
);
732 merge_ctx_state(brw
, &state
);
734 const struct brw_tracked_state
*atoms
=
735 brw_get_pipeline_atoms(brw
, pipeline
);
736 const int num_atoms
= brw
->num_atoms
[pipeline
];
738 if (unlikely(INTEL_DEBUG
)) {
739 /* Debug version which enforces various sanity checks on the
740 * state flags which are generated and checked to help ensure
741 * state atoms are ordered correctly in the list.
743 struct brw_state_flags examined
, prev
;
744 memset(&examined
, 0, sizeof(examined
));
747 for (i
= 0; i
< num_atoms
; i
++) {
748 const struct brw_tracked_state
*atom
= &atoms
[i
];
749 struct brw_state_flags generated
;
751 check_and_emit_atom(brw
, &state
, atom
);
753 accumulate_state(&examined
, &atom
->dirty
);
755 /* generated = (prev ^ state)
756 * if (examined & generated)
759 xor_states(&generated
, &prev
, &state
);
760 assert(!check_state(&examined
, &generated
));
765 for (i
= 0; i
< num_atoms
; i
++) {
766 const struct brw_tracked_state
*atom
= &atoms
[i
];
768 check_and_emit_atom(brw
, &state
, atom
);
772 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
773 STATIC_ASSERT(ARRAY_SIZE(brw_bits
) == BRW_NUM_STATE_BITS
+ 1);
775 brw_update_dirty_count(mesa_bits
, state
.mesa
);
776 brw_update_dirty_count(brw_bits
, state
.brw
);
777 if (dirty_count
++ % 1000 == 0) {
778 brw_print_dirty_count(mesa_bits
);
779 brw_print_dirty_count(brw_bits
);
780 fprintf(stderr
, "\n");
785 /***********************************************************************
788 void brw_upload_render_state(struct brw_context
*brw
)
790 brw_upload_pipeline_state(brw
, BRW_RENDER_PIPELINE
);
794 brw_pipeline_state_finished(struct brw_context
*brw
,
795 enum brw_pipeline pipeline
)
797 /* Save all dirty state into the other pipelines */
798 for (int i
= 0; i
< BRW_NUM_PIPELINES
; i
++) {
800 brw
->state
.pipelines
[i
].mesa
|= brw
->NewGLState
;
801 brw
->state
.pipelines
[i
].brw
|= brw
->ctx
.NewDriverState
;
803 memset(&brw
->state
.pipelines
[i
], 0, sizeof(struct brw_state_flags
));
808 brw
->ctx
.NewDriverState
= 0ull;
812 * Clear dirty bits to account for the fact that the state emitted by
813 * brw_upload_render_state() has been committed to the hardware. This is a
814 * separate call from brw_upload_render_state() because it's possible that
815 * after the call to brw_upload_render_state(), we will discover that we've
816 * run out of aperture space, and need to rewind the batch buffer to the state
817 * it had before the brw_upload_render_state() call.
820 brw_render_state_finished(struct brw_context
*brw
)
822 brw_pipeline_state_finished(brw
, BRW_RENDER_PIPELINE
);
826 brw_upload_compute_state(struct brw_context
*brw
)
828 brw_upload_pipeline_state(brw
, BRW_COMPUTE_PIPELINE
);
832 brw_compute_state_finished(struct brw_context
*brw
)
834 brw_pipeline_state_finished(brw
, BRW_COMPUTE_PIPELINE
);