2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "brw_context.h"
35 #include "brw_defines.h"
36 #include "brw_state.h"
37 #include "brw_program.h"
38 #include "drivers/common/meta.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_buffers.h"
42 #include "brw_ff_gs.h"
46 #include "main/framebuffer.h"
49 brw_enable_obj_preemption(struct brw_context
*brw
, bool enable
)
51 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
52 assert(devinfo
->gen
>= 9);
54 if (enable
== brw
->object_preemption
)
57 /* A fixed function pipe flush is required before modifying this field */
58 brw_emit_end_of_pipe_sync(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
);
60 bool replay_mode
= enable
?
61 GEN9_REPLAY_MODE_MIDOBJECT
: GEN9_REPLAY_MODE_MIDBUFFER
;
63 /* enable object level preemption */
64 brw_load_register_imm32(brw
, CS_CHICKEN1
,
65 replay_mode
| GEN9_REPLAY_MODE_MASK
);
67 brw
->object_preemption
= enable
;
71 brw_upload_initial_gpu_state(struct brw_context
*brw
)
73 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
74 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
76 /* On platforms with hardware contexts, we can set our initial GPU state
77 * right away rather than doing it via state atoms. This saves a small
78 * amount of overhead on every draw call.
83 if (devinfo
->gen
== 6)
84 brw_emit_post_sync_nonzero_flush(brw
);
86 brw_upload_invariant_state(brw
);
88 if (devinfo
->gen
== 11) {
89 /* The default behavior of bit 5 "Headerless Message for Pre-emptable
90 * Contexts" in SAMPLER MODE register is set to 0, which means
91 * headerless sampler messages are not allowed for pre-emptable
92 * contexts. Set the bit 5 to 1 to allow them.
94 brw_load_register_imm32(brw
, GEN11_SAMPLER_MODE
,
95 HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK
|
96 HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS
);
98 /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
99 * HALF_SLICE_CHICKEN7 register.
101 brw_load_register_imm32(brw
, HALF_SLICE_CHICKEN7
,
102 TEXEL_OFFSET_FIX_MASK
|
103 TEXEL_OFFSET_FIX_ENABLE
);
105 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
106 * in L3CNTLREG register. The default setting of the bit is not the
107 * desirable behavior.
109 brw_load_register_imm32(brw
, GEN8_L3CNTLREG
,
110 GEN8_L3CNTLREG_EDBC_NO_HANG
);
112 /* WaEnableStateCacheRedirectToCS:icl */
113 brw_load_register_imm32(brw
, SLICE_COMMON_ECO_CHICKEN1
,
114 GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE
|
115 REG_MASK(GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE
));
118 if (devinfo
->gen
== 10 || devinfo
->gen
== 11) {
119 /* From gen10 workaround table in h/w specs:
121 * "On 3DSTATE_3D_MODE, driver must always program bits 31:16 of DW1
124 * This means that we end up setting the entire 3D_MODE state. Bits
125 * in this register control things such as slice hashing and we want
126 * the default values of zero at the moment.
129 OUT_BATCH(_3DSTATE_3D_MODE
<< 16 | (2 - 2));
130 OUT_BATCH(0xFFFF << 16);
134 if (devinfo
->gen
== 9) {
135 /* Recommended optimizations for Victim Cache eviction and floating
138 brw_load_register_imm32(brw
, GEN7_CACHE_MODE_1
,
139 REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
) |
140 REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
) |
141 GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE
|
142 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC
);
144 if (gen_device_info_is_9lp(devinfo
)) {
145 brw_load_register_imm32(brw
, GEN7_GT_MODE
,
146 GEN9_SUBSLICE_HASHING_MASK_BITS
|
147 GEN9_SUBSLICE_HASHING_16x16
);
151 if (devinfo
->gen
>= 8) {
152 gen8_emit_3dstate_sample_pattern(brw
);
155 OUT_BATCH(_3DSTATE_WM_HZ_OP
<< 16 | (5 - 2));
163 OUT_BATCH(_3DSTATE_WM_CHROMAKEY
<< 16 | (2 - 2));
168 /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
169 * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address.
171 * This is only safe on kernels with context isolation support.
173 if (!compiler
->constant_buffer_0_is_relative
) {
174 if (devinfo
->gen
>= 9) {
176 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
177 OUT_BATCH(CS_DEBUG_MODE2
);
178 OUT_BATCH(REG_MASK(CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
) |
179 CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
);
181 } else if (devinfo
->gen
== 8) {
183 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
185 OUT_BATCH(REG_MASK(INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
) |
186 INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE
);
191 brw
->object_preemption
= false;
193 if (devinfo
->gen
>= 10)
194 brw_enable_obj_preemption(brw
, true);
197 static inline const struct brw_tracked_state
*
198 brw_get_pipeline_atoms(struct brw_context
*brw
,
199 enum brw_pipeline pipeline
)
202 case BRW_RENDER_PIPELINE
:
203 return brw
->render_atoms
;
204 case BRW_COMPUTE_PIPELINE
:
205 return brw
->compute_atoms
;
207 STATIC_ASSERT(BRW_NUM_PIPELINES
== 2);
208 unreachable("Unsupported pipeline");
214 brw_copy_pipeline_atoms(struct brw_context
*brw
,
215 enum brw_pipeline pipeline
,
216 const struct brw_tracked_state
**atoms
,
219 /* This is to work around brw_context::atoms being declared const. We want
220 * it to be const, but it needs to be initialized somehow!
222 struct brw_tracked_state
*context_atoms
=
223 (struct brw_tracked_state
*) brw_get_pipeline_atoms(brw
, pipeline
);
225 for (int i
= 0; i
< num_atoms
; i
++) {
226 context_atoms
[i
] = *atoms
[i
];
227 assert(context_atoms
[i
].dirty
.mesa
| context_atoms
[i
].dirty
.brw
);
228 assert(context_atoms
[i
].emit
);
231 brw
->num_atoms
[pipeline
] = num_atoms
;
234 void brw_init_state( struct brw_context
*brw
)
236 struct gl_context
*ctx
= &brw
->ctx
;
237 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
239 /* Force the first brw_select_pipeline to emit pipeline select */
240 brw
->last_pipeline
= BRW_NUM_PIPELINES
;
242 brw_init_caches(brw
);
244 if (devinfo
->gen
>= 11)
245 gen11_init_atoms(brw
);
246 else if (devinfo
->gen
>= 10)
247 gen10_init_atoms(brw
);
248 else if (devinfo
->gen
>= 9)
249 gen9_init_atoms(brw
);
250 else if (devinfo
->gen
>= 8)
251 gen8_init_atoms(brw
);
252 else if (devinfo
->is_haswell
)
253 gen75_init_atoms(brw
);
254 else if (devinfo
->gen
>= 7)
255 gen7_init_atoms(brw
);
256 else if (devinfo
->gen
>= 6)
257 gen6_init_atoms(brw
);
258 else if (devinfo
->gen
>= 5)
259 gen5_init_atoms(brw
);
260 else if (devinfo
->is_g4x
)
261 gen45_init_atoms(brw
);
263 gen4_init_atoms(brw
);
265 brw_upload_initial_gpu_state(brw
);
267 brw
->NewGLState
= ~0;
268 brw
->ctx
.NewDriverState
= ~0ull;
270 /* ~0 is a nonsensical value which won't match anything we program, so
271 * the programming will take effect on the first time around.
273 brw
->pma_stall_bits
= ~0;
275 /* Make sure that brw->ctx.NewDriverState has enough bits to hold all possible
278 STATIC_ASSERT(BRW_NUM_STATE_BITS
<= 8 * sizeof(brw
->ctx
.NewDriverState
));
280 ctx
->DriverFlags
.NewTransformFeedback
= BRW_NEW_TRANSFORM_FEEDBACK
;
281 ctx
->DriverFlags
.NewTransformFeedbackProg
= BRW_NEW_TRANSFORM_FEEDBACK
;
282 ctx
->DriverFlags
.NewRasterizerDiscard
= BRW_NEW_RASTERIZER_DISCARD
;
283 ctx
->DriverFlags
.NewUniformBuffer
= BRW_NEW_UNIFORM_BUFFER
;
284 ctx
->DriverFlags
.NewShaderStorageBuffer
= BRW_NEW_UNIFORM_BUFFER
;
285 ctx
->DriverFlags
.NewTextureBuffer
= BRW_NEW_TEXTURE_BUFFER
;
286 ctx
->DriverFlags
.NewAtomicBuffer
= BRW_NEW_UNIFORM_BUFFER
;
287 ctx
->DriverFlags
.NewImageUnits
= BRW_NEW_IMAGE_UNITS
;
288 ctx
->DriverFlags
.NewDefaultTessLevels
= BRW_NEW_DEFAULT_TESS_LEVELS
;
289 ctx
->DriverFlags
.NewIntelConservativeRasterization
= BRW_NEW_CONSERVATIVE_RASTERIZATION
;
293 void brw_destroy_state( struct brw_context
*brw
)
295 brw_destroy_caches(brw
);
298 /***********************************************************************
302 check_state(const struct brw_state_flags
*a
, const struct brw_state_flags
*b
)
304 return ((a
->mesa
& b
->mesa
) | (a
->brw
& b
->brw
)) != 0;
307 static void accumulate_state( struct brw_state_flags
*a
,
308 const struct brw_state_flags
*b
)
315 static void xor_states( struct brw_state_flags
*result
,
316 const struct brw_state_flags
*a
,
317 const struct brw_state_flags
*b
)
319 result
->mesa
= a
->mesa
^ b
->mesa
;
320 result
->brw
= a
->brw
^ b
->brw
;
323 struct dirty_bit_map
{
329 #define DEFINE_BIT(name) {name, #name, 0}
331 static struct dirty_bit_map mesa_bits
[] = {
332 DEFINE_BIT(_NEW_MODELVIEW
),
333 DEFINE_BIT(_NEW_PROJECTION
),
334 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
335 DEFINE_BIT(_NEW_COLOR
),
336 DEFINE_BIT(_NEW_DEPTH
),
337 DEFINE_BIT(_NEW_EVAL
),
338 DEFINE_BIT(_NEW_FOG
),
339 DEFINE_BIT(_NEW_HINT
),
340 DEFINE_BIT(_NEW_LIGHT
),
341 DEFINE_BIT(_NEW_LINE
),
342 DEFINE_BIT(_NEW_PIXEL
),
343 DEFINE_BIT(_NEW_POINT
),
344 DEFINE_BIT(_NEW_POLYGON
),
345 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
346 DEFINE_BIT(_NEW_SCISSOR
),
347 DEFINE_BIT(_NEW_STENCIL
),
348 DEFINE_BIT(_NEW_TEXTURE_OBJECT
),
349 DEFINE_BIT(_NEW_TRANSFORM
),
350 DEFINE_BIT(_NEW_VIEWPORT
),
351 DEFINE_BIT(_NEW_TEXTURE_STATE
),
352 DEFINE_BIT(_NEW_RENDERMODE
),
353 DEFINE_BIT(_NEW_BUFFERS
),
354 DEFINE_BIT(_NEW_CURRENT_ATTRIB
),
355 DEFINE_BIT(_NEW_MULTISAMPLE
),
356 DEFINE_BIT(_NEW_TRACK_MATRIX
),
357 DEFINE_BIT(_NEW_PROGRAM
),
358 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
359 DEFINE_BIT(_NEW_FRAG_CLAMP
),
360 /* Avoid sign extension problems. */
361 {(unsigned) _NEW_VARYING_VP_INPUTS
, "_NEW_VARYING_VP_INPUTS", 0},
365 static struct dirty_bit_map brw_bits
[] = {
366 DEFINE_BIT(BRW_NEW_FS_PROG_DATA
),
367 DEFINE_BIT(BRW_NEW_BLORP_BLIT_PROG_DATA
),
368 DEFINE_BIT(BRW_NEW_SF_PROG_DATA
),
369 DEFINE_BIT(BRW_NEW_VS_PROG_DATA
),
370 DEFINE_BIT(BRW_NEW_FF_GS_PROG_DATA
),
371 DEFINE_BIT(BRW_NEW_GS_PROG_DATA
),
372 DEFINE_BIT(BRW_NEW_TCS_PROG_DATA
),
373 DEFINE_BIT(BRW_NEW_TES_PROG_DATA
),
374 DEFINE_BIT(BRW_NEW_CLIP_PROG_DATA
),
375 DEFINE_BIT(BRW_NEW_CS_PROG_DATA
),
376 DEFINE_BIT(BRW_NEW_URB_FENCE
),
377 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
378 DEFINE_BIT(BRW_NEW_GEOMETRY_PROGRAM
),
379 DEFINE_BIT(BRW_NEW_TESS_PROGRAMS
),
380 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
381 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
382 DEFINE_BIT(BRW_NEW_PATCH_PRIMITIVE
),
383 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
384 DEFINE_BIT(BRW_NEW_CONTEXT
),
385 DEFINE_BIT(BRW_NEW_PSP
),
386 DEFINE_BIT(BRW_NEW_SURFACES
),
387 DEFINE_BIT(BRW_NEW_BINDING_TABLE_POINTERS
),
388 DEFINE_BIT(BRW_NEW_INDICES
),
389 DEFINE_BIT(BRW_NEW_VERTICES
),
390 DEFINE_BIT(BRW_NEW_DEFAULT_TESS_LEVELS
),
391 DEFINE_BIT(BRW_NEW_BATCH
),
392 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
393 DEFINE_BIT(BRW_NEW_VS_CONSTBUF
),
394 DEFINE_BIT(BRW_NEW_TCS_CONSTBUF
),
395 DEFINE_BIT(BRW_NEW_TES_CONSTBUF
),
396 DEFINE_BIT(BRW_NEW_GS_CONSTBUF
),
397 DEFINE_BIT(BRW_NEW_PROGRAM_CACHE
),
398 DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS
),
399 DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT
),
400 DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK
),
401 DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD
),
402 DEFINE_BIT(BRW_NEW_STATS_WM
),
403 DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER
),
404 DEFINE_BIT(BRW_NEW_IMAGE_UNITS
),
405 DEFINE_BIT(BRW_NEW_META_IN_PROGRESS
),
406 DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION
),
407 DEFINE_BIT(BRW_NEW_NUM_SAMPLES
),
408 DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER
),
409 DEFINE_BIT(BRW_NEW_GEN4_UNIT_STATE
),
410 DEFINE_BIT(BRW_NEW_CC_VP
),
411 DEFINE_BIT(BRW_NEW_SF_VP
),
412 DEFINE_BIT(BRW_NEW_CLIP_VP
),
413 DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE
),
414 DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS
),
415 DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM
),
416 DEFINE_BIT(BRW_NEW_CS_WORK_GROUPS
),
417 DEFINE_BIT(BRW_NEW_URB_SIZE
),
418 DEFINE_BIT(BRW_NEW_CC_STATE
),
419 DEFINE_BIT(BRW_NEW_BLORP
),
420 DEFINE_BIT(BRW_NEW_VIEWPORT_COUNT
),
421 DEFINE_BIT(BRW_NEW_CONSERVATIVE_RASTERIZATION
),
422 DEFINE_BIT(BRW_NEW_DRAW_CALL
),
423 DEFINE_BIT(BRW_NEW_AUX_STATE
),
428 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, uint64_t bits
)
430 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
431 if (bit_map
[i
].bit
& bits
)
437 brw_print_dirty_count(struct dirty_bit_map
*bit_map
)
439 for (int i
= 0; bit_map
[i
].bit
!= 0; i
++) {
440 if (bit_map
[i
].count
> 1) {
441 fprintf(stderr
, "0x%016"PRIx64
": %12d (%s)\n",
442 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
448 brw_upload_tess_programs(struct brw_context
*brw
)
450 if (brw
->programs
[MESA_SHADER_TESS_EVAL
]) {
451 brw_upload_tcs_prog(brw
);
452 brw_upload_tes_prog(brw
);
454 brw
->tcs
.base
.prog_data
= NULL
;
455 brw
->tes
.base
.prog_data
= NULL
;
460 brw_upload_programs(struct brw_context
*brw
,
461 enum brw_pipeline pipeline
)
463 struct gl_context
*ctx
= &brw
->ctx
;
464 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
466 if (pipeline
== BRW_RENDER_PIPELINE
) {
467 brw_upload_vs_prog(brw
);
468 brw_upload_tess_programs(brw
);
470 if (brw
->programs
[MESA_SHADER_GEOMETRY
]) {
471 brw_upload_gs_prog(brw
);
473 brw
->gs
.base
.prog_data
= NULL
;
474 if (devinfo
->gen
< 7)
475 brw_upload_ff_gs_prog(brw
);
478 /* Update the VUE map for data exiting the GS stage of the pipeline.
479 * This comes from the last enabled shader stage.
481 GLbitfield64 old_slots
= brw
->vue_map_geom_out
.slots_valid
;
482 bool old_separate
= brw
->vue_map_geom_out
.separate
;
483 struct brw_vue_prog_data
*vue_prog_data
;
484 if (brw
->programs
[MESA_SHADER_GEOMETRY
])
485 vue_prog_data
= brw_vue_prog_data(brw
->gs
.base
.prog_data
);
486 else if (brw
->programs
[MESA_SHADER_TESS_EVAL
])
487 vue_prog_data
= brw_vue_prog_data(brw
->tes
.base
.prog_data
);
489 vue_prog_data
= brw_vue_prog_data(brw
->vs
.base
.prog_data
);
491 brw
->vue_map_geom_out
= vue_prog_data
->vue_map
;
493 /* If the layout has changed, signal BRW_NEW_VUE_MAP_GEOM_OUT. */
494 if (old_slots
!= brw
->vue_map_geom_out
.slots_valid
||
495 old_separate
!= brw
->vue_map_geom_out
.separate
)
496 brw
->ctx
.NewDriverState
|= BRW_NEW_VUE_MAP_GEOM_OUT
;
498 if ((old_slots
^ brw
->vue_map_geom_out
.slots_valid
) &
499 VARYING_BIT_VIEWPORT
) {
500 ctx
->NewDriverState
|= BRW_NEW_VIEWPORT_COUNT
;
501 brw
->clip
.viewport_count
=
502 (brw
->vue_map_geom_out
.slots_valid
& VARYING_BIT_VIEWPORT
) ?
503 ctx
->Const
.MaxViewports
: 1;
506 brw_upload_wm_prog(brw
);
508 if (devinfo
->gen
< 6) {
509 brw_upload_clip_prog(brw
);
510 brw_upload_sf_prog(brw
);
513 brw_disk_cache_write_render_programs(brw
);
514 } else if (pipeline
== BRW_COMPUTE_PIPELINE
) {
515 brw_upload_cs_prog(brw
);
516 brw_disk_cache_write_compute_program(brw
);
521 merge_ctx_state(struct brw_context
*brw
,
522 struct brw_state_flags
*state
)
524 state
->mesa
|= brw
->NewGLState
;
525 state
->brw
|= brw
->ctx
.NewDriverState
;
528 static ALWAYS_INLINE
void
529 check_and_emit_atom(struct brw_context
*brw
,
530 struct brw_state_flags
*state
,
531 const struct brw_tracked_state
*atom
)
533 if (check_state(state
, &atom
->dirty
)) {
535 merge_ctx_state(brw
, state
);
540 brw_upload_pipeline_state(struct brw_context
*brw
,
541 enum brw_pipeline pipeline
)
543 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
544 struct gl_context
*ctx
= &brw
->ctx
;
546 static int dirty_count
= 0;
547 struct brw_state_flags state
= brw
->state
.pipelines
[pipeline
];
548 const unsigned fb_samples
=
549 MAX2(_mesa_geometric_samples(ctx
->DrawBuffer
), 1);
551 brw_select_pipeline(brw
, pipeline
);
553 if (unlikely(INTEL_DEBUG
& DEBUG_REEMIT
)) {
554 /* Always re-emit all state. */
555 brw
->NewGLState
= ~0;
556 ctx
->NewDriverState
= ~0ull;
559 if (pipeline
== BRW_RENDER_PIPELINE
) {
560 if (brw
->programs
[MESA_SHADER_FRAGMENT
] !=
561 ctx
->FragmentProgram
._Current
) {
562 brw
->programs
[MESA_SHADER_FRAGMENT
] = ctx
->FragmentProgram
._Current
;
563 brw
->ctx
.NewDriverState
|= BRW_NEW_FRAGMENT_PROGRAM
;
566 if (brw
->programs
[MESA_SHADER_TESS_EVAL
] !=
567 ctx
->TessEvalProgram
._Current
) {
568 brw
->programs
[MESA_SHADER_TESS_EVAL
] = ctx
->TessEvalProgram
._Current
;
569 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
572 if (brw
->programs
[MESA_SHADER_TESS_CTRL
] !=
573 ctx
->TessCtrlProgram
._Current
) {
574 brw
->programs
[MESA_SHADER_TESS_CTRL
] = ctx
->TessCtrlProgram
._Current
;
575 brw
->ctx
.NewDriverState
|= BRW_NEW_TESS_PROGRAMS
;
578 if (brw
->programs
[MESA_SHADER_GEOMETRY
] !=
579 ctx
->GeometryProgram
._Current
) {
580 brw
->programs
[MESA_SHADER_GEOMETRY
] = ctx
->GeometryProgram
._Current
;
581 brw
->ctx
.NewDriverState
|= BRW_NEW_GEOMETRY_PROGRAM
;
584 if (brw
->programs
[MESA_SHADER_VERTEX
] != ctx
->VertexProgram
._Current
) {
585 brw
->programs
[MESA_SHADER_VERTEX
] = ctx
->VertexProgram
._Current
;
586 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTEX_PROGRAM
;
590 if (brw
->programs
[MESA_SHADER_COMPUTE
] != ctx
->ComputeProgram
._Current
) {
591 brw
->programs
[MESA_SHADER_COMPUTE
] = ctx
->ComputeProgram
._Current
;
592 brw
->ctx
.NewDriverState
|= BRW_NEW_COMPUTE_PROGRAM
;
595 if (brw
->meta_in_progress
!= _mesa_meta_in_progress(ctx
)) {
596 brw
->meta_in_progress
= _mesa_meta_in_progress(ctx
);
597 brw
->ctx
.NewDriverState
|= BRW_NEW_META_IN_PROGRESS
;
600 if (brw
->num_samples
!= fb_samples
) {
601 brw
->num_samples
= fb_samples
;
602 brw
->ctx
.NewDriverState
|= BRW_NEW_NUM_SAMPLES
;
605 /* Exit early if no state is flagged as dirty */
606 merge_ctx_state(brw
, &state
);
607 if ((state
.mesa
| state
.brw
) == 0)
610 /* Emit Sandybridge workaround flushes on every primitive, for safety. */
611 if (devinfo
->gen
== 6)
612 brw_emit_post_sync_nonzero_flush(brw
);
614 brw_upload_programs(brw
, pipeline
);
615 merge_ctx_state(brw
, &state
);
617 brw_upload_state_base_address(brw
);
619 const struct brw_tracked_state
*atoms
=
620 brw_get_pipeline_atoms(brw
, pipeline
);
621 const int num_atoms
= brw
->num_atoms
[pipeline
];
623 if (unlikely(INTEL_DEBUG
)) {
624 /* Debug version which enforces various sanity checks on the
625 * state flags which are generated and checked to help ensure
626 * state atoms are ordered correctly in the list.
628 struct brw_state_flags examined
, prev
;
629 memset(&examined
, 0, sizeof(examined
));
632 for (i
= 0; i
< num_atoms
; i
++) {
633 const struct brw_tracked_state
*atom
= &atoms
[i
];
634 struct brw_state_flags generated
;
636 check_and_emit_atom(brw
, &state
, atom
);
638 accumulate_state(&examined
, &atom
->dirty
);
640 /* generated = (prev ^ state)
641 * if (examined & generated)
644 xor_states(&generated
, &prev
, &state
);
645 assert(!check_state(&examined
, &generated
));
650 for (i
= 0; i
< num_atoms
; i
++) {
651 const struct brw_tracked_state
*atom
= &atoms
[i
];
653 check_and_emit_atom(brw
, &state
, atom
);
657 if (unlikely(INTEL_DEBUG
& DEBUG_STATE
)) {
658 STATIC_ASSERT(ARRAY_SIZE(brw_bits
) == BRW_NUM_STATE_BITS
+ 1);
660 brw_update_dirty_count(mesa_bits
, state
.mesa
);
661 brw_update_dirty_count(brw_bits
, state
.brw
);
662 if (dirty_count
++ % 1000 == 0) {
663 brw_print_dirty_count(mesa_bits
);
664 brw_print_dirty_count(brw_bits
);
665 fprintf(stderr
, "\n");
670 /***********************************************************************
673 void brw_upload_render_state(struct brw_context
*brw
)
675 brw_upload_pipeline_state(brw
, BRW_RENDER_PIPELINE
);
679 brw_pipeline_state_finished(struct brw_context
*brw
,
680 enum brw_pipeline pipeline
)
682 /* Save all dirty state into the other pipelines */
683 for (unsigned i
= 0; i
< BRW_NUM_PIPELINES
; i
++) {
685 brw
->state
.pipelines
[i
].mesa
|= brw
->NewGLState
;
686 brw
->state
.pipelines
[i
].brw
|= brw
->ctx
.NewDriverState
;
688 memset(&brw
->state
.pipelines
[i
], 0, sizeof(struct brw_state_flags
));
693 brw
->ctx
.NewDriverState
= 0ull;
697 * Clear dirty bits to account for the fact that the state emitted by
698 * brw_upload_render_state() has been committed to the hardware. This is a
699 * separate call from brw_upload_render_state() because it's possible that
700 * after the call to brw_upload_render_state(), we will discover that we've
701 * run out of aperture space, and need to rewind the batch buffer to the state
702 * it had before the brw_upload_render_state() call.
705 brw_render_state_finished(struct brw_context
*brw
)
707 brw_pipeline_state_finished(brw
, BRW_RENDER_PIPELINE
);
711 brw_upload_compute_state(struct brw_context
*brw
)
713 brw_upload_pipeline_state(brw
, BRW_COMPUTE_PIPELINE
);
717 brw_compute_state_finished(struct brw_context
*brw
)
719 brw_pipeline_state_finished(brw
, BRW_COMPUTE_PIPELINE
);