src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  67     * table upload must be last.
  68     */
  69    &brw_vs_pull_constants,
  70    &brw_wm_pull_constants,
  71    &brw_renderbuffer_surfaces,
  72    &brw_texture_surfaces,
  73    &brw_binding_table,
  74
  75    &brw_samplers,
  76
  77    /* These set up state for brw_psp_urb_cbs */
  78    &brw_wm_unit,
  79    &brw_sf_vp,
  80    &brw_sf_unit,
  81    &brw_vs_unit,                /* always required, enabled or not */
  82    &brw_clip_unit,
  83    &brw_gs_unit,
  84
  85    /* Command packets:
  86     */
  87    &brw_invariant_state,
  88    &brw_state_base_address,
  89
  90    &brw_binding_table_pointers,
  91    &brw_blend_constant_color,
  92
  93    &brw_depthbuffer,
  94
  95    &brw_polygon_stipple,
  96    &brw_polygon_stipple_offset,
  97
  98    &brw_line_stipple,
  99    &brw_aa_line_parameters,
 100
 101    &brw_psp_urb_cbs,
 102
 103    &brw_drawing_rect,
 104    &brw_indices,
 105    &brw_index_buffer,
 106    &brw_vertices,
 107
 108    &brw_constant_buffer
 109 };
 110
 111 static const struct brw_tracked_state *gen6_atoms[] =
 112 {
 113    &brw_check_fallback,
 114
 115    &brw_wm_input_sizes,
 116    &brw_vs_prog, /* must do before state base address */
 117    &brw_gs_prog, /* must do before state base address */
 118    &brw_wm_prog, /* must do before state base address */
 119
 120    &gen6_clip_vp,
 121    &gen6_sf_vp,
 122
 123    /* Command packets: */
 124    &brw_invariant_state,
 125
 126    /* must do before binding table pointers, cc state ptrs */
 127    &brw_state_base_address,
 128
 129    &brw_cc_vp,
 130    &gen6_viewport_state,        /* must do after *_vp stages */
 131
 132    &gen6_urb,
 133    &gen6_blend_state,           /* must do before cc unit */
 134    &gen6_color_calc_state,      /* must do before cc unit */
 135    &gen6_depth_stencil_state,   /* must do before cc unit */
 136    &gen6_cc_state_pointers,
 137
 138    &gen6_vs_push_constants, /* Before vs_state */
 139    &gen6_wm_push_constants, /* Before wm_state */
 140
 141    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 142     * table upload must be last.
 143     */
 144    &brw_vs_pull_constants,
 145    &brw_wm_pull_constants,
 146    &gen6_renderbuffer_surfaces,
 147    &brw_texture_surfaces,
 148    &gen6_sol_surface,
 149    &brw_binding_table,
 150
 151    &brw_samplers,
 152    &gen6_sampler_state,
 153
 154    &gen6_vs_state,
 155    &gen6_gs_state,
 156    &gen6_clip_state,
 157    &gen6_sf_state,
 158    &gen6_wm_state,
 159
 160    &gen6_scissor_state,
 161
 162    &gen6_binding_table_pointers,
 163
 164    &brw_depthbuffer,
 165
 166    &brw_polygon_stipple,
 167    &brw_polygon_stipple_offset,
 168
 169    &brw_line_stipple,
 170    &brw_aa_line_parameters,
 171
 172    &brw_drawing_rect,
 173
 174    &gen6_sol_indices,
 175    &brw_indices,
 176    &brw_index_buffer,
 177    &brw_vertices,
 178 };
 179
 180 const struct brw_tracked_state *gen7_atoms[] =
 181 {
 182    &brw_check_fallback,
 183
 184    &brw_wm_input_sizes,
 185    &brw_vs_prog,
 186    &brw_gs_prog,
 187    &brw_wm_prog,
 188
 189    /* Command packets: */
 190    &brw_invariant_state,
 191    &gen7_push_constant_alloc,
 192
 193    /* must do before binding table pointers, cc state ptrs */
 194    &brw_state_base_address,
 195
 196    &brw_cc_vp,
 197    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 198    &gen7_sf_clip_viewport,
 199
 200    &gen7_urb,
 201    &gen6_blend_state,           /* must do before cc unit */
 202    &gen6_color_calc_state,      /* must do before cc unit */
 203    &gen6_depth_stencil_state,   /* must do before cc unit */
 204    &gen7_blend_state_pointer,
 205    &gen7_cc_state_pointer,
 206    &gen7_depth_stencil_state_pointer,
 207
 208    &gen6_vs_push_constants, /* Before vs_state */
 209    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 210
 211    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 212     * table upload must be last.
 213     */
 214    &brw_vs_pull_constants,
 215    &brw_wm_pull_constants,
 216    &gen6_renderbuffer_surfaces,
 217    &brw_texture_surfaces,
 218    &brw_binding_table,
 219
 220    &gen7_samplers,
 221
 222    &gen7_disable_stages,
 223    &gen7_vs_state,
 224    &gen7_sol_state,
 225    &gen7_clip_state,
 226    &gen7_sbe_state,
 227    &gen7_sf_state,
 228    &gen7_wm_state,
 229    &gen7_ps_state,
 230
 231    &gen6_scissor_state,
 232
 233    &gen7_depthbuffer,
 234
 235    &brw_polygon_stipple,
 236    &brw_polygon_stipple_offset,
 237
 238    &brw_line_stipple,
 239    &brw_aa_line_parameters,
 240
 241    &brw_drawing_rect,
 242
 243    &brw_indices,
 244    &brw_index_buffer,
 245    &brw_vertices,
 246 };
 247
 248
 249 void brw_init_state( struct brw_context *brw )
 250 {
 251    const struct brw_tracked_state **atoms;
 252    int num_atoms;
 253
 254    brw_init_caches(brw);
 255
 256    if (brw->intel.gen >= 7) {
 257       atoms = gen7_atoms;
 258       num_atoms = ARRAY_SIZE(gen7_atoms);
 259    } else if (brw->intel.gen == 6) {
 260       atoms = gen6_atoms;
 261       num_atoms = ARRAY_SIZE(gen6_atoms);
 262    } else {
 263       atoms = gen4_atoms;
 264       num_atoms = ARRAY_SIZE(gen4_atoms);
 265    }
 266
 267    brw->atoms = atoms;
 268    brw->num_atoms = num_atoms;
 269
 270    while (num_atoms--) {
 271       assert((*atoms)->dirty.mesa |
 272              (*atoms)->dirty.brw |
 273              (*atoms)->dirty.cache);
 274       assert((*atoms)->emit);
 275       atoms++;
 276    }
 277 }
 278
 279
 280 void brw_destroy_state( struct brw_context *brw )
 281 {
 282    brw_destroy_caches(brw);
 283 }
 284
 285 /***********************************************************************
 286  */
 287
 288 static GLuint check_state( const struct brw_state_flags *a,
 289                            const struct brw_state_flags *b )
 290 {
 291    return ((a->mesa & b->mesa) |
 292            (a->brw & b->brw) |
 293            (a->cache & b->cache)) != 0;
 294 }
 295
 296 static void accumulate_state( struct brw_state_flags *a,
 297                               const struct brw_state_flags *b )
 298 {
 299    a->mesa |= b->mesa;
 300    a->brw |= b->brw;
 301    a->cache |= b->cache;
 302 }
 303
 304
 305 static void xor_states( struct brw_state_flags *result,
 306                              const struct brw_state_flags *a,
 307                               const struct brw_state_flags *b )
 308 {
 309    result->mesa = a->mesa ^ b->mesa;
 310    result->brw = a->brw ^ b->brw;
 311    result->cache = a->cache ^ b->cache;
 312 }
 313
 314 struct dirty_bit_map {
 315    uint32_t bit;
 316    char *name;
 317    uint32_t count;
 318 };
 319
 320 #define DEFINE_BIT(name) {name, #name, 0}
 321
 322 static struct dirty_bit_map mesa_bits[] = {
 323    DEFINE_BIT(_NEW_MODELVIEW),
 324    DEFINE_BIT(_NEW_PROJECTION),
 325    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 326    DEFINE_BIT(_NEW_COLOR),
 327    DEFINE_BIT(_NEW_DEPTH),
 328    DEFINE_BIT(_NEW_EVAL),
 329    DEFINE_BIT(_NEW_FOG),
 330    DEFINE_BIT(_NEW_HINT),
 331    DEFINE_BIT(_NEW_LIGHT),
 332    DEFINE_BIT(_NEW_LINE),
 333    DEFINE_BIT(_NEW_PIXEL),
 334    DEFINE_BIT(_NEW_POINT),
 335    DEFINE_BIT(_NEW_POLYGON),
 336    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 337    DEFINE_BIT(_NEW_SCISSOR),
 338    DEFINE_BIT(_NEW_STENCIL),
 339    DEFINE_BIT(_NEW_TEXTURE),
 340    DEFINE_BIT(_NEW_TRANSFORM),
 341    DEFINE_BIT(_NEW_VIEWPORT),
 342    DEFINE_BIT(_NEW_PACKUNPACK),
 343    DEFINE_BIT(_NEW_ARRAY),
 344    DEFINE_BIT(_NEW_RENDERMODE),
 345    DEFINE_BIT(_NEW_BUFFERS),
 346    DEFINE_BIT(_NEW_MULTISAMPLE),
 347    DEFINE_BIT(_NEW_TRACK_MATRIX),
 348    DEFINE_BIT(_NEW_PROGRAM),
 349    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 350    {0, 0, 0}
 351 };
 352
 353 static struct dirty_bit_map brw_bits[] = {
 354    DEFINE_BIT(BRW_NEW_URB_FENCE),
 355    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 356    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 357    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 358    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 359    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 360    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 361    DEFINE_BIT(BRW_NEW_CONTEXT),
 362    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 363    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 364    DEFINE_BIT(BRW_NEW_PSP),
 365    DEFINE_BIT(BRW_NEW_SURFACES),
 366    DEFINE_BIT(BRW_NEW_INDICES),
 367    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 368    DEFINE_BIT(BRW_NEW_VERTICES),
 369    DEFINE_BIT(BRW_NEW_BATCH),
 370    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 371    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 372    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 373    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 374    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 375    {0, 0, 0}
 376 };
 377
 378 static struct dirty_bit_map cache_bits[] = {
 379    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 380    DEFINE_BIT(CACHE_NEW_CC_VP),
 381    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 382    DEFINE_BIT(CACHE_NEW_WM_PROG),
 383    DEFINE_BIT(CACHE_NEW_SAMPLER),
 384    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 385    DEFINE_BIT(CACHE_NEW_SF_PROG),
 386    DEFINE_BIT(CACHE_NEW_SF_VP),
 387    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 388    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 389    DEFINE_BIT(CACHE_NEW_VS_PROG),
 390    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 391    DEFINE_BIT(CACHE_NEW_GS_PROG),
 392    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 393    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 394    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 395    {0, 0, 0}
 396 };
 397
 398
 399 static void
 400 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 401 {
 402    int i;
 403
 404    for (i = 0; i < 32; i++) {
 405       if (bit_map[i].bit == 0)
 406          return;
 407
 408       if (bit_map[i].bit & bits)
 409          bit_map[i].count++;
 410    }
 411 }
 412
 413 static void
 414 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 415 {
 416    int i;
 417
 418    for (i = 0; i < 32; i++) {
 419       if (bit_map[i].bit == 0)
 420          return;
 421
 422       fprintf(stderr, "0x%08x: %12d (%s)\n",
 423               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 424    }
 425 }
 426
 427 /***********************************************************************
 428  * Emit all state:
 429  */
 430 void brw_upload_state(struct brw_context *brw)
 431 {
 432    struct gl_context *ctx = &brw->intel.ctx;
 433    struct intel_context *intel = &brw->intel;
 434    struct brw_state_flags *state = &brw->state.dirty;
 435    int i;
 436    static int dirty_count = 0;
 437
 438    state->mesa |= brw->intel.NewGLState;
 439    brw->intel.NewGLState = 0;
 440
 441    if (brw->emit_state_always) {
 442       state->mesa |= ~0;
 443       state->brw |= ~0;
 444       state->cache |= ~0;
 445    }
 446
 447    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 448       brw->fragment_program = ctx->FragmentProgram._Current;
 449       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 450    }
 451
 452    if (brw->vertex_program != ctx->VertexProgram._Current) {
 453       brw->vertex_program = ctx->VertexProgram._Current;
 454       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 455    }
 456
 457    if ((state->mesa | state->cache | state->brw) == 0)
 458       return;
 459
 460    brw->intel.Fallback = false; /* boolean, not bitfield */
 461
 462    intel_check_front_buffer_rendering(intel);
 463
 464    if (unlikely(INTEL_DEBUG)) {
 465       /* Debug version which enforces various sanity checks on the
 466        * state flags which are generated and checked to help ensure
 467        * state atoms are ordered correctly in the list.
 468        */
 469       struct brw_state_flags examined, prev;
 470       memset(&examined, 0, sizeof(examined));
 471       prev = *state;
 472
 473       for (i = 0; i < brw->num_atoms; i++) {
 474          const struct brw_tracked_state *atom = brw->atoms[i];
 475          struct brw_state_flags generated;
 476
 477          if (brw->intel.Fallback)
 478             break;
 479
 480          if (check_state(state, &atom->dirty)) {
 481             atom->emit(brw);
 482          }
 483
 484          accumulate_state(&examined, &atom->dirty);
 485
 486          /* generated = (prev ^ state)
 487           * if (examined & generated)
 488           *     fail;
 489           */
 490          xor_states(&generated, &prev, state);
 491          assert(!check_state(&examined, &generated));
 492          prev = *state;
 493       }
 494    }
 495    else {
 496       for (i = 0; i < brw->num_atoms; i++) {
 497          const struct brw_tracked_state *atom = brw->atoms[i];
 498
 499          if (brw->intel.Fallback)
 500             break;
 501
 502          if (check_state(state, &atom->dirty)) {
 503             atom->emit(brw);
 504          }
 505       }
 506    }
 507
 508    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 509       brw_update_dirty_count(mesa_bits, state->mesa);
 510       brw_update_dirty_count(brw_bits, state->brw);
 511       brw_update_dirty_count(cache_bits, state->cache);
 512       if (dirty_count++ % 1000 == 0) {
 513          brw_print_dirty_count(mesa_bits, state->mesa);
 514          brw_print_dirty_count(brw_bits, state->brw);
 515          brw_print_dirty_count(cache_bits, state->cache);
 516          fprintf(stderr, "\n");
 517       }
 518    }
 519
 520    if (!brw->intel.Fallback)
 521       memset(state, 0, sizeof(*state));
 522 }