src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog,
  51    &brw_gs_prog,
  52    &brw_clip_prog,
  53    &brw_sf_prog,
  54    &brw_wm_prog,
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
  67    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
  68
  69    &brw_vs_surfaces,            /* must do before unit */
  70    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  71    &brw_wm_surfaces,            /* must do before samplers and unit */
  72    &brw_wm_binding_table,
  73    &brw_wm_samplers,
  74
  75    &brw_wm_unit,
  76    &brw_sf_vp,
  77    &brw_sf_unit,
  78    &brw_vs_unit,                /* always required, enabled or not */
  79    &brw_clip_unit,
  80    &brw_gs_unit,
  81
  82    /* Command packets:
  83     */
  84    &brw_invarient_state,
  85    &brw_state_base_address,
  86
  87    &brw_binding_table_pointers,
  88    &brw_blend_constant_color,
  89
  90    &brw_depthbuffer,
  91
  92    &brw_polygon_stipple,
  93    &brw_polygon_stipple_offset,
  94
  95    &brw_line_stipple,
  96    &brw_aa_line_parameters,
  97
  98    &brw_psp_urb_cbs,
  99
 100    &brw_drawing_rect,
 101    &brw_indices,
 102    &brw_index_buffer,
 103    &brw_vertices,
 104
 105    &brw_constant_buffer
 106 };
 107
 108 static const struct brw_tracked_state *gen6_atoms[] =
 109 {
 110    &brw_check_fallback,
 111
 112    &brw_wm_input_sizes,
 113    &brw_vs_prog,
 114    &brw_gs_prog,
 115    &brw_wm_prog,
 116
 117    &gen6_clip_vp,
 118    &gen6_sf_vp,
 119
 120    /* Command packets: */
 121    &brw_invarient_state,
 122
 123    /* must do before binding table pointers, cc state ptrs */
 124    &brw_state_base_address,
 125
 126    &brw_cc_vp,
 127    &gen6_viewport_state,        /* must do after *_vp stages */
 128
 129    &gen6_urb,
 130    &gen6_blend_state,           /* must do before cc unit */
 131    &gen6_color_calc_state,      /* must do before cc unit */
 132    &gen6_depth_stencil_state,   /* must do before cc unit */
 133    &gen6_cc_state_pointers,
 134
 135    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 136    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 137    &gen6_vs_constants, /* Before vs_state */
 138    &gen6_wm_constants, /* Before wm_state */
 139
 140    &brw_vs_surfaces,            /* must do before unit */
 141    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 142    &brw_wm_surfaces,            /* must do before samplers and unit */
 143    &brw_wm_binding_table,
 144
 145    &brw_wm_samplers,
 146    &gen6_sampler_state,
 147
 148    &gen6_vs_state,
 149    &gen6_gs_state,
 150    &gen6_clip_state,
 151    &gen6_sf_state,
 152    &gen6_wm_state,
 153
 154    &gen6_scissor_state,
 155
 156    &gen6_binding_table_pointers,
 157
 158    &brw_depthbuffer,
 159
 160    &brw_polygon_stipple,
 161    &brw_polygon_stipple_offset,
 162
 163    &brw_line_stipple,
 164    &brw_aa_line_parameters,
 165
 166    &brw_drawing_rect,
 167
 168    &brw_indices,
 169    &brw_index_buffer,
 170    &brw_vertices,
 171 };
 172
 173 const struct brw_tracked_state *gen7_atoms[] =
 174 {
 175    &brw_check_fallback,
 176
 177    &brw_wm_input_sizes,
 178    &brw_vs_prog,
 179    &brw_gs_prog,
 180    &brw_wm_prog,
 181
 182    &gen6_clip_vp,
 183    &gen6_sf_vp,
 184
 185    /* Command packets: */
 186    &brw_invarient_state,
 187
 188    /* must do before binding table pointers, cc state ptrs */
 189    &brw_state_base_address,
 190
 191    &brw_cc_vp,
 192    &gen6_viewport_state,        /* must do after *_vp stages */
 193
 194    &gen7_urb,
 195    &gen6_blend_state,           /* must do before cc unit */
 196    &gen6_color_calc_state,      /* must do before cc unit */
 197    &gen6_depth_stencil_state,   /* must do before cc unit */
 198    &gen7_blend_state_pointer,
 199    &gen7_cc_state_pointer,
 200    &gen7_depth_stencil_state_pointer,
 201
 202    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 203    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 204    &gen6_vs_constants, /* Before vs_state */
 205    &gen7_wm_constants, /* Before wm_state */
 206
 207    &brw_vs_surfaces,            /* must do before unit */
 208    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 209    &brw_wm_surfaces,            /* must do before samplers and unit */
 210    &brw_wm_binding_table,
 211
 212    &brw_wm_samplers,
 213    &gen6_sampler_state,
 214
 215    &gen6_vs_state,
 216    &gen6_gs_state,
 217    &gen7_clip_state,
 218    &gen7_sbe_state,
 219    &gen7_sf_state,
 220    &gen7_wm_state,
 221    &gen7_ps_state,
 222
 223    &gen6_scissor_state,
 224
 225    &gen6_binding_table_pointers,
 226
 227    &brw_depthbuffer,
 228
 229    &brw_polygon_stipple,
 230    &brw_polygon_stipple_offset,
 231
 232    &brw_line_stipple,
 233    &brw_aa_line_parameters,
 234
 235    &brw_drawing_rect,
 236
 237    &brw_indices,
 238    &brw_index_buffer,
 239    &brw_vertices,
 240 };
 241
 242
 243 void brw_init_state( struct brw_context *brw )
 244 {
 245    const struct brw_tracked_state **atoms;
 246    int num_atoms;
 247
 248    brw_init_caches(brw);
 249
 250    if (brw->intel.gen >= 7) {
 251       atoms = gen7_atoms;
 252       num_atoms = ARRAY_SIZE(gen7_atoms);
 253    } else if (brw->intel.gen == 6) {
 254       atoms = gen6_atoms;
 255       num_atoms = ARRAY_SIZE(gen6_atoms);
 256    } else {
 257       atoms = gen4_atoms;
 258       num_atoms = ARRAY_SIZE(gen4_atoms);
 259    }
 260
 261    while (num_atoms--) {
 262       assert((*atoms)->dirty.mesa |
 263              (*atoms)->dirty.brw |
 264              (*atoms)->dirty.cache);
 265
 266       if ((*atoms)->prepare)
 267          brw->prepare_atoms[brw->num_prepare_atoms++] = **atoms;
 268       if ((*atoms)->emit)
 269          brw->emit_atoms[brw->num_emit_atoms++] = **atoms;
 270       atoms++;
 271    }
 272    assert(brw->num_emit_atoms <= ARRAY_SIZE(brw->emit_atoms));
 273    assert(brw->num_prepare_atoms <= ARRAY_SIZE(brw->prepare_atoms));
 274 }
 275
 276
 277 void brw_destroy_state( struct brw_context *brw )
 278 {
 279    brw_destroy_caches(brw);
 280 }
 281
 282 /***********************************************************************
 283  */
 284
 285 static GLuint check_state( const struct brw_state_flags *a,
 286                            const struct brw_state_flags *b )
 287 {
 288    return ((a->mesa & b->mesa) |
 289            (a->brw & b->brw) |
 290            (a->cache & b->cache)) != 0;
 291 }
 292
 293 static void accumulate_state( struct brw_state_flags *a,
 294                               const struct brw_state_flags *b )
 295 {
 296    a->mesa |= b->mesa;
 297    a->brw |= b->brw;
 298    a->cache |= b->cache;
 299 }
 300
 301
 302 static void xor_states( struct brw_state_flags *result,
 303                              const struct brw_state_flags *a,
 304                               const struct brw_state_flags *b )
 305 {
 306    result->mesa = a->mesa ^ b->mesa;
 307    result->brw = a->brw ^ b->brw;
 308    result->cache = a->cache ^ b->cache;
 309 }
 310
 311 void
 312 brw_clear_validated_bos(struct brw_context *brw)
 313 {
 314    int i;
 315
 316    /* Clear the last round of validated bos */
 317    for (i = 0; i < brw->state.validated_bo_count; i++) {
 318       drm_intel_bo_unreference(brw->state.validated_bos[i]);
 319       brw->state.validated_bos[i] = NULL;
 320    }
 321    brw->state.validated_bo_count = 0;
 322 }
 323
 324 struct dirty_bit_map {
 325    uint32_t bit;
 326    char *name;
 327    uint32_t count;
 328 };
 329
 330 #define DEFINE_BIT(name) {name, #name, 0}
 331
 332 static struct dirty_bit_map mesa_bits[] = {
 333    DEFINE_BIT(_NEW_MODELVIEW),
 334    DEFINE_BIT(_NEW_PROJECTION),
 335    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 336    DEFINE_BIT(_NEW_COLOR),
 337    DEFINE_BIT(_NEW_DEPTH),
 338    DEFINE_BIT(_NEW_EVAL),
 339    DEFINE_BIT(_NEW_FOG),
 340    DEFINE_BIT(_NEW_HINT),
 341    DEFINE_BIT(_NEW_LIGHT),
 342    DEFINE_BIT(_NEW_LINE),
 343    DEFINE_BIT(_NEW_PIXEL),
 344    DEFINE_BIT(_NEW_POINT),
 345    DEFINE_BIT(_NEW_POLYGON),
 346    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 347    DEFINE_BIT(_NEW_SCISSOR),
 348    DEFINE_BIT(_NEW_STENCIL),
 349    DEFINE_BIT(_NEW_TEXTURE),
 350    DEFINE_BIT(_NEW_TRANSFORM),
 351    DEFINE_BIT(_NEW_VIEWPORT),
 352    DEFINE_BIT(_NEW_PACKUNPACK),
 353    DEFINE_BIT(_NEW_ARRAY),
 354    DEFINE_BIT(_NEW_RENDERMODE),
 355    DEFINE_BIT(_NEW_BUFFERS),
 356    DEFINE_BIT(_NEW_MULTISAMPLE),
 357    DEFINE_BIT(_NEW_TRACK_MATRIX),
 358    DEFINE_BIT(_NEW_PROGRAM),
 359    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 360    {0, 0, 0}
 361 };
 362
 363 static struct dirty_bit_map brw_bits[] = {
 364    DEFINE_BIT(BRW_NEW_URB_FENCE),
 365    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 366    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 367    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 368    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 369    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 370    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 371    DEFINE_BIT(BRW_NEW_CONTEXT),
 372    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 373    DEFINE_BIT(BRW_NEW_PSP),
 374    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 375    DEFINE_BIT(BRW_NEW_BINDING_TABLE),
 376    DEFINE_BIT(BRW_NEW_INDICES),
 377    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 378    DEFINE_BIT(BRW_NEW_VERTICES),
 379    DEFINE_BIT(BRW_NEW_BATCH),
 380    DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
 381    DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
 382    DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
 383    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 384    DEFINE_BIT(BRW_NEW_WM_CONSTBUF),
 385    {0, 0, 0}
 386 };
 387
 388 static struct dirty_bit_map cache_bits[] = {
 389    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 390    DEFINE_BIT(CACHE_NEW_CC_VP),
 391    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 392    DEFINE_BIT(CACHE_NEW_WM_PROG),
 393    DEFINE_BIT(CACHE_NEW_SAMPLER),
 394    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 395    DEFINE_BIT(CACHE_NEW_SF_PROG),
 396    DEFINE_BIT(CACHE_NEW_SF_VP),
 397    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 398    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 399    DEFINE_BIT(CACHE_NEW_VS_PROG),
 400    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 401    DEFINE_BIT(CACHE_NEW_GS_PROG),
 402    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 403    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 404    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 405    {0, 0, 0}
 406 };
 407
 408
 409 static void
 410 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 411 {
 412    int i;
 413
 414    for (i = 0; i < 32; i++) {
 415       if (bit_map[i].bit == 0)
 416          return;
 417
 418       if (bit_map[i].bit & bits)
 419          bit_map[i].count++;
 420    }
 421 }
 422
 423 static void
 424 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 425 {
 426    int i;
 427
 428    for (i = 0; i < 32; i++) {
 429       if (bit_map[i].bit == 0)
 430          return;
 431
 432       fprintf(stderr, "0x%08x: %12d (%s)\n",
 433               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 434    }
 435 }
 436
 437 /***********************************************************************
 438  * Emit all state:
 439  */
 440 void brw_validate_state( struct brw_context *brw )
 441 {
 442    struct gl_context *ctx = &brw->intel.ctx;
 443    struct intel_context *intel = &brw->intel;
 444    struct brw_state_flags *state = &brw->state.dirty;
 445    const struct brw_tracked_state *atoms = brw->prepare_atoms;
 446    int num_atoms = brw->num_prepare_atoms;
 447    GLuint i;
 448
 449    brw_clear_validated_bos(brw);
 450
 451    state->mesa |= brw->intel.NewGLState;
 452    brw->intel.NewGLState = 0;
 453
 454    brw_add_validated_bo(brw, intel->batch.bo);
 455
 456    if (brw->emit_state_always) {
 457       state->mesa |= ~0;
 458       state->brw |= ~0;
 459       state->cache |= ~0;
 460    }
 461
 462    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 463       brw->fragment_program = ctx->FragmentProgram._Current;
 464       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 465    }
 466
 467    if (brw->vertex_program != ctx->VertexProgram._Current) {
 468       brw->vertex_program = ctx->VertexProgram._Current;
 469       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 470    }
 471
 472    if ((state->mesa | state->cache | state->brw) == 0)
 473       return;
 474
 475    brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
 476
 477    /* do prepare stage for all atoms */
 478    for (i = 0; i < num_atoms; i++) {
 479       const struct brw_tracked_state *atom = &atoms[i];
 480
 481       if (check_state(state, &atom->dirty)) {
 482          atom->prepare(brw);
 483
 484          if (brw->intel.Fallback)
 485             break;
 486       }
 487    }
 488
 489    intel_check_front_buffer_rendering(intel);
 490
 491    /* Make sure that the textures which are referenced by the current
 492     * brw fragment program are actually present/valid.
 493     * If this fails, we can experience GPU lock-ups.
 494     */
 495    {
 496       const struct brw_fragment_program *fp;
 497       fp = brw_fragment_program_const(brw->fragment_program);
 498       if (fp) {
 499          assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
 500                 == fp->tex_units_used);
 501       }
 502    }
 503 }
 504
 505
 506 void brw_upload_state(struct brw_context *brw)
 507 {
 508    struct brw_state_flags *state = &brw->state.dirty;
 509    const struct brw_tracked_state *atoms = brw->emit_atoms;
 510    int num_atoms = brw->num_emit_atoms;
 511    int i;
 512    static int dirty_count = 0;
 513
 514    brw_clear_validated_bos(brw);
 515
 516    if (unlikely(INTEL_DEBUG)) {
 517       /* Debug version which enforces various sanity checks on the
 518        * state flags which are generated and checked to help ensure
 519        * state atoms are ordered correctly in the list.
 520        */
 521       struct brw_state_flags examined, prev;
 522       memset(&examined, 0, sizeof(examined));
 523       prev = *state;
 524
 525       for (i = 0; i < num_atoms; i++) {
 526          const struct brw_tracked_state *atom = &atoms[i];
 527          struct brw_state_flags generated;
 528
 529          if (brw->intel.Fallback)
 530             break;
 531
 532          if (check_state(state, &atom->dirty)) {
 533             atom->emit(brw);
 534          }
 535
 536          accumulate_state(&examined, &atom->dirty);
 537
 538          /* generated = (prev ^ state)
 539           * if (examined & generated)
 540           *     fail;
 541           */
 542          xor_states(&generated, &prev, state);
 543          assert(!check_state(&examined, &generated));
 544          prev = *state;
 545       }
 546    }
 547    else {
 548       for (i = 0; i < num_atoms; i++) {
 549          const struct brw_tracked_state *atom = &atoms[i];
 550
 551          if (brw->intel.Fallback)
 552             break;
 553
 554          if (check_state(state, &atom->dirty)) {
 555             atom->emit(brw);
 556          }
 557       }
 558    }
 559
 560    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 561       brw_update_dirty_count(mesa_bits, state->mesa);
 562       brw_update_dirty_count(brw_bits, state->brw);
 563       brw_update_dirty_count(cache_bits, state->cache);
 564       if (dirty_count++ % 1000 == 0) {
 565          brw_print_dirty_count(mesa_bits, state->mesa);
 566          brw_print_dirty_count(brw_bits, state->brw);
 567          brw_print_dirty_count(cache_bits, state->cache);
 568          fprintf(stderr, "\n");
 569       }
 570    }
 571
 572    if (!brw->intel.Fallback)
 573       memset(state, 0, sizeof(*state));
 574 }