src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  67     * table upload must be last.
  68     */
  69    &brw_vs_pull_constants,
  70    &brw_wm_pull_constants,
  71    &brw_renderbuffer_surfaces,
  72    &brw_texture_surfaces,
  73    &brw_binding_table,
  74
  75    &brw_samplers,
  76
  77    /* These set up state for brw_psp_urb_cbs */
  78    &brw_wm_unit,
  79    &brw_sf_vp,
  80    &brw_sf_unit,
  81    &brw_vs_unit,                /* always required, enabled or not */
  82    &brw_clip_unit,
  83    &brw_gs_unit,
  84
  85    /* Command packets:
  86     */
  87    &brw_invarient_state,
  88    &brw_state_base_address,
  89
  90    &brw_binding_table_pointers,
  91    &brw_blend_constant_color,
  92
  93    &brw_depthbuffer,
  94
  95    &brw_polygon_stipple,
  96    &brw_polygon_stipple_offset,
  97
  98    &brw_line_stipple,
  99    &brw_aa_line_parameters,
 100
 101    &brw_psp_urb_cbs,
 102
 103    &brw_drawing_rect,
 104    &brw_indices,
 105    &brw_index_buffer,
 106    &brw_vertices,
 107
 108    &brw_constant_buffer
 109 };
 110
 111 static const struct brw_tracked_state *gen6_atoms[] =
 112 {
 113    &brw_check_fallback,
 114
 115    &brw_wm_input_sizes,
 116    &brw_vs_prog, /* must do before state base address */
 117    &brw_gs_prog, /* must do before state base address */
 118    &brw_wm_prog, /* must do before state base address */
 119
 120    &gen6_clip_vp,
 121    &gen6_sf_vp,
 122
 123    /* Command packets: */
 124    &brw_invarient_state,
 125
 126    /* must do before binding table pointers, cc state ptrs */
 127    &brw_state_base_address,
 128
 129    &brw_cc_vp,
 130    &gen6_viewport_state,        /* must do after *_vp stages */
 131
 132    &gen6_urb,
 133    &gen6_blend_state,           /* must do before cc unit */
 134    &gen6_color_calc_state,      /* must do before cc unit */
 135    &gen6_depth_stencil_state,   /* must do before cc unit */
 136    &gen6_cc_state_pointers,
 137
 138    &gen6_vs_push_constants, /* Before vs_state */
 139    &gen6_wm_push_constants, /* Before wm_state */
 140
 141    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 142     * table upload must be last.
 143     */
 144    &brw_vs_pull_constants,
 145    &brw_wm_pull_constants,
 146    &gen6_renderbuffer_surfaces,
 147    &brw_texture_surfaces,
 148    &gen6_sol_surface,
 149    &brw_binding_table,
 150
 151    &brw_samplers,
 152    &gen6_sampler_state,
 153
 154    &gen6_vs_state,
 155    &gen6_gs_state,
 156    &gen6_clip_state,
 157    &gen6_sf_state,
 158    &gen6_wm_state,
 159
 160    &gen6_scissor_state,
 161
 162    &gen6_binding_table_pointers,
 163
 164    &brw_depthbuffer,
 165
 166    &brw_polygon_stipple,
 167    &brw_polygon_stipple_offset,
 168
 169    &brw_line_stipple,
 170    &brw_aa_line_parameters,
 171
 172    &brw_drawing_rect,
 173
 174    &brw_indices,
 175    &brw_index_buffer,
 176    &brw_vertices,
 177 };
 178
 179 const struct brw_tracked_state *gen7_atoms[] =
 180 {
 181    &brw_check_fallback,
 182
 183    &brw_wm_input_sizes,
 184    &brw_vs_prog,
 185    &brw_gs_prog,
 186    &brw_wm_prog,
 187
 188    /* Command packets: */
 189    &brw_invarient_state,
 190
 191    /* must do before binding table pointers, cc state ptrs */
 192    &brw_state_base_address,
 193
 194    &brw_cc_vp,
 195    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 196    &gen7_sf_clip_viewport,
 197
 198    &gen7_urb,
 199    &gen6_blend_state,           /* must do before cc unit */
 200    &gen6_color_calc_state,      /* must do before cc unit */
 201    &gen6_depth_stencil_state,   /* must do before cc unit */
 202    &gen7_blend_state_pointer,
 203    &gen7_cc_state_pointer,
 204    &gen7_depth_stencil_state_pointer,
 205
 206    &gen6_vs_push_constants, /* Before vs_state */
 207    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 208
 209    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 210     * table upload must be last.
 211     */
 212    &brw_vs_pull_constants,
 213    &brw_wm_pull_constants,
 214    &gen6_renderbuffer_surfaces,
 215    &brw_texture_surfaces,
 216    &brw_binding_table,
 217
 218    &gen7_samplers,
 219
 220    &gen7_disable_stages,
 221    &gen7_vs_state,
 222    &gen7_clip_state,
 223    &gen7_sbe_state,
 224    &gen7_sf_state,
 225    &gen7_wm_state,
 226    &gen7_ps_state,
 227
 228    &gen6_scissor_state,
 229
 230    &gen7_depthbuffer,
 231
 232    &brw_polygon_stipple,
 233    &brw_polygon_stipple_offset,
 234
 235    &brw_line_stipple,
 236    &brw_aa_line_parameters,
 237
 238    &brw_drawing_rect,
 239
 240    &brw_indices,
 241    &brw_index_buffer,
 242    &brw_vertices,
 243 };
 244
 245
 246 void brw_init_state( struct brw_context *brw )
 247 {
 248    const struct brw_tracked_state **atoms;
 249    int num_atoms;
 250
 251    brw_init_caches(brw);
 252
 253    if (brw->intel.gen >= 7) {
 254       atoms = gen7_atoms;
 255       num_atoms = ARRAY_SIZE(gen7_atoms);
 256    } else if (brw->intel.gen == 6) {
 257       atoms = gen6_atoms;
 258       num_atoms = ARRAY_SIZE(gen6_atoms);
 259    } else {
 260       atoms = gen4_atoms;
 261       num_atoms = ARRAY_SIZE(gen4_atoms);
 262    }
 263
 264    brw->atoms = atoms;
 265    brw->num_atoms = num_atoms;
 266
 267    while (num_atoms--) {
 268       assert((*atoms)->dirty.mesa |
 269              (*atoms)->dirty.brw |
 270              (*atoms)->dirty.cache);
 271       assert((*atoms)->emit);
 272       atoms++;
 273    }
 274 }
 275
 276
 277 void brw_destroy_state( struct brw_context *brw )
 278 {
 279    brw_destroy_caches(brw);
 280 }
 281
 282 /***********************************************************************
 283  */
 284
 285 static GLuint check_state( const struct brw_state_flags *a,
 286                            const struct brw_state_flags *b )
 287 {
 288    return ((a->mesa & b->mesa) |
 289            (a->brw & b->brw) |
 290            (a->cache & b->cache)) != 0;
 291 }
 292
 293 static void accumulate_state( struct brw_state_flags *a,
 294                               const struct brw_state_flags *b )
 295 {
 296    a->mesa |= b->mesa;
 297    a->brw |= b->brw;
 298    a->cache |= b->cache;
 299 }
 300
 301
 302 static void xor_states( struct brw_state_flags *result,
 303                              const struct brw_state_flags *a,
 304                               const struct brw_state_flags *b )
 305 {
 306    result->mesa = a->mesa ^ b->mesa;
 307    result->brw = a->brw ^ b->brw;
 308    result->cache = a->cache ^ b->cache;
 309 }
 310
 311 struct dirty_bit_map {
 312    uint32_t bit;
 313    char *name;
 314    uint32_t count;
 315 };
 316
 317 #define DEFINE_BIT(name) {name, #name, 0}
 318
 319 static struct dirty_bit_map mesa_bits[] = {
 320    DEFINE_BIT(_NEW_MODELVIEW),
 321    DEFINE_BIT(_NEW_PROJECTION),
 322    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 323    DEFINE_BIT(_NEW_COLOR),
 324    DEFINE_BIT(_NEW_DEPTH),
 325    DEFINE_BIT(_NEW_EVAL),
 326    DEFINE_BIT(_NEW_FOG),
 327    DEFINE_BIT(_NEW_HINT),
 328    DEFINE_BIT(_NEW_LIGHT),
 329    DEFINE_BIT(_NEW_LINE),
 330    DEFINE_BIT(_NEW_PIXEL),
 331    DEFINE_BIT(_NEW_POINT),
 332    DEFINE_BIT(_NEW_POLYGON),
 333    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 334    DEFINE_BIT(_NEW_SCISSOR),
 335    DEFINE_BIT(_NEW_STENCIL),
 336    DEFINE_BIT(_NEW_TEXTURE),
 337    DEFINE_BIT(_NEW_TRANSFORM),
 338    DEFINE_BIT(_NEW_VIEWPORT),
 339    DEFINE_BIT(_NEW_PACKUNPACK),
 340    DEFINE_BIT(_NEW_ARRAY),
 341    DEFINE_BIT(_NEW_RENDERMODE),
 342    DEFINE_BIT(_NEW_BUFFERS),
 343    DEFINE_BIT(_NEW_MULTISAMPLE),
 344    DEFINE_BIT(_NEW_TRACK_MATRIX),
 345    DEFINE_BIT(_NEW_PROGRAM),
 346    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 347    {0, 0, 0}
 348 };
 349
 350 static struct dirty_bit_map brw_bits[] = {
 351    DEFINE_BIT(BRW_NEW_URB_FENCE),
 352    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 353    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 354    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 355    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 356    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 357    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 358    DEFINE_BIT(BRW_NEW_CONTEXT),
 359    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 360    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 361    DEFINE_BIT(BRW_NEW_PSP),
 362    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 363    DEFINE_BIT(BRW_NEW_INDICES),
 364    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 365    DEFINE_BIT(BRW_NEW_VERTICES),
 366    DEFINE_BIT(BRW_NEW_BATCH),
 367    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 368    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 369    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 370    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 371    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 372    DEFINE_BIT(BRW_NEW_HIZ),
 373    {0, 0, 0}
 374 };
 375
 376 static struct dirty_bit_map cache_bits[] = {
 377    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 378    DEFINE_BIT(CACHE_NEW_CC_VP),
 379    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 380    DEFINE_BIT(CACHE_NEW_WM_PROG),
 381    DEFINE_BIT(CACHE_NEW_SAMPLER),
 382    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 383    DEFINE_BIT(CACHE_NEW_SF_PROG),
 384    DEFINE_BIT(CACHE_NEW_SF_VP),
 385    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 386    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 387    DEFINE_BIT(CACHE_NEW_VS_PROG),
 388    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 389    DEFINE_BIT(CACHE_NEW_GS_PROG),
 390    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 391    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 392    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 393    {0, 0, 0}
 394 };
 395
 396
 397 static void
 398 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 399 {
 400    int i;
 401
 402    for (i = 0; i < 32; i++) {
 403       if (bit_map[i].bit == 0)
 404          return;
 405
 406       if (bit_map[i].bit & bits)
 407          bit_map[i].count++;
 408    }
 409 }
 410
 411 static void
 412 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 413 {
 414    int i;
 415
 416    for (i = 0; i < 32; i++) {
 417       if (bit_map[i].bit == 0)
 418          return;
 419
 420       fprintf(stderr, "0x%08x: %12d (%s)\n",
 421               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 422    }
 423 }
 424
 425 /***********************************************************************
 426  * Emit all state:
 427  */
 428 void brw_upload_state(struct brw_context *brw)
 429 {
 430    struct gl_context *ctx = &brw->intel.ctx;
 431    struct intel_context *intel = &brw->intel;
 432    struct brw_state_flags *state = &brw->state.dirty;
 433    int i;
 434    static int dirty_count = 0;
 435
 436    state->mesa |= brw->intel.NewGLState;
 437    brw->intel.NewGLState = 0;
 438
 439    if (brw->emit_state_always) {
 440       state->mesa |= ~0;
 441       state->brw |= ~0;
 442       state->cache |= ~0;
 443    }
 444
 445    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 446       brw->fragment_program = ctx->FragmentProgram._Current;
 447       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 448    }
 449
 450    if (brw->vertex_program != ctx->VertexProgram._Current) {
 451       brw->vertex_program = ctx->VertexProgram._Current;
 452       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 453    }
 454
 455    if ((state->mesa | state->cache | state->brw) == 0)
 456       return;
 457
 458    brw->intel.Fallback = false; /* boolean, not bitfield */
 459
 460    intel_check_front_buffer_rendering(intel);
 461
 462    if (unlikely(INTEL_DEBUG)) {
 463       /* Debug version which enforces various sanity checks on the
 464        * state flags which are generated and checked to help ensure
 465        * state atoms are ordered correctly in the list.
 466        */
 467       struct brw_state_flags examined, prev;
 468       memset(&examined, 0, sizeof(examined));
 469       prev = *state;
 470
 471       for (i = 0; i < brw->num_atoms; i++) {
 472          const struct brw_tracked_state *atom = brw->atoms[i];
 473          struct brw_state_flags generated;
 474
 475          if (brw->intel.Fallback)
 476             break;
 477
 478          if (check_state(state, &atom->dirty)) {
 479             atom->emit(brw);
 480          }
 481
 482          accumulate_state(&examined, &atom->dirty);
 483
 484          /* generated = (prev ^ state)
 485           * if (examined & generated)
 486           *     fail;
 487           */
 488          xor_states(&generated, &prev, state);
 489          assert(!check_state(&examined, &generated));
 490          prev = *state;
 491       }
 492    }
 493    else {
 494       for (i = 0; i < brw->num_atoms; i++) {
 495          const struct brw_tracked_state *atom = brw->atoms[i];
 496
 497          if (brw->intel.Fallback)
 498             break;
 499
 500          if (check_state(state, &atom->dirty)) {
 501             atom->emit(brw);
 502          }
 503       }
 504    }
 505
 506    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 507       brw_update_dirty_count(mesa_bits, state->mesa);
 508       brw_update_dirty_count(brw_bits, state->brw);
 509       brw_update_dirty_count(cache_bits, state->cache);
 510       if (dirty_count++ % 1000 == 0) {
 511          brw_print_dirty_count(mesa_bits, state->mesa);
 512          brw_print_dirty_count(brw_bits, state->brw);
 513          brw_print_dirty_count(cache_bits, state->cache);
 514          fprintf(stderr, "\n");
 515       }
 516    }
 517
 518    if (!brw->intel.Fallback)
 519       memset(state, 0, sizeof(*state));
 520 }