src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_gs_prog, /* must do before state base address */
  44
  45    &brw_interpolation_map,
  46
  47    &brw_clip_prog, /* must do before state base address */
  48    &brw_sf_prog, /* must do before state base address */
  49    &brw_wm_prog, /* must do before state base address */
  50
  51    /* Once all the programs are done, we know how large urb entry
  52     * sizes need to be and can decide if we need to change the urb
  53     * layout.
  54     */
  55    &brw_curbe_offsets,
  56    &brw_recalculate_urb_fence,
  57
  58    &brw_cc_vp,
  59    &brw_cc_unit,
  60
  61    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  62     * table upload must be last.
  63     */
  64    &brw_vs_pull_constants,
  65    &brw_wm_pull_constants,
  66    &brw_renderbuffer_surfaces,
  67    &brw_texture_surfaces,
  68    &brw_vs_binding_table,
  69    &brw_wm_binding_table,
  70
  71    &brw_samplers,
  72
  73    /* These set up state for brw_psp_urb_cbs */
  74    &brw_wm_unit,
  75    &brw_sf_vp,
  76    &brw_sf_unit,
  77    &brw_vs_unit,                /* always required, enabled or not */
  78    &brw_clip_unit,
  79    &brw_gs_unit,
  80
  81    /* Command packets:
  82     */
  83    &brw_invariant_state,
  84    &brw_state_base_address,
  85
  86    &brw_binding_table_pointers,
  87    &brw_blend_constant_color,
  88
  89    &brw_depthbuffer,
  90
  91    &brw_polygon_stipple,
  92    &brw_polygon_stipple_offset,
  93
  94    &brw_line_stipple,
  95    &brw_aa_line_parameters,
  96
  97    &brw_psp_urb_cbs,
  98
  99    &brw_drawing_rect,
 100    &brw_indices,
 101    &brw_index_buffer,
 102    &brw_vertices,
 103
 104    &brw_constant_buffer
 105 };
 106
 107 static const struct brw_tracked_state *gen6_atoms[] =
 108 {
 109    &brw_vs_prog, /* must do before state base address */
 110    &brw_gs_prog, /* must do before state base address */
 111    &brw_wm_prog, /* must do before state base address */
 112
 113    &gen6_clip_vp,
 114    &gen6_sf_vp,
 115
 116    /* Command packets: */
 117
 118    /* must do before binding table pointers, cc state ptrs */
 119    &brw_state_base_address,
 120
 121    &brw_cc_vp,
 122    &gen6_viewport_state,        /* must do after *_vp stages */
 123
 124    &gen6_urb,
 125    &gen6_blend_state,           /* must do before cc unit */
 126    &gen6_color_calc_state,      /* must do before cc unit */
 127    &gen6_depth_stencil_state,   /* must do before cc unit */
 128
 129    &gen6_vs_push_constants, /* Before vs_state */
 130    &gen6_wm_push_constants, /* Before wm_state */
 131
 132    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 133     * table upload must be last.
 134     */
 135    &brw_vs_pull_constants,
 136    &brw_vs_ubo_surfaces,
 137    &brw_wm_pull_constants,
 138    &brw_wm_ubo_surfaces,
 139    &gen6_renderbuffer_surfaces,
 140    &brw_texture_surfaces,
 141    &gen6_sol_surface,
 142    &brw_vs_binding_table,
 143    &gen6_gs_binding_table,
 144    &brw_wm_binding_table,
 145
 146    &brw_samplers,
 147    &gen6_sampler_state,
 148    &gen6_multisample_state,
 149
 150    &gen6_vs_state,
 151    &gen6_gs_state,
 152    &gen6_clip_state,
 153    &gen6_sf_state,
 154    &gen6_wm_state,
 155
 156    &gen6_scissor_state,
 157
 158    &gen6_binding_table_pointers,
 159
 160    &brw_depthbuffer,
 161
 162    &brw_polygon_stipple,
 163    &brw_polygon_stipple_offset,
 164
 165    &brw_line_stipple,
 166    &brw_aa_line_parameters,
 167
 168    &brw_drawing_rect,
 169
 170    &brw_indices,
 171    &brw_index_buffer,
 172    &brw_vertices,
 173 };
 174
 175 static const struct brw_tracked_state *gen7_atoms[] =
 176 {
 177    &brw_vs_prog,
 178    &brw_wm_prog,
 179
 180    /* Command packets: */
 181
 182    /* must do before binding table pointers, cc state ptrs */
 183    &brw_state_base_address,
 184
 185    &brw_cc_vp,
 186    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 187    &gen7_sf_clip_viewport,
 188
 189    &gen7_urb,
 190    &gen6_blend_state,           /* must do before cc unit */
 191    &gen6_color_calc_state,      /* must do before cc unit */
 192    &gen6_depth_stencil_state,   /* must do before cc unit */
 193
 194    &gen6_vs_push_constants, /* Before vs_state */
 195    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 196
 197    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 198     * table upload must be last.
 199     */
 200    &brw_vs_pull_constants,
 201    &brw_vs_ubo_surfaces,
 202    &brw_wm_pull_constants,
 203    &brw_wm_ubo_surfaces,
 204    &gen6_renderbuffer_surfaces,
 205    &brw_texture_surfaces,
 206    &brw_vs_binding_table,
 207    &brw_wm_binding_table,
 208
 209    &gen7_samplers,
 210    &gen6_multisample_state,
 211
 212    &gen7_disable_stages,
 213    &gen7_vs_state,
 214    &gen7_sol_state,
 215    &gen7_clip_state,
 216    &gen7_sbe_state,
 217    &gen7_sf_state,
 218    &gen7_wm_state,
 219    &gen7_ps_state,
 220
 221    &gen6_scissor_state,
 222
 223    &gen7_depthbuffer,
 224
 225    &brw_polygon_stipple,
 226    &brw_polygon_stipple_offset,
 227
 228    &brw_line_stipple,
 229    &brw_aa_line_parameters,
 230
 231    &brw_drawing_rect,
 232
 233    &brw_indices,
 234    &brw_index_buffer,
 235    &brw_vertices,
 236
 237    &haswell_cut_index,
 238 };
 239
 240 static void
 241 brw_upload_initial_gpu_state(struct brw_context *brw)
 242 {
 243    /* On platforms with hardware contexts, we can set our initial GPU state
 244     * right away rather than doing it via state atoms.  This saves a small
 245     * amount of overhead on every draw call.
 246     */
 247    if (!brw->hw_ctx)
 248       return;
 249
 250    brw_upload_invariant_state(brw);
 251
 252    if (brw->gen >= 7) {
 253       gen7_allocate_push_constants(brw);
 254    }
 255 }
 256
 257 void brw_init_state( struct brw_context *brw )
 258 {
 259    const struct brw_tracked_state **atoms;
 260    int num_atoms;
 261
 262    brw_init_caches(brw);
 263
 264    if (brw->gen >= 7) {
 265       atoms = gen7_atoms;
 266       num_atoms = ARRAY_SIZE(gen7_atoms);
 267    } else if (brw->gen == 6) {
 268       atoms = gen6_atoms;
 269       num_atoms = ARRAY_SIZE(gen6_atoms);
 270    } else {
 271       atoms = gen4_atoms;
 272       num_atoms = ARRAY_SIZE(gen4_atoms);
 273    }
 274
 275    brw->atoms = atoms;
 276    brw->num_atoms = num_atoms;
 277
 278    while (num_atoms--) {
 279       assert((*atoms)->dirty.mesa |
 280              (*atoms)->dirty.brw |
 281              (*atoms)->dirty.cache);
 282       assert((*atoms)->emit);
 283       atoms++;
 284    }
 285
 286    brw_upload_initial_gpu_state(brw);
 287 }
 288
 289
 290 void brw_destroy_state( struct brw_context *brw )
 291 {
 292    brw_destroy_caches(brw);
 293 }
 294
 295 /***********************************************************************
 296  */
 297
 298 static bool
 299 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 300 {
 301    return ((a->mesa & b->mesa) |
 302            (a->brw & b->brw) |
 303            (a->cache & b->cache)) != 0;
 304 }
 305
 306 static void accumulate_state( struct brw_state_flags *a,
 307                               const struct brw_state_flags *b )
 308 {
 309    a->mesa |= b->mesa;
 310    a->brw |= b->brw;
 311    a->cache |= b->cache;
 312 }
 313
 314
 315 static void xor_states( struct brw_state_flags *result,
 316                              const struct brw_state_flags *a,
 317                               const struct brw_state_flags *b )
 318 {
 319    result->mesa = a->mesa ^ b->mesa;
 320    result->brw = a->brw ^ b->brw;
 321    result->cache = a->cache ^ b->cache;
 322 }
 323
 324 struct dirty_bit_map {
 325    uint32_t bit;
 326    char *name;
 327    uint32_t count;
 328 };
 329
 330 #define DEFINE_BIT(name) {name, #name, 0}
 331
 332 static struct dirty_bit_map mesa_bits[] = {
 333    DEFINE_BIT(_NEW_MODELVIEW),
 334    DEFINE_BIT(_NEW_PROJECTION),
 335    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 336    DEFINE_BIT(_NEW_COLOR),
 337    DEFINE_BIT(_NEW_DEPTH),
 338    DEFINE_BIT(_NEW_EVAL),
 339    DEFINE_BIT(_NEW_FOG),
 340    DEFINE_BIT(_NEW_HINT),
 341    DEFINE_BIT(_NEW_LIGHT),
 342    DEFINE_BIT(_NEW_LINE),
 343    DEFINE_BIT(_NEW_PIXEL),
 344    DEFINE_BIT(_NEW_POINT),
 345    DEFINE_BIT(_NEW_POLYGON),
 346    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 347    DEFINE_BIT(_NEW_SCISSOR),
 348    DEFINE_BIT(_NEW_STENCIL),
 349    DEFINE_BIT(_NEW_TEXTURE),
 350    DEFINE_BIT(_NEW_TRANSFORM),
 351    DEFINE_BIT(_NEW_VIEWPORT),
 352    DEFINE_BIT(_NEW_ARRAY),
 353    DEFINE_BIT(_NEW_RENDERMODE),
 354    DEFINE_BIT(_NEW_BUFFERS),
 355    DEFINE_BIT(_NEW_MULTISAMPLE),
 356    DEFINE_BIT(_NEW_TRACK_MATRIX),
 357    DEFINE_BIT(_NEW_PROGRAM),
 358    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 359    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 360    DEFINE_BIT(_NEW_FRAG_CLAMP),
 361    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 362    {0, 0, 0}
 363 };
 364
 365 static struct dirty_bit_map brw_bits[] = {
 366    DEFINE_BIT(BRW_NEW_URB_FENCE),
 367    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 368    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 369    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 370    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 371    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 372    DEFINE_BIT(BRW_NEW_CONTEXT),
 373    DEFINE_BIT(BRW_NEW_PSP),
 374    DEFINE_BIT(BRW_NEW_SURFACES),
 375    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 376    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 377    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 378    DEFINE_BIT(BRW_NEW_INDICES),
 379    DEFINE_BIT(BRW_NEW_VERTICES),
 380    DEFINE_BIT(BRW_NEW_BATCH),
 381    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 382    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 383    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 384    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 385    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 386    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 387    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 388    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 389    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 390    {0, 0, 0}
 391 };
 392
 393 static struct dirty_bit_map cache_bits[] = {
 394    DEFINE_BIT(CACHE_NEW_CC_VP),
 395    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 396    DEFINE_BIT(CACHE_NEW_WM_PROG),
 397    DEFINE_BIT(CACHE_NEW_SAMPLER),
 398    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 399    DEFINE_BIT(CACHE_NEW_SF_PROG),
 400    DEFINE_BIT(CACHE_NEW_SF_VP),
 401    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 402    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 403    DEFINE_BIT(CACHE_NEW_VS_PROG),
 404    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 405    DEFINE_BIT(CACHE_NEW_GS_PROG),
 406    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 407    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 408    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 409    {0, 0, 0}
 410 };
 411
 412
 413 static void
 414 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 415 {
 416    int i;
 417
 418    for (i = 0; i < 32; i++) {
 419       if (bit_map[i].bit == 0)
 420          return;
 421
 422       if (bit_map[i].bit & bits)
 423          bit_map[i].count++;
 424    }
 425 }
 426
 427 static void
 428 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 429 {
 430    int i;
 431
 432    for (i = 0; i < 32; i++) {
 433       if (bit_map[i].bit == 0)
 434          return;
 435
 436       fprintf(stderr, "0x%08x: %12d (%s)\n",
 437               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 438    }
 439 }
 440
 441 /***********************************************************************
 442  * Emit all state:
 443  */
 444 void brw_upload_state(struct brw_context *brw)
 445 {
 446    struct gl_context *ctx = &brw->ctx;
 447    struct brw_state_flags *state = &brw->state.dirty;
 448    int i;
 449    static int dirty_count = 0;
 450
 451    state->mesa |= brw->NewGLState;
 452    brw->NewGLState = 0;
 453
 454    state->brw |= ctx->NewDriverState;
 455    ctx->NewDriverState = 0;
 456
 457    if (brw->emit_state_always) {
 458       state->mesa |= ~0;
 459       state->brw |= ~0;
 460       state->cache |= ~0;
 461    }
 462
 463    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 464       brw->fragment_program = ctx->FragmentProgram._Current;
 465       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 466    }
 467
 468    if (brw->vertex_program != ctx->VertexProgram._Current) {
 469       brw->vertex_program = ctx->VertexProgram._Current;
 470       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 471    }
 472
 473    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 474       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 475       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 476    }
 477
 478    if ((state->mesa | state->cache | state->brw) == 0)
 479       return;
 480
 481    intel_check_front_buffer_rendering(brw);
 482
 483    if (unlikely(INTEL_DEBUG)) {
 484       /* Debug version which enforces various sanity checks on the
 485        * state flags which are generated and checked to help ensure
 486        * state atoms are ordered correctly in the list.
 487        */
 488       struct brw_state_flags examined, prev;
 489       memset(&examined, 0, sizeof(examined));
 490       prev = *state;
 491
 492       for (i = 0; i < brw->num_atoms; i++) {
 493          const struct brw_tracked_state *atom = brw->atoms[i];
 494          struct brw_state_flags generated;
 495
 496          if (check_state(state, &atom->dirty)) {
 497             atom->emit(brw);
 498          }
 499
 500          accumulate_state(&examined, &atom->dirty);
 501
 502          /* generated = (prev ^ state)
 503           * if (examined & generated)
 504           *     fail;
 505           */
 506          xor_states(&generated, &prev, state);
 507          assert(!check_state(&examined, &generated));
 508          prev = *state;
 509       }
 510    }
 511    else {
 512       for (i = 0; i < brw->num_atoms; i++) {
 513          const struct brw_tracked_state *atom = brw->atoms[i];
 514
 515          if (check_state(state, &atom->dirty)) {
 516             atom->emit(brw);
 517          }
 518       }
 519    }
 520
 521    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 522       brw_update_dirty_count(mesa_bits, state->mesa);
 523       brw_update_dirty_count(brw_bits, state->brw);
 524       brw_update_dirty_count(cache_bits, state->cache);
 525       if (dirty_count++ % 1000 == 0) {
 526          brw_print_dirty_count(mesa_bits);
 527          brw_print_dirty_count(brw_bits);
 528          brw_print_dirty_count(cache_bits);
 529          fprintf(stderr, "\n");
 530       }
 531    }
 532
 533    memset(state, 0, sizeof(*state));
 534 }