src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "drivers/common/meta.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_buffers.h"
  39
  40 static const struct brw_tracked_state *gen4_atoms[] =
  41 {
  42    &brw_vs_prog, /* must do before GS prog, state base address. */
  43    &brw_gs_prog, /* must do before state base address */
  44    &brw_clip_prog, /* must do before state base address */
  45    &brw_sf_prog, /* must do before state base address */
  46    &brw_wm_prog, /* must do before state base address */
  47
  48    /* Once all the programs are done, we know how large urb entry
  49     * sizes need to be and can decide if we need to change the urb
  50     * layout.
  51     */
  52    &brw_curbe_offsets,
  53    &brw_recalculate_urb_fence,
  54
  55    &brw_cc_vp,
  56    &brw_cc_unit,
  57
  58    /* Surface state setup.  Must come before the VS/WM unit.  The binding
  59     * table upload must be last.
  60     */
  61    &brw_vs_pull_constants,
  62    &brw_wm_pull_constants,
  63    &brw_renderbuffer_surfaces,
  64    &brw_texture_surfaces,
  65    &brw_vs_binding_table,
  66    &brw_wm_binding_table,
  67
  68    &brw_samplers,
  69
  70    /* These set up state for brw_psp_urb_cbs */
  71    &brw_wm_unit,
  72    &brw_sf_vp,
  73    &brw_sf_unit,
  74    &brw_vs_unit,                /* always required, enabled or not */
  75    &brw_clip_unit,
  76    &brw_gs_unit,
  77
  78    /* Command packets:
  79     */
  80    &brw_invariant_state,
  81    &brw_state_base_address,
  82
  83    &brw_binding_table_pointers,
  84    &brw_blend_constant_color,
  85
  86    &brw_depthbuffer,
  87
  88    &brw_polygon_stipple,
  89    &brw_polygon_stipple_offset,
  90
  91    &brw_line_stipple,
  92    &brw_aa_line_parameters,
  93
  94    &brw_psp_urb_cbs,
  95
  96    &brw_drawing_rect,
  97    &brw_indices,
  98    &brw_index_buffer,
  99    &brw_vertices,
 100
 101    &brw_constant_buffer
 102 };
 103
 104 static const struct brw_tracked_state *gen6_atoms[] =
 105 {
 106    &brw_vs_prog, /* must do before state base address */
 107    &brw_gs_prog, /* must do before state base address */
 108    &brw_wm_prog, /* must do before state base address */
 109
 110    &gen6_clip_vp,
 111    &gen6_sf_vp,
 112
 113    /* Command packets: */
 114
 115    /* must do before binding table pointers, cc state ptrs */
 116    &brw_state_base_address,
 117
 118    &brw_cc_vp,
 119    &gen6_viewport_state,        /* must do after *_vp stages */
 120
 121    &gen6_urb,
 122    &gen6_blend_state,           /* must do before cc unit */
 123    &gen6_color_calc_state,      /* must do before cc unit */
 124    &gen6_depth_stencil_state,   /* must do before cc unit */
 125
 126    &gen6_vs_push_constants, /* Before vs_state */
 127    &gen6_wm_push_constants, /* Before wm_state */
 128
 129    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 130     * table upload must be last.
 131     */
 132    &brw_vs_pull_constants,
 133    &brw_vs_ubo_surfaces,
 134    &brw_wm_pull_constants,
 135    &brw_wm_ubo_surfaces,
 136    &gen6_renderbuffer_surfaces,
 137    &brw_texture_surfaces,
 138    &gen6_sol_surface,
 139    &brw_vs_binding_table,
 140    &gen6_gs_binding_table,
 141    &brw_wm_binding_table,
 142
 143    &brw_samplers,
 144    &gen6_sampler_state,
 145    &gen6_multisample_state,
 146
 147    &gen6_vs_state,
 148    &gen6_gs_state,
 149    &gen6_clip_state,
 150    &gen6_sf_state,
 151    &gen6_wm_state,
 152
 153    &gen6_scissor_state,
 154
 155    &gen6_binding_table_pointers,
 156
 157    &brw_depthbuffer,
 158
 159    &brw_polygon_stipple,
 160    &brw_polygon_stipple_offset,
 161
 162    &brw_line_stipple,
 163    &brw_aa_line_parameters,
 164
 165    &brw_drawing_rect,
 166
 167    &brw_indices,
 168    &brw_index_buffer,
 169    &brw_vertices,
 170 };
 171
 172 static const struct brw_tracked_state *gen7_atoms[] =
 173 {
 174    &brw_vs_prog,
 175    &brw_wm_prog,
 176
 177    /* Command packets: */
 178
 179    /* must do before binding table pointers, cc state ptrs */
 180    &brw_state_base_address,
 181
 182    &brw_cc_vp,
 183    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 184    &gen7_sf_clip_viewport,
 185
 186    &gen7_urb,
 187    &gen6_blend_state,           /* must do before cc unit */
 188    &gen6_color_calc_state,      /* must do before cc unit */
 189    &gen6_depth_stencil_state,   /* must do before cc unit */
 190
 191    &gen6_vs_push_constants, /* Before vs_state */
 192    &gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 193
 194    /* Surface state setup.  Must come before the VS/WM unit.  The binding
 195     * table upload must be last.
 196     */
 197    &brw_vs_pull_constants,
 198    &brw_vs_ubo_surfaces,
 199    &brw_wm_pull_constants,
 200    &brw_wm_ubo_surfaces,
 201    &gen6_renderbuffer_surfaces,
 202    &brw_texture_surfaces,
 203    &brw_vs_binding_table,
 204    &brw_wm_binding_table,
 205
 206    &gen7_samplers,
 207    &gen6_multisample_state,
 208
 209    &gen7_disable_stages,
 210    &gen7_vs_state,
 211    &gen7_sol_state,
 212    &gen7_clip_state,
 213    &gen7_sbe_state,
 214    &gen7_sf_state,
 215    &gen7_wm_state,
 216    &gen7_ps_state,
 217
 218    &gen6_scissor_state,
 219
 220    &gen7_depthbuffer,
 221
 222    &brw_polygon_stipple,
 223    &brw_polygon_stipple_offset,
 224
 225    &brw_line_stipple,
 226    &brw_aa_line_parameters,
 227
 228    &brw_drawing_rect,
 229
 230    &brw_indices,
 231    &brw_index_buffer,
 232    &brw_vertices,
 233
 234    &haswell_cut_index,
 235 };
 236
 237 static void
 238 brw_upload_initial_gpu_state(struct brw_context *brw)
 239 {
 240    struct intel_context *intel = &brw->intel;
 241
 242    /* On platforms with hardware contexts, we can set our initial GPU state
 243     * right away rather than doing it via state atoms.  This saves a small
 244     * amount of overhead on every draw call.
 245     */
 246    if (!intel->hw_ctx)
 247       return;
 248
 249    brw_upload_invariant_state(brw);
 250
 251    if (intel->gen >= 7) {
 252       gen7_allocate_push_constants(brw);
 253    }
 254 }
 255
 256 void brw_init_state( struct brw_context *brw )
 257 {
 258    const struct brw_tracked_state **atoms;
 259    int num_atoms;
 260
 261    brw_init_caches(brw);
 262
 263    if (brw->intel.gen >= 7) {
 264       atoms = gen7_atoms;
 265       num_atoms = ARRAY_SIZE(gen7_atoms);
 266    } else if (brw->intel.gen == 6) {
 267       atoms = gen6_atoms;
 268       num_atoms = ARRAY_SIZE(gen6_atoms);
 269    } else {
 270       atoms = gen4_atoms;
 271       num_atoms = ARRAY_SIZE(gen4_atoms);
 272    }
 273
 274    brw->atoms = atoms;
 275    brw->num_atoms = num_atoms;
 276
 277    while (num_atoms--) {
 278       assert((*atoms)->dirty.mesa |
 279              (*atoms)->dirty.brw |
 280              (*atoms)->dirty.cache);
 281       assert((*atoms)->emit);
 282       atoms++;
 283    }
 284
 285    brw_upload_initial_gpu_state(brw);
 286 }
 287
 288
 289 void brw_destroy_state( struct brw_context *brw )
 290 {
 291    brw_destroy_caches(brw);
 292 }
 293
 294 /***********************************************************************
 295  */
 296
 297 static bool
 298 check_state(const struct brw_state_flags *a, const struct brw_state_flags *b)
 299 {
 300    return ((a->mesa & b->mesa) |
 301            (a->brw & b->brw) |
 302            (a->cache & b->cache)) != 0;
 303 }
 304
 305 static void accumulate_state( struct brw_state_flags *a,
 306                               const struct brw_state_flags *b )
 307 {
 308    a->mesa |= b->mesa;
 309    a->brw |= b->brw;
 310    a->cache |= b->cache;
 311 }
 312
 313
 314 static void xor_states( struct brw_state_flags *result,
 315                              const struct brw_state_flags *a,
 316                               const struct brw_state_flags *b )
 317 {
 318    result->mesa = a->mesa ^ b->mesa;
 319    result->brw = a->brw ^ b->brw;
 320    result->cache = a->cache ^ b->cache;
 321 }
 322
 323 struct dirty_bit_map {
 324    uint32_t bit;
 325    char *name;
 326    uint32_t count;
 327 };
 328
 329 #define DEFINE_BIT(name) {name, #name, 0}
 330
 331 static struct dirty_bit_map mesa_bits[] = {
 332    DEFINE_BIT(_NEW_MODELVIEW),
 333    DEFINE_BIT(_NEW_PROJECTION),
 334    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 335    DEFINE_BIT(_NEW_COLOR),
 336    DEFINE_BIT(_NEW_DEPTH),
 337    DEFINE_BIT(_NEW_EVAL),
 338    DEFINE_BIT(_NEW_FOG),
 339    DEFINE_BIT(_NEW_HINT),
 340    DEFINE_BIT(_NEW_LIGHT),
 341    DEFINE_BIT(_NEW_LINE),
 342    DEFINE_BIT(_NEW_PIXEL),
 343    DEFINE_BIT(_NEW_POINT),
 344    DEFINE_BIT(_NEW_POLYGON),
 345    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 346    DEFINE_BIT(_NEW_SCISSOR),
 347    DEFINE_BIT(_NEW_STENCIL),
 348    DEFINE_BIT(_NEW_TEXTURE),
 349    DEFINE_BIT(_NEW_TRANSFORM),
 350    DEFINE_BIT(_NEW_VIEWPORT),
 351    DEFINE_BIT(_NEW_ARRAY),
 352    DEFINE_BIT(_NEW_RENDERMODE),
 353    DEFINE_BIT(_NEW_BUFFERS),
 354    DEFINE_BIT(_NEW_MULTISAMPLE),
 355    DEFINE_BIT(_NEW_TRACK_MATRIX),
 356    DEFINE_BIT(_NEW_PROGRAM),
 357    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 358    DEFINE_BIT(_NEW_BUFFER_OBJECT),
 359    DEFINE_BIT(_NEW_FRAG_CLAMP),
 360    DEFINE_BIT(_NEW_VARYING_VP_INPUTS),
 361    {0, 0, 0}
 362 };
 363
 364 static struct dirty_bit_map brw_bits[] = {
 365    DEFINE_BIT(BRW_NEW_URB_FENCE),
 366    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 367    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 368    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 369    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 370    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 371    DEFINE_BIT(BRW_NEW_CONTEXT),
 372    DEFINE_BIT(BRW_NEW_PSP),
 373    DEFINE_BIT(BRW_NEW_SURFACES),
 374    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 375    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 376    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 377    DEFINE_BIT(BRW_NEW_INDICES),
 378    DEFINE_BIT(BRW_NEW_VERTICES),
 379    DEFINE_BIT(BRW_NEW_BATCH),
 380    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 381    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 382    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 383    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 384    DEFINE_BIT(BRW_NEW_VUE_MAP_GEOM_OUT),
 385    DEFINE_BIT(BRW_NEW_TRANSFORM_FEEDBACK),
 386    DEFINE_BIT(BRW_NEW_RASTERIZER_DISCARD),
 387    DEFINE_BIT(BRW_NEW_UNIFORM_BUFFER),
 388    DEFINE_BIT(BRW_NEW_META_IN_PROGRESS),
 389    {0, 0, 0}
 390 };
 391
 392 static struct dirty_bit_map cache_bits[] = {
 393    DEFINE_BIT(CACHE_NEW_CC_VP),
 394    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 395    DEFINE_BIT(CACHE_NEW_WM_PROG),
 396    DEFINE_BIT(CACHE_NEW_SAMPLER),
 397    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 398    DEFINE_BIT(CACHE_NEW_SF_PROG),
 399    DEFINE_BIT(CACHE_NEW_SF_VP),
 400    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 401    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 402    DEFINE_BIT(CACHE_NEW_VS_PROG),
 403    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 404    DEFINE_BIT(CACHE_NEW_GS_PROG),
 405    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 406    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 407    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 408    {0, 0, 0}
 409 };
 410
 411
 412 static void
 413 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 414 {
 415    int i;
 416
 417    for (i = 0; i < 32; i++) {
 418       if (bit_map[i].bit == 0)
 419          return;
 420
 421       if (bit_map[i].bit & bits)
 422          bit_map[i].count++;
 423    }
 424 }
 425
 426 static void
 427 brw_print_dirty_count(struct dirty_bit_map *bit_map)
 428 {
 429    int i;
 430
 431    for (i = 0; i < 32; i++) {
 432       if (bit_map[i].bit == 0)
 433          return;
 434
 435       fprintf(stderr, "0x%08x: %12d (%s)\n",
 436               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 437    }
 438 }
 439
 440 /***********************************************************************
 441  * Emit all state:
 442  */
 443 void brw_upload_state(struct brw_context *brw)
 444 {
 445    struct gl_context *ctx = &brw->intel.ctx;
 446    struct intel_context *intel = &brw->intel;
 447    struct brw_state_flags *state = &brw->state.dirty;
 448    int i;
 449    static int dirty_count = 0;
 450
 451    state->mesa |= brw->intel.NewGLState;
 452    brw->intel.NewGLState = 0;
 453
 454    state->brw |= ctx->NewDriverState;
 455    ctx->NewDriverState = 0;
 456
 457    if (brw->emit_state_always) {
 458       state->mesa |= ~0;
 459       state->brw |= ~0;
 460       state->cache |= ~0;
 461    }
 462
 463    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 464       brw->fragment_program = ctx->FragmentProgram._Current;
 465       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 466    }
 467
 468    if (brw->vertex_program != ctx->VertexProgram._Current) {
 469       brw->vertex_program = ctx->VertexProgram._Current;
 470       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 471    }
 472
 473    if (brw->meta_in_progress != _mesa_meta_in_progress(ctx)) {
 474       brw->meta_in_progress = _mesa_meta_in_progress(ctx);
 475       brw->state.dirty.brw |= BRW_NEW_META_IN_PROGRESS;
 476    }
 477
 478    if ((state->mesa | state->cache | state->brw) == 0)
 479       return;
 480
 481    intel_check_front_buffer_rendering(intel);
 482
 483    if (unlikely(INTEL_DEBUG)) {
 484       /* Debug version which enforces various sanity checks on the
 485        * state flags which are generated and checked to help ensure
 486        * state atoms are ordered correctly in the list.
 487        */
 488       struct brw_state_flags examined, prev;
 489       memset(&examined, 0, sizeof(examined));
 490       prev = *state;
 491
 492       for (i = 0; i < brw->num_atoms; i++) {
 493          const struct brw_tracked_state *atom = brw->atoms[i];
 494          struct brw_state_flags generated;
 495
 496          if (check_state(state, &atom->dirty)) {
 497             atom->emit(brw);
 498          }
 499
 500          accumulate_state(&examined, &atom->dirty);
 501
 502          /* generated = (prev ^ state)
 503           * if (examined & generated)
 504           *     fail;
 505           */
 506          xor_states(&generated, &prev, state);
 507          assert(!check_state(&examined, &generated));
 508          prev = *state;
 509       }
 510    }
 511    else {
 512       for (i = 0; i < brw->num_atoms; i++) {
 513          const struct brw_tracked_state *atom = brw->atoms[i];
 514
 515          if (check_state(state, &atom->dirty)) {
 516             atom->emit(brw);
 517          }
 518       }
 519    }
 520
 521    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 522       brw_update_dirty_count(mesa_bits, state->mesa);
 523       brw_update_dirty_count(brw_bits, state->brw);
 524       brw_update_dirty_count(cache_bits, state->cache);
 525       if (dirty_count++ % 1000 == 0) {
 526          brw_print_dirty_count(mesa_bits);
 527          brw_print_dirty_count(brw_bits);
 528          brw_print_dirty_count(cache_bits);
 529          fprintf(stderr, "\n");
 530       }
 531    }
 532
 533    memset(state, 0, sizeof(*state));
 534 }