src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 /* This is used to initialize brw->state.atoms[].  We could use this
  40  * list directly except for a single atom, brw_constant_buffer, which
  41  * has a .dirty value which changes according to the parameters of the
  42  * current fragment and vertex programs, and so cannot be a static
  43  * value.
  44  */
  45 static const struct brw_tracked_state *gen4_atoms[] =
  46 {
  47    &brw_check_fallback,
  48
  49    &brw_wm_input_sizes,
  50    &brw_vs_prog, /* must do before GS prog, state base address. */
  51    &brw_gs_prog, /* must do before state base address */
  52    &brw_clip_prog, /* must do before state base address */
  53    &brw_sf_prog, /* must do before state base address */
  54    &brw_wm_prog, /* must do before state base address */
  55
  56    /* Once all the programs are done, we know how large urb entry
  57     * sizes need to be and can decide if we need to change the urb
  58     * layout.
  59     */
  60    &brw_curbe_offsets,
  61    &brw_recalculate_urb_fence,
  62
  63    &brw_cc_vp,
  64    &brw_cc_unit,
  65
  66    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
  67    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
  68
  69    &brw_vs_surfaces,            /* must do before unit */
  70    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  71    &brw_wm_surfaces,            /* must do before samplers and unit */
  72    &brw_wm_binding_table,
  73    &brw_wm_samplers,
  74
  75    /* These set up state for brw_psp_urb_cbs */
  76    &brw_wm_unit,
  77    &brw_sf_vp,
  78    &brw_sf_unit,
  79    &brw_vs_unit,                /* always required, enabled or not */
  80    &brw_clip_unit,
  81    &brw_gs_unit,
  82
  83    /* Command packets:
  84     */
  85    &brw_invarient_state,
  86    &brw_state_base_address,
  87
  88    &brw_binding_table_pointers,
  89    &brw_blend_constant_color,
  90
  91    &brw_depthbuffer,
  92
  93    &brw_polygon_stipple,
  94    &brw_polygon_stipple_offset,
  95
  96    &brw_line_stipple,
  97    &brw_aa_line_parameters,
  98
  99    &brw_psp_urb_cbs,
 100
 101    &brw_drawing_rect,
 102    &brw_indices,
 103    &brw_index_buffer,
 104    &brw_vertices,
 105
 106    &brw_constant_buffer
 107 };
 108
 109 static const struct brw_tracked_state *gen6_atoms[] =
 110 {
 111    &brw_check_fallback,
 112
 113    &brw_wm_input_sizes,
 114    &brw_vs_prog, /* must do before state base address */
 115    &brw_gs_prog, /* must do before state base address */
 116    &brw_wm_prog, /* must do before state base address */
 117
 118    &gen6_clip_vp,
 119    &gen6_sf_vp,
 120
 121    /* Command packets: */
 122    &brw_invarient_state,
 123
 124    /* must do before binding table pointers, cc state ptrs */
 125    &brw_state_base_address,
 126
 127    &brw_cc_vp,
 128    &gen6_viewport_state,        /* must do after *_vp stages */
 129
 130    &gen6_urb,
 131    &gen6_blend_state,           /* must do before cc unit */
 132    &gen6_color_calc_state,      /* must do before cc unit */
 133    &gen6_depth_stencil_state,   /* must do before cc unit */
 134    &gen6_cc_state_pointers,
 135
 136    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 137    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 138    &gen6_vs_constants, /* Before vs_state */
 139    &gen6_wm_constants, /* Before wm_state */
 140
 141    &brw_vs_surfaces,            /* must do before unit */
 142    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 143    &brw_wm_surfaces,            /* must do before samplers and unit */
 144    &brw_wm_binding_table,
 145
 146    &brw_wm_samplers,
 147    &gen6_sampler_state,
 148
 149    &gen6_vs_state,
 150    &gen6_gs_state,
 151    &gen6_clip_state,
 152    &gen6_sf_state,
 153    &gen6_wm_state,
 154
 155    &gen6_scissor_state,
 156
 157    &gen6_binding_table_pointers,
 158
 159    &brw_depthbuffer,
 160
 161    &brw_polygon_stipple,
 162    &brw_polygon_stipple_offset,
 163
 164    &brw_line_stipple,
 165    &brw_aa_line_parameters,
 166
 167    &brw_drawing_rect,
 168
 169    &brw_indices,
 170    &brw_index_buffer,
 171    &brw_vertices,
 172 };
 173
 174 const struct brw_tracked_state *gen7_atoms[] =
 175 {
 176    &brw_check_fallback,
 177
 178    &brw_wm_input_sizes,
 179    &brw_vs_prog,
 180    &brw_gs_prog,
 181    &brw_wm_prog,
 182
 183    /* Command packets: */
 184    &brw_invarient_state,
 185
 186    /* must do before binding table pointers, cc state ptrs */
 187    &brw_state_base_address,
 188
 189    &brw_cc_vp,
 190    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
 191    &gen7_sf_clip_viewport,
 192
 193    &gen7_urb,
 194    &gen6_blend_state,           /* must do before cc unit */
 195    &gen6_color_calc_state,      /* must do before cc unit */
 196    &gen6_depth_stencil_state,   /* must do before cc unit */
 197    &gen7_blend_state_pointer,
 198    &gen7_cc_state_pointer,
 199    &gen7_depth_stencil_state_pointer,
 200
 201    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
 202    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
 203    &gen6_vs_constants, /* Before vs_state */
 204    &gen6_wm_constants, /* Before wm_surfaces and constant_buffer */
 205
 206    &brw_vs_surfaces,            /* must do before unit */
 207    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
 208    &brw_wm_surfaces,            /* must do before samplers and unit */
 209    &brw_wm_binding_table,
 210
 211    &gen7_samplers,
 212
 213    &gen7_disable_stages,
 214    &gen7_vs_state,
 215    &gen7_clip_state,
 216    &gen7_sbe_state,
 217    &gen7_sf_state,
 218    &gen7_wm_state,
 219    &gen7_ps_state,
 220
 221    &gen6_scissor_state,
 222
 223    &gen7_depthbuffer,
 224
 225    &brw_polygon_stipple,
 226    &brw_polygon_stipple_offset,
 227
 228    &brw_line_stipple,
 229    &brw_aa_line_parameters,
 230
 231    &brw_drawing_rect,
 232
 233    &brw_indices,
 234    &brw_index_buffer,
 235    &brw_vertices,
 236 };
 237
 238
 239 void brw_init_state( struct brw_context *brw )
 240 {
 241    const struct brw_tracked_state **atoms;
 242    int num_atoms;
 243
 244    brw_init_caches(brw);
 245
 246    if (brw->intel.gen >= 7) {
 247       atoms = gen7_atoms;
 248       num_atoms = ARRAY_SIZE(gen7_atoms);
 249    } else if (brw->intel.gen == 6) {
 250       atoms = gen6_atoms;
 251       num_atoms = ARRAY_SIZE(gen6_atoms);
 252    } else {
 253       atoms = gen4_atoms;
 254       num_atoms = ARRAY_SIZE(gen4_atoms);
 255    }
 256
 257    brw->atoms = atoms;
 258    brw->num_atoms = num_atoms;
 259
 260    while (num_atoms--) {
 261       assert((*atoms)->dirty.mesa |
 262              (*atoms)->dirty.brw |
 263              (*atoms)->dirty.cache);
 264       assert((*atoms)->emit);
 265       atoms++;
 266    }
 267 }
 268
 269
 270 void brw_destroy_state( struct brw_context *brw )
 271 {
 272    brw_destroy_caches(brw);
 273 }
 274
 275 /***********************************************************************
 276  */
 277
 278 static GLuint check_state( const struct brw_state_flags *a,
 279                            const struct brw_state_flags *b )
 280 {
 281    return ((a->mesa & b->mesa) |
 282            (a->brw & b->brw) |
 283            (a->cache & b->cache)) != 0;
 284 }
 285
 286 static void accumulate_state( struct brw_state_flags *a,
 287                               const struct brw_state_flags *b )
 288 {
 289    a->mesa |= b->mesa;
 290    a->brw |= b->brw;
 291    a->cache |= b->cache;
 292 }
 293
 294
 295 static void xor_states( struct brw_state_flags *result,
 296                              const struct brw_state_flags *a,
 297                               const struct brw_state_flags *b )
 298 {
 299    result->mesa = a->mesa ^ b->mesa;
 300    result->brw = a->brw ^ b->brw;
 301    result->cache = a->cache ^ b->cache;
 302 }
 303
 304 struct dirty_bit_map {
 305    uint32_t bit;
 306    char *name;
 307    uint32_t count;
 308 };
 309
 310 #define DEFINE_BIT(name) {name, #name, 0}
 311
 312 static struct dirty_bit_map mesa_bits[] = {
 313    DEFINE_BIT(_NEW_MODELVIEW),
 314    DEFINE_BIT(_NEW_PROJECTION),
 315    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 316    DEFINE_BIT(_NEW_COLOR),
 317    DEFINE_BIT(_NEW_DEPTH),
 318    DEFINE_BIT(_NEW_EVAL),
 319    DEFINE_BIT(_NEW_FOG),
 320    DEFINE_BIT(_NEW_HINT),
 321    DEFINE_BIT(_NEW_LIGHT),
 322    DEFINE_BIT(_NEW_LINE),
 323    DEFINE_BIT(_NEW_PIXEL),
 324    DEFINE_BIT(_NEW_POINT),
 325    DEFINE_BIT(_NEW_POLYGON),
 326    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 327    DEFINE_BIT(_NEW_SCISSOR),
 328    DEFINE_BIT(_NEW_STENCIL),
 329    DEFINE_BIT(_NEW_TEXTURE),
 330    DEFINE_BIT(_NEW_TRANSFORM),
 331    DEFINE_BIT(_NEW_VIEWPORT),
 332    DEFINE_BIT(_NEW_PACKUNPACK),
 333    DEFINE_BIT(_NEW_ARRAY),
 334    DEFINE_BIT(_NEW_RENDERMODE),
 335    DEFINE_BIT(_NEW_BUFFERS),
 336    DEFINE_BIT(_NEW_MULTISAMPLE),
 337    DEFINE_BIT(_NEW_TRACK_MATRIX),
 338    DEFINE_BIT(_NEW_PROGRAM),
 339    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 340    {0, 0, 0}
 341 };
 342
 343 static struct dirty_bit_map brw_bits[] = {
 344    DEFINE_BIT(BRW_NEW_URB_FENCE),
 345    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 346    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 347    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 348    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 349    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 350    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 351    DEFINE_BIT(BRW_NEW_CONTEXT),
 352    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 353    DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
 354    DEFINE_BIT(BRW_NEW_PSP),
 355    DEFINE_BIT(BRW_NEW_WM_SURFACES),
 356    DEFINE_BIT(BRW_NEW_INDICES),
 357    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 358    DEFINE_BIT(BRW_NEW_VERTICES),
 359    DEFINE_BIT(BRW_NEW_BATCH),
 360    DEFINE_BIT(BRW_NEW_NR_WM_SURFACES),
 361    DEFINE_BIT(BRW_NEW_NR_VS_SURFACES),
 362    DEFINE_BIT(BRW_NEW_VS_CONSTBUF),
 363    DEFINE_BIT(BRW_NEW_WM_CONSTBUF),
 364    DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
 365    DEFINE_BIT(BRW_NEW_GS_BINDING_TABLE),
 366    DEFINE_BIT(BRW_NEW_PS_BINDING_TABLE),
 367    DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
 368    {0, 0, 0}
 369 };
 370
 371 static struct dirty_bit_map cache_bits[] = {
 372    DEFINE_BIT(CACHE_NEW_BLEND_STATE),
 373    DEFINE_BIT(CACHE_NEW_CC_VP),
 374    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 375    DEFINE_BIT(CACHE_NEW_WM_PROG),
 376    DEFINE_BIT(CACHE_NEW_SAMPLER),
 377    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 378    DEFINE_BIT(CACHE_NEW_SF_PROG),
 379    DEFINE_BIT(CACHE_NEW_SF_VP),
 380    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 381    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 382    DEFINE_BIT(CACHE_NEW_VS_PROG),
 383    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 384    DEFINE_BIT(CACHE_NEW_GS_PROG),
 385    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 386    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 387    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 388    {0, 0, 0}
 389 };
 390
 391
 392 static void
 393 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 394 {
 395    int i;
 396
 397    for (i = 0; i < 32; i++) {
 398       if (bit_map[i].bit == 0)
 399          return;
 400
 401       if (bit_map[i].bit & bits)
 402          bit_map[i].count++;
 403    }
 404 }
 405
 406 static void
 407 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 408 {
 409    int i;
 410
 411    for (i = 0; i < 32; i++) {
 412       if (bit_map[i].bit == 0)
 413          return;
 414
 415       fprintf(stderr, "0x%08x: %12d (%s)\n",
 416               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 417    }
 418 }
 419
 420 /***********************************************************************
 421  * Emit all state:
 422  */
 423 void brw_upload_state(struct brw_context *brw)
 424 {
 425    struct gl_context *ctx = &brw->intel.ctx;
 426    struct intel_context *intel = &brw->intel;
 427    struct brw_state_flags *state = &brw->state.dirty;
 428    int i;
 429    static int dirty_count = 0;
 430
 431    state->mesa |= brw->intel.NewGLState;
 432    brw->intel.NewGLState = 0;
 433
 434    if (brw->emit_state_always) {
 435       state->mesa |= ~0;
 436       state->brw |= ~0;
 437       state->cache |= ~0;
 438    }
 439
 440    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 441       brw->fragment_program = ctx->FragmentProgram._Current;
 442       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 443    }
 444
 445    if (brw->vertex_program != ctx->VertexProgram._Current) {
 446       brw->vertex_program = ctx->VertexProgram._Current;
 447       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 448    }
 449
 450    if ((state->mesa | state->cache | state->brw) == 0)
 451       return;
 452
 453    brw->intel.Fallback = false; /* boolean, not bitfield */
 454
 455    intel_check_front_buffer_rendering(intel);
 456
 457    if (unlikely(INTEL_DEBUG)) {
 458       /* Debug version which enforces various sanity checks on the
 459        * state flags which are generated and checked to help ensure
 460        * state atoms are ordered correctly in the list.
 461        */
 462       struct brw_state_flags examined, prev;
 463       memset(&examined, 0, sizeof(examined));
 464       prev = *state;
 465
 466       for (i = 0; i < brw->num_atoms; i++) {
 467          const struct brw_tracked_state *atom = brw->atoms[i];
 468          struct brw_state_flags generated;
 469
 470          if (brw->intel.Fallback)
 471             break;
 472
 473          if (check_state(state, &atom->dirty)) {
 474             atom->emit(brw);
 475          }
 476
 477          accumulate_state(&examined, &atom->dirty);
 478
 479          /* generated = (prev ^ state)
 480           * if (examined & generated)
 481           *     fail;
 482           */
 483          xor_states(&generated, &prev, state);
 484          assert(!check_state(&examined, &generated));
 485          prev = *state;
 486       }
 487    }
 488    else {
 489       for (i = 0; i < brw->num_atoms; i++) {
 490          const struct brw_tracked_state *atom = brw->atoms[i];
 491
 492          if (brw->intel.Fallback)
 493             break;
 494
 495          if (check_state(state, &atom->dirty)) {
 496             atom->emit(brw);
 497          }
 498       }
 499    }
 500
 501    if (unlikely(INTEL_DEBUG & DEBUG_STATE)) {
 502       brw_update_dirty_count(mesa_bits, state->mesa);
 503       brw_update_dirty_count(brw_bits, state->brw);
 504       brw_update_dirty_count(cache_bits, state->cache);
 505       if (dirty_count++ % 1000 == 0) {
 506          brw_print_dirty_count(mesa_bits, state->mesa);
 507          brw_print_dirty_count(brw_bits, state->brw);
 508          brw_print_dirty_count(cache_bits, state->cache);
 509          fprintf(stderr, "\n");
 510       }
 511    }
 512
 513    if (!brw->intel.Fallback)
 514       memset(state, 0, sizeof(*state));
 515 }