2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "intel_batchbuffer.h"
37 #include "intel_buffers.h"
38 #include "intel_chipset.h"
40 /* This is used to initialize brw->state.atoms[]. We could use this
41 * list directly except for a single atom, brw_constant_buffer, which
42 * has a .dirty value which changes according to the parameters of the
43 * current fragment and vertex programs, and so cannot be a static
46 static const struct brw_tracked_state
*gen4_atoms
[] =
57 /* Once all the programs are done, we know how large urb entry
58 * sizes need to be and can decide if we need to change the urb
62 &brw_recalculate_urb_fence
,
67 &brw_vs_surfaces
, /* must do before unit */
68 &brw_wm_constant_surface
, /* must do before wm surfaces/bind bo */
69 &brw_wm_surfaces
, /* must do before samplers and unit */
75 &brw_vs_unit
, /* always required, enabled or not */
82 &brw_state_base_address
,
84 &brw_binding_table_pointers
,
85 &brw_blend_constant_color
,
90 &brw_polygon_stipple_offset
,
93 &brw_aa_line_parameters
,
105 const struct brw_tracked_state
*gen6_atoms
[] =
118 /* Command packets: */
119 &brw_invarient_state
,
121 &gen6_viewport_state
, /* must do after *_vp stages */
124 &gen6_blend_state
, /* must do before cc unit */
125 &gen6_color_calc_state
, /* must do before cc unit */
126 &gen6_depth_stencil_state
, /* must do before cc unit */
127 &gen6_cc_state_pointers
,
129 &brw_vs_surfaces
, /* must do before unit */
130 &brw_wm_constant_surface
, /* must do before wm surfaces/bind bo */
131 &brw_wm_surfaces
, /* must do before samplers and unit */
144 &brw_state_base_address
,
146 &gen6_binding_table_pointers
,
150 &brw_polygon_stipple
,
151 &brw_polygon_stipple_offset
,
154 &brw_aa_line_parameters
,
163 void brw_init_state( struct brw_context
*brw
)
165 brw_init_caches(brw
);
169 void brw_destroy_state( struct brw_context
*brw
)
171 brw_destroy_caches(brw
);
172 brw_destroy_batch_cache(brw
);
175 /***********************************************************************
178 static GLboolean
check_state( const struct brw_state_flags
*a
,
179 const struct brw_state_flags
*b
)
181 return ((a
->mesa
& b
->mesa
) ||
183 (a
->cache
& b
->cache
));
186 static void accumulate_state( struct brw_state_flags
*a
,
187 const struct brw_state_flags
*b
)
191 a
->cache
|= b
->cache
;
195 static void xor_states( struct brw_state_flags
*result
,
196 const struct brw_state_flags
*a
,
197 const struct brw_state_flags
*b
)
199 result
->mesa
= a
->mesa
^ b
->mesa
;
200 result
->brw
= a
->brw
^ b
->brw
;
201 result
->cache
= a
->cache
^ b
->cache
;
205 brw_clear_validated_bos(struct brw_context
*brw
)
209 /* Clear the last round of validated bos */
210 for (i
= 0; i
< brw
->state
.validated_bo_count
; i
++) {
211 dri_bo_unreference(brw
->state
.validated_bos
[i
]);
212 brw
->state
.validated_bos
[i
] = NULL
;
214 brw
->state
.validated_bo_count
= 0;
217 struct dirty_bit_map
{
223 #define DEFINE_BIT(name) {name, #name, 0}
225 static struct dirty_bit_map mesa_bits
[] = {
226 DEFINE_BIT(_NEW_MODELVIEW
),
227 DEFINE_BIT(_NEW_PROJECTION
),
228 DEFINE_BIT(_NEW_TEXTURE_MATRIX
),
229 DEFINE_BIT(_NEW_COLOR_MATRIX
),
230 DEFINE_BIT(_NEW_ACCUM
),
231 DEFINE_BIT(_NEW_COLOR
),
232 DEFINE_BIT(_NEW_DEPTH
),
233 DEFINE_BIT(_NEW_EVAL
),
234 DEFINE_BIT(_NEW_FOG
),
235 DEFINE_BIT(_NEW_HINT
),
236 DEFINE_BIT(_NEW_LIGHT
),
237 DEFINE_BIT(_NEW_LINE
),
238 DEFINE_BIT(_NEW_PIXEL
),
239 DEFINE_BIT(_NEW_POINT
),
240 DEFINE_BIT(_NEW_POLYGON
),
241 DEFINE_BIT(_NEW_POLYGONSTIPPLE
),
242 DEFINE_BIT(_NEW_SCISSOR
),
243 DEFINE_BIT(_NEW_STENCIL
),
244 DEFINE_BIT(_NEW_TEXTURE
),
245 DEFINE_BIT(_NEW_TRANSFORM
),
246 DEFINE_BIT(_NEW_VIEWPORT
),
247 DEFINE_BIT(_NEW_PACKUNPACK
),
248 DEFINE_BIT(_NEW_ARRAY
),
249 DEFINE_BIT(_NEW_RENDERMODE
),
250 DEFINE_BIT(_NEW_BUFFERS
),
251 DEFINE_BIT(_NEW_MULTISAMPLE
),
252 DEFINE_BIT(_NEW_TRACK_MATRIX
),
253 DEFINE_BIT(_NEW_PROGRAM
),
254 DEFINE_BIT(_NEW_PROGRAM_CONSTANTS
),
258 static struct dirty_bit_map brw_bits
[] = {
259 DEFINE_BIT(BRW_NEW_URB_FENCE
),
260 DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM
),
261 DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM
),
262 DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS
),
263 DEFINE_BIT(BRW_NEW_CURBE_OFFSETS
),
264 DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE
),
265 DEFINE_BIT(BRW_NEW_PRIMITIVE
),
266 DEFINE_BIT(BRW_NEW_CONTEXT
),
267 DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS
),
268 DEFINE_BIT(BRW_NEW_PSP
),
269 DEFINE_BIT(BRW_NEW_INDICES
),
270 DEFINE_BIT(BRW_NEW_INDEX_BUFFER
),
271 DEFINE_BIT(BRW_NEW_VERTICES
),
272 DEFINE_BIT(BRW_NEW_BATCH
),
273 DEFINE_BIT(BRW_NEW_DEPTH_BUFFER
),
277 static struct dirty_bit_map cache_bits
[] = {
278 DEFINE_BIT(CACHE_NEW_BLEND_STATE
),
279 DEFINE_BIT(CACHE_NEW_CC_VP
),
280 DEFINE_BIT(CACHE_NEW_CC_UNIT
),
281 DEFINE_BIT(CACHE_NEW_WM_PROG
),
282 DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR
),
283 DEFINE_BIT(CACHE_NEW_SAMPLER
),
284 DEFINE_BIT(CACHE_NEW_WM_UNIT
),
285 DEFINE_BIT(CACHE_NEW_SF_PROG
),
286 DEFINE_BIT(CACHE_NEW_SF_VP
),
287 DEFINE_BIT(CACHE_NEW_SF_UNIT
),
288 DEFINE_BIT(CACHE_NEW_VS_UNIT
),
289 DEFINE_BIT(CACHE_NEW_VS_PROG
),
290 DEFINE_BIT(CACHE_NEW_GS_UNIT
),
291 DEFINE_BIT(CACHE_NEW_GS_PROG
),
292 DEFINE_BIT(CACHE_NEW_CLIP_VP
),
293 DEFINE_BIT(CACHE_NEW_CLIP_UNIT
),
294 DEFINE_BIT(CACHE_NEW_CLIP_PROG
),
295 DEFINE_BIT(CACHE_NEW_SURFACE
),
296 DEFINE_BIT(CACHE_NEW_SURF_BIND
),
302 brw_update_dirty_count(struct dirty_bit_map
*bit_map
, int32_t bits
)
306 for (i
= 0; i
< 32; i
++) {
307 if (bit_map
[i
].bit
== 0)
310 if (bit_map
[i
].bit
& bits
)
316 brw_print_dirty_count(struct dirty_bit_map
*bit_map
, int32_t bits
)
320 for (i
= 0; i
< 32; i
++) {
321 if (bit_map
[i
].bit
== 0)
324 fprintf(stderr
, "0x%08x: %12d (%s)\n",
325 bit_map
[i
].bit
, bit_map
[i
].count
, bit_map
[i
].name
);
329 /***********************************************************************
332 void brw_validate_state( struct brw_context
*brw
)
334 GLcontext
*ctx
= &brw
->intel
.ctx
;
335 struct intel_context
*intel
= &brw
->intel
;
336 struct brw_state_flags
*state
= &brw
->state
.dirty
;
338 const struct brw_tracked_state
**atoms
;
341 brw_clear_validated_bos(brw
);
343 state
->mesa
|= brw
->intel
.NewGLState
;
344 brw
->intel
.NewGLState
= 0;
346 brw_add_validated_bo(brw
, intel
->batch
->buf
);
348 if (IS_GEN6(intel
->intelScreen
->deviceID
)) {
350 num_atoms
= ARRAY_SIZE(gen6_atoms
);
353 num_atoms
= ARRAY_SIZE(gen4_atoms
);
356 if (brw
->emit_state_always
) {
362 if (brw
->fragment_program
!= ctx
->FragmentProgram
._Current
) {
363 brw
->fragment_program
= ctx
->FragmentProgram
._Current
;
364 brw
->state
.dirty
.brw
|= BRW_NEW_FRAGMENT_PROGRAM
;
367 if (brw
->vertex_program
!= ctx
->VertexProgram
._Current
) {
368 brw
->vertex_program
= ctx
->VertexProgram
._Current
;
369 brw
->state
.dirty
.brw
|= BRW_NEW_VERTEX_PROGRAM
;
372 if (state
->mesa
== 0 &&
377 if (brw
->state
.dirty
.brw
& BRW_NEW_CONTEXT
)
378 brw_clear_batch_cache(brw
);
380 brw
->intel
.Fallback
= GL_FALSE
; /* boolean, not bitfield */
382 /* do prepare stage for all atoms */
383 for (i
= 0; i
< num_atoms
; i
++) {
384 const struct brw_tracked_state
*atom
= atoms
[i
];
386 if (brw
->intel
.Fallback
)
389 if (check_state(state
, &atom
->dirty
)) {
396 intel_check_front_buffer_rendering(intel
);
398 /* Make sure that the textures which are referenced by the current
399 * brw fragment program are actually present/valid.
400 * If this fails, we can experience GPU lock-ups.
403 const struct brw_fragment_program
*fp
;
404 fp
= brw_fragment_program_const(brw
->fragment_program
);
406 assert((fp
->tex_units_used
& ctx
->Texture
._EnabledUnits
)
407 == fp
->tex_units_used
);
413 void brw_upload_state(struct brw_context
*brw
)
415 struct intel_context
*intel
= &brw
->intel
;
416 struct brw_state_flags
*state
= &brw
->state
.dirty
;
418 static int dirty_count
= 0;
419 const struct brw_tracked_state
**atoms
;
422 if (IS_GEN6(intel
->intelScreen
->deviceID
)) {
424 num_atoms
= ARRAY_SIZE(gen6_atoms
);
427 num_atoms
= ARRAY_SIZE(gen4_atoms
);
430 brw_clear_validated_bos(brw
);
433 /* Debug version which enforces various sanity checks on the
434 * state flags which are generated and checked to help ensure
435 * state atoms are ordered correctly in the list.
437 struct brw_state_flags examined
, prev
;
438 memset(&examined
, 0, sizeof(examined
));
441 for (i
= 0; i
< num_atoms
; i
++) {
442 const struct brw_tracked_state
*atom
= atoms
[i
];
443 struct brw_state_flags generated
;
445 assert(atom
->dirty
.mesa
||
449 if (brw
->intel
.Fallback
)
452 if (check_state(state
, &atom
->dirty
)) {
458 accumulate_state(&examined
, &atom
->dirty
);
460 /* generated = (prev ^ state)
461 * if (examined & generated)
464 xor_states(&generated
, &prev
, state
);
465 assert(!check_state(&examined
, &generated
));
470 for (i
= 0; i
< num_atoms
; i
++) {
471 const struct brw_tracked_state
*atom
= atoms
[i
];
473 if (brw
->intel
.Fallback
)
476 if (check_state(state
, &atom
->dirty
)) {
484 if (INTEL_DEBUG
& DEBUG_STATE
) {
485 brw_update_dirty_count(mesa_bits
, state
->mesa
);
486 brw_update_dirty_count(brw_bits
, state
->brw
);
487 brw_update_dirty_count(cache_bits
, state
->cache
);
488 if (dirty_count
++ % 1000 == 0) {
489 brw_print_dirty_count(mesa_bits
, state
->mesa
);
490 brw_print_dirty_count(brw_bits
, state
->brw
);
491 brw_print_dirty_count(cache_bits
, state
->cache
);
492 fprintf(stderr
, "\n");
496 if (!brw
->intel
.Fallback
)
497 memset(state
, 0, sizeof(*state
));